SONY CXL5514M

CXL5514M/P
CMOS-CCD 1H Delay Line for PAL
Description
The CXL5514M/P are CMOS-CCD delay line ICs
designed for processing video signals. This ICs
provide a 1H delay time for PAL signals including
the external lowpass filter.
Features
• Single 5V power supply
• Low power consumption
• Built-in peripheral circuit
• Built-in tripling PLL circuit
• Sync tip clamp mode
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VDD
+6
• Operating temperature Topr
–10 to +60
• Storage temperature Tstg
–55 to +150
• Allowable power dissipation
PD
CXL5514M 350
CXL5514P 480
CXL5514M
8 pin SOP (Plastic)
CXL5514P
8 pin DIP (Plastic)
Input Signal Amplitude
VSIG 500mVp-p (Typ.), 575mVp-p (Max.)
(at internal clamp condition)
V
°C
°C
Functions
• 848-bit CCD register
• Clock driver
• Auto-bias circuit
• Sync tip clamp circuit
• Sample and hold circuit
• Tripling PLL circuit
• Inverted output
mW
mW
Recommended Operating Range (Ta = 25°C)
VDD 5V ± 5%
Structure
CMOS-CCD
Recommended Clock Conditions (Ta = 25°C)
• Input clock amplitude
VCLK 0.2 to 1.0Vp-p (0.4Vp-p Typ.)
• Clock frequency
fCLK
4.433619MHz
• Input clock waveform Sine wave
Block Diagram and Pin Configuration (Top View)
VDD
VCO OUT
VCO IN
CLK
8
7
6
5
PLL
Auto-bias circuit
Timing circuit
Clamp circuit
CCD
(848 bit)
Clock driver
Output circuit
(S/H 1 bit)
Bias circuit A
Bias circuit B
1
2
3
4
IN
AB
OUT
VSS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E94903-ST
CXL5514M/P
Pin Description
Pin No.
Symbol
I/O
Description
1
IN
I
Signal input
2
AB
O
Auto-bias DC output
3
OUT
O
Signal output
4
VSS
—
GND
5
CLK
I
Clock input (fsc)
6
VCO IN
I
VCO input
7
VCO OUT
O
VCO output (3fsc)
8
VDD
—
5V power supply
Impedance
>10KΩ
40 to 500Ω
>10KΩ
Electrical Characteristics
(Ta = 25°C, VDD = 5V, fCLK = 4.433619MHz, VCLK = 400mVp-p, sine wave)
See “Electrical Characteristics Test Circuit”.
SW conditions
Min.
Typ.
Max.
—
10
15
20
mA
1
b
–2
0
2
dB
2
200kz ←→ 4.434MHz
b ←→ c
150mVp-p Sine wave
b
–2.7
–1.7
–0.7
dB
3
Symbol
Conditions
Supply current
IDD
—
Low frequency gain
GL
200kHz
500mVp-p
Sine wave
Frequency response
fR
Item
1
2
a
a
Unit NOTE
Differential gain
DG
5-staircase wave
(See Note 4.)
d
c
0
3
5
%
4
Differential phase
DP
5-staircase wave
(See Note 4.)
d
c
0
3
5
degree
4
S/H pulse coupling
CP
No signal input
f
a
—
—
350
mVp-p
5
S/N ratio
SN
50% white video signal
(See Note 6.)
e
d
52
56
—
dB
6
–2–
CXL5514M/P
NOTE
1. This is the IC supply current value during clock and signal input.
2. GL is the output gain of OUT pin when a 500mVp-p, 200kHz sine wave is fed to IN pin.
GL = 20 log
OUT pin output voltage [mVp-p]
[dB]
500 [mVp-p]
3. Indicates the dissipation at 4.434MHz in relation to 200kHz. From the output voltage at OUT pin when a
150mVp-p, 200kHz sine wave is fed to IN pin, and from the output voltage at OUT pin when a 150mVp-p,
4.434MHz sine wave is fed to the same, calculation is made according to the following formula.
fR = 20 log
OUT pin output voltage (4.434MHz) [mVp-p]
[dB]
OUT pin output voltage (200kHz) [mVp-p]
4. In Fig. below, the differential gain (DG) and the differential phase (DP) are tested with a vector scope when
the 5-staircase wave is fed.
150mV
350mV
500mV
150mV
1H 64µs
5. Leakage of internal clock components and related high frequency component to the output signal, during
no signal input, is tested.
Test value
[mVp-p]
–3–
CXL5514M/P
6. S/N ratio during a 50% white video signal input shown in Fig. below is tested at the video noise meter, in
BPF 100kHz to 5MHz, Sub Carrier Trap mode.
175mV
325mV
150mV
1H 64µs
CLOCK
fSC (4.433619MHz) Sine wave
400mVp-p (Typ.)
–4–
–5–
50% white
video signal
5-staircase wave
4.434MHz
150mVp-p
Sine wave
200kHz
150mVp-p
Sine wave
200kHz
500mVp-p
Sine wave
f
e
d
c SW1
b
a
Electrical Characteristics Test Circuit
1µ
5V
1M
8
6.8µ
7
6
0.1µ
2
1
4
VSS
–50
–50
SW2
BPF
Note 2)
LPF
Note1)
BPF frequency response
d
c
b
a
×3
×3
50 200
6M 13.3M
Frequency [Hz]
[dB]
Note 2)
2.2k
+15V
0
–3
6M 13.3M
Frequency [Hz]
LPF frequency response
0.1µ
3
OUT
0
–3
[dB]
Note1)
AB
CXL5514M/P
5
CLK
0.1µ
fsc (4.433619MHz)
400mVp-p
Sine wave
VCO OUT VCO IN
IN
VDD
2200p
Noise meter
Vector scope
Spectrum analyzer
Oscilloscope
CXL5514M/P
Input
Application Circuit
7
1µ
–6–
1M
1.8k
AB
2
IN
1
2.2k
3fsc OUT
0.1µ
3
OUT
5
1µ
4
VSS
CLK
0.1µ
1k
470
Transistor used
NPN: 2SA403
56k
33k
LPF
Transistor used
NPN: 2SC403
2.2k
Output
5V
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
2SC403
5V
6
0.1µ
fsc (4.433619MHz)
400mVp-p
Sine wave
VCO IN
CXL5514M/P
7
VCO OUT
8
VDD
6.8µ
When VCO OUT (7Pin) in use
5V
2200p
CXL5514M/P
CXL5514M/P
Example of Representative Characteristics
Supply current vs. Supply voltage
Low frequency Gain vs. Supply voltage
1
Low frequency Gain [dB]
Supply current [mA]
20
15
10
4.75
5
Supply voltage [V]
0
–1
–2
4.75
5.25
Frequency response vs. Supply voltage
5
Supply voltage [V]
5.25
Differential gain vs. Supply voltage
0
10
Differential gain [%]
Frequency response [dB]
8
–1
–2
6
4
2
–3
4.75
5
Supply voltage [V]
0
4.75
5.25
Supply current vs. Ambient temperature
5
Supply voltage [V]
5.25
Low frequency Gain vs. Ambient temperature
20
1
Low frequency Gain [dB]
Supply current [mA]
18
16
14
0
–1
12
10
–20
0
20
40
60
–2
–20
80
0
20
40
Ambient temperature [°C]
Ambient temperature [°C]
–7–
60
80
CXL5514M/P
Frequency response vs. Ambient temperature
Differential gain vs. Ambient temperature
0
10
Differential gain [%]
–1
–2
6
4
2
–3
–20
0
20
40
60
Ambient temperature [°C]
0
–20
80
0
20
40
60
Ambient temperature [°C]
Frequency response
2
0
–2
Gain [dB]
Frequency response [dB]
8
–4
–6
–8
–10
10k
100k
1M
Frequency [Hz]
–8–
10M
80
CXL5514M/P
Package Outline
Unit : mm
CXL5514M
8PIN SOP (PLASTIC)
+ 0.4
1.25 – 0.15
+ 0.4
5.0 – 0.1
0.10
8
5
+ 0.3
4.4 – 0.1
6.4 ± 0.4
A
4
1
+ 0.1
0.15 – 0.05
1.27
+ 0.1
0.4 – 0.05
0.5 ± 0.2
+ 0.15
0.1 – 0.1
± 0.12 M
0° to 10°
DETAILA
PACKAGE STRUCTURE
SONY CODE
SOP-8P-L03
EIAJ CODE
∗SOP008-P-0225-A
JEDEC CODE
MOLDING COMPOUND
EPOXY / PHENOL RESIN
LEAD TREATMENT
SOLDER PLATING
LEAD MATERIAL
42 ALLOY
PACKAGE WEIGHT
0.1g
CXL5514P
+ 0.3
6.4 – 0.1
+ 0.4
9.4 – 0.1
5
7.62
8
+ 0.1
0.05
0.25 –
8PIN DIP (PLASTIC) 300mil
0° to 15°
4
1
+ 0.4
3.7 – 0.1
3.0 MIN
0.5 MIN
2.54
0.5 ± 0.1
1.2 ± 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
DIP-8P-01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
∗DIP008-P-0300-A
LEAD MATERIAL
COPPER ALLOY
PACKAGE WEIGHT
0.5g
JEDEC CODE
–9–