CXL1503M/1505M CMOS-CCD Signal Processor Description CXL1503M/1505M are CMOS-CCD signal processors developed for CCD camera complementary color filter array processing system. CXL1503M 1H × 4 301.5 bit CCD delay line CXL1505M 1H × 4 453.5 bit CCD delay line 24 pin SOP (Plastic) Features • Single power supply 5V • Low power consumption CXL1503M 100mW (Typ.) CXL1505M 150mW (Typ.) • Built-in peripheral circuits • Built-in CDS (Correlated Double Sampling) circuit Function • Clock driver • Autobias circuit (center and black) • Pedestal clamp circuit • CDS circuit Structure CMOS-CCD Absolute Maximum Ratings (Ta = 25°C) 6 V • Supply voltage VDD • Operating temperature Topr –10 to +60 °C • Storage temperature Tstg –55 to +150 °C • Allowable power dissipation PD 500 mW Recommended Operating Conditions (Ta = 25°C) Supply voltage VDD 5 ± 5% V Recommended Clock Conditions (Ta = 25°C) Item Symbol Min. Typ. Max. Unit Clock voltage Low VL 0 1.0 V Clock voltage High VH VDD – 1.0 VDD V Remarks CXL1503M fCL 4.77 MHz NTSC: 910fH/3 CCIR: 908fH/3 CXL1505M fCL 7.16 MHz NTSC: 455fH CCIR: 454fH Clock frequency Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E89174A03-PS CXL1503M/1505M ABCN 21 XDL2 VDD VDD VSS VSS VDD VSS Pin Configuration (Top View) XDL1 Block Diagram 19 18 4 8 1 16 20 17 A. B CENTER VSS 1 ABBL 3 A. B BLACK P. D PG GEN. CLP DL A CDS-OUTPUT CIRCUIT 15 OUT A CLP DL B CDS-OUTPUT CIRCUIT 13 OUT B CLP CDS-OUTPUT CIRCUIT DL C 11 OUT C CDS-OUTPUT CIRCUIT DL D POTENTIAL CONTROL IS 12 10 14 CDS 5 19 XDL1 CLP 7 18 XDL2 VDD 8 17 VSS OUT D 9 16 VSS 15 OUT A 14 CDS OUT C 11 13 OUT B 9 OUT D BIAS. N.C. 7 CLP INPUT SOURCE VGG WAVE FORM IN D 6 N.C. 12 PG GEN. CLP 20 VDD VGG 10 PG GEN. IN D 6 21 ABCN IS 5 PG GEN. IN C 2 22 IN A VDD 4 P. D 5V IN B 24 23 DCAB ABBL 3 DCAB 23 IN A 22 24 IN B IN C 2 TIMING GENERATOR Pin Description No. Symbol 1, 16, 17 VSS — Impedance (Ω) Description I/O GND 2 IN C I Signal input C channel > 100k (at no clamp) 3 ABBL O Autobias DC output for Y signal 2k to 20k VDD — 5V power supply 5 IS O Input source DC output 5k 6 IN D I Signal input D channel > 100k (at no clamp) 7 CLP I Clamp pulse input > 100k 9 OUT D O Signal output D channel 50 to 500 10 VGG O Gate bias DC output 2k to 10k 11 OUT C O Signal output C channel 50 to 500 12 N.C. — 13 OUT B O Signal output B channel 50 to 500 14 CDS O DC output for CDS 500 to 5k 15 OUT A O Signal output A channel 50 to 500 18 XDL2 I Clock pulse input 2 > 100k 19 XDL1 I Clock pulse input 1 > 100k 21 ABCN O Autobias DC output for C signal 2k to 20k 22 IN A I Signal input A channel > 100k (at no clamp) 23 DCAB I DC bias input for A and B channel > 100k 24 IN B I Signal input B channel > 100k (at no clamp) 4, 8, 20 — –2– V5 A1 V6 VGG IDD IG Output circuit bias level Supply∗1 current –3– ↓ a 0 0 CRT ∗1 Standerd values are different between CXL1503M and CXL1505M. Cross talk between channels 0 (Note 2) 0 1 1 1 5 5 Output amplitude (SIN 1MHz, 100mVp-p) –1.8 –0.8 Output amplitude (SIN 100kHz, 100mVp-p) –1.5 –0.4 (Note 1) 20 log A, Bch → V1 (Note 4) C, Dch → V2 – 0.2V a→ ←b ↓ 0 a to d a to d 30 20 0.8 2.3 0.6 2.2 2.0 40 35 3.0 3.5 3.0 4.2 4.0 mA V V V V V 3 5 5 15 12 — — % % % % % dB A, Bch → V1 Output amplitude (mVp-p) 20 log C, Dch → –4.5 –3.5 –0.5 dB Input amplitude (SIN 100kHz, 100mVp-p) V2 – 0.2V a a (Note 3) b b a to d a to d Cch → ← Dch ∆LCD a b b b — — (Note 3) V6 V6 c b V1 0.3 a a a a a 1.2 a a a a a 0.3 a a a a a 1.2 a a b a b 1.0 a a b Min. Typ. Max. Unit fCL = 4.77MHz (CXL1503M) fCL = 7.16MHz (CXL1505M) a Conditions (Ta = 25°C, VDD = 5.0V, VSS = 0V) Ach → ← Bch ∆LAB ∆G Insertion gain difference between channels Linearity difference between channels Lin. CXL1505M CXL1503M Linearity Frequency∗1 response CXL1505M V6 V4 CDS CDS source level fG V3 IS Input source level Insertion gain V2 ABBL Autobias black level CXL1503M V1 Bias condition SW position Test Point SW1 SW2 SW3 SW4 to 7 E1 ABCN Symbol Autobias center level Item Electrical Characteristics CXL1503M/1505M CXL1503M/1505M Notes) 1. Linearity testing For A channel and B channel, set input bias E1 to ABCN + 0.2 [V] first, and then set it to ABCN [V] and ABCN – 0.2 [V]. Then input a sine wave of 100kHz and 100mVp-p, and compare the three output amplitudes. For C channel and D channel, set input bias E1 to ABBL – 0.4 [V] first, and then set it to ABBL – 0.2 [V] and ABBL [V]. Then input a sine wave of 100kHz and 100mVp-p, and compare the three output amplitudes. The maximum output amplitude for the respective A, B, C and D channels is taken as Sout max. and the minimum output amplitude as Sout min. The linearity of the respective channels is defined as Lin = Sout max – Sout min × 200 [%] Sout max + Sout min 2. Calculation of insertion gain difference As the max. insertion gain among A, B, C and D channels' is taken as Gmax and the min. as Gmin., the insertion gain difference between channels becomes: ∆G = ABS (1 – 10 ( Gmax – Gmin 20 ) ) × 100 [%] 3. Calculation of linearity difference Define A channel linearity as LA, and B channel linearity as LB. We obtain the difference ∆LAB as follows. ∆LAB = LA – LB [%] Similarly we obtain the linearity difference ∆LCD of C channel and D channel as follows. ∆LCD = LC – LD [%] 4. Crosstalk calculation We take CRTa as: A channel crosstalk value only during B channel input CRTb as: B channel crosstalk value only during A channel input CRTc as: C channel crosstalk value only during D channel input CRTd as: D channel crosstalk value only during C channel input The crosstalk value of respective channels becomes: CRTa to d = Crosstalk component × 100 [%] Each channel output value –4– CXL1503M/1505M Clock Waveform Timing ∗(140) 210ns ∗(52.5) 87.5ns 10ns 10ns 90% 90% 50% 50% 10% 10% XDL1 ∗( ) is for CXL1505M. ∗(52.5) 17.5ns 87.5ns 10ns XDL2 10ns 90% 90% 50% 50% 10% 10% –5– CXL1503M/1505M Electrical Characteristics Test Circuit a b a a 100kHz, 100mVp-p sine wave c SW1 a No signal b 5V 1MHz, 100mVp-p sine wave 3.3k a V1 b b b SW7 SW6 SW5 SW4 1µ 16V 23 24 22 V4 5V XDL1 XDL2 21 19 20 18 3.3k 1µ 16V 17 14 15 16 a 13 SW3 b c 5V 1 5 4 3 2 6 8 7 9 11 10 1µ 16V 1µ 16V 1µ 16V ×1 LPF d 3.3k 12 (NC) ×1 V5 V6 5V 3.3k V2 10k 10k 10k 10k A1 a VDD 5V E1 SW2 V3 b Application Circuit 5V Input B Input A VDD 3.3k XDL XDL 1 2 Output A 4.7µ 16V 5V 0.1µ 0.1µ 16V 16V 1µ 16V 3.3k 1µ 16V 24 23 22 100p 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 Output B 5V 0.1µ 1µ 16V 16V 1µ 16V 3.3k Output C (NC) 0.1µ 16V 1µ 16V 5V 100p 4.7µ 16V Input C VDD 100p 4.7µ 16V Input CLP D Input 3.3k Output D VDD Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. –6– CXL1503M/1505M Frequency response –2 Insertion gain [dB] –3 –4 –5 –6 –7 10k 100k Signal frequency [Hz] Autobias center level vs. Supply voltage 3 ABBL – Autobias black level [V] ABCN – Autobias center level [V] 10M Autobias black level vs. Supply voltage 3 2 1 2 1 4.5 5 VDD – Supply voltage [V] 5.5 4.5 Insertion gain vs. Supply voltage 5 VDD – Supply voltage [V] 5.5 Linearity vs. Supply voltage 10 Lin – Linearity [%] 0 IG – Insertion gain [dB] 1M –2.5 –5 5 0 4.5 5 VDD – Supply voltage [V] 5.5 4.5 –7– 5 VDD – Supply voltage [V] 5.5 CXL1503M/1505M Frequency response vs. Supply voltage Autobias center level vs. Ambient temperature 3 ABCN – Autobias center level [V] fG – Frequency response [dB] 0 –1 –2 4.5 2 1 5 VDD – Supply voltage [V] 0 5.5 Autobias black level vs. Ambient temperature 60 Insertion gain vs. Ambient temperature IG – Insertion gain [dB] ABBL – Autobias black level [V] 40 0 3 2 1 –2.5 –5 0 20 40 Ta – Ambient temperature [°C] 0 20 40 60 Ta – Ambient temperature [°C] 60 Linearity vs. Ambient temperature Frequency response vs. Ambient temperature 10 0 fG – Frequency response [dB] Lin – Linearity [%] 20 Ta – Ambient temperature [°C] 5 0 –1 –2 0 20 40 60 Ta – Ambient temperature [°C] 0 20 40 60 Ta – Ambient temperature [°C] –8– CXL1503M/1505M Package Outline Unit: mm 24PIN SOP (PLASTIC) + 0.4 1.85 – 0.15 + 0.4 15.0 – 0.1 0.15 24 0.24 6.9 + 0.2 0.1 – 0.05 1.27 + 0.1 0.2 – 0.05 0.5 ± 0.2 12 1 0.45 ± 0.1 7.9 ± 0.4 + 0.3 5.3 – 0.1 13 M PACKAGE STRUCTURE MOLDING COMPOUND EPOXY RESIN SONY CODE SOP-24P-L01 LEAD TREATMENT SOLDER PLATING EIAJ CODE SOP024-P-0300 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.3g JEDEC CODE –9–