SONY CXL5505P

CXL5505M/P
CMOS-CCD 1H Delay Line for PAL
Description
The CXL5505M/P are CMOS-CCD delay line ICs
that provide 1H delay time for PAL signals including
the external low-pass filter.
CXL5505M
14 pin SOP (Plastic)
CXL5505P
14 pin DIP (Plastic)
Features
• Single 5V power supply
• Low power consumption 100mW (Typ.)
• Built-in peripheral circuits
• Built-in quadruple PLL circuit
Functions
• 1130-bit CCD register
• Clock driver
• Auto-bias circuit
• Input clamp circuit
• Sample-and-hold circuit
• PLL circuit
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VDD
6
V
• Operating temperature Topr
–10 to +60
°C
• Storage temperature Tstg
–55 to +150 °C
• Allowable power dissipation
PD
CXL5505M
400
mW
CXL5505P
800
mW
Structure
CMOS-CCD
Recommended Operating Condition (Ta = 25°C)
Supply voltage
VDD
5 ± 5%
V
Recommended Clock Conditions (Ta = 25°C)
• Input clock amplitude VCLK
0.3 to 1.0
Vp-p
(0.5Vp-p typ.)
• Clock frequency
fCLK
4.433619
MHz
• Input clock waveform Sine wave
Input Signal Amplitude
VSIG 575mVp-p (Max.) (at internal clamp condition)
VSS
AB
VDD
VCO IN
PC OUT
VDD
CLK
Blook Diagram and Pin Configuration (Top View)
14
13
12
11
10
9
8
PLL
Auto-bias circuit
Timing circuit
Clock driver
CCD
(1130bit)
Bias circuit (A)
Output circuit
Bias circuit (B)
(S/H 1bit)
VG2
5
6
7
VCO OUT
VG1
4
VSS
3
VSS
2
OUT
1
IN
Clamp circuit
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E90731B7X-PS
CXL5505M/P
Pin Description
Pin No.
Symbol
Description
I/O
Impedance
> 10kΩ at no clamp
1
IN
I
Signal input
2
VG1
O
Gate bias 1 DC output
3∗
VG2
I
Gate bias 2 DC input
4
OUT
O
Signal output
5
VSS
—
GND
6
VSS
—
GND
7
VCO OUT
O
VCO output
8
CLK
I
Clock input
9
VDD
—
Power supply (5V)
10
PC OUT
O
Phase comparator output
11
VCO IN
I
VCO input
12
VDD
—
Power supply (5V)
13
AB
O
Auto-bias DC output
14
VSS
—
GND (SUB)
40 to 500Ω
> 10kΩ
600 to 200kΩ
∗ Description of Pin 3 (VG2)
Control of input signal clamp condition
0V ........ Sync tip clamp condition
5V ........ Center bias condition
Center biased to approx. 2.1V by means of the IC internal resistance (approx. 10kΩ).
In this mode, the input signal is limited to APL 50% and the maximum input signal amplitude is
200mVp-p.
Input waveform
Clamp
level
–2–
Output waveform
CXL5505M/P
Electrical Characteristics
(Ta = 25°C, VDD = 5V, fCLK = 4.433619MHz, VCLK = 500mVp-p, sine wave)
See "Electrical Characteristics Test Circuit"
Item
Symbol
Test condition
SW condition
1
2
3
Min.
Typ.
Max.
Unit
Note
Supply current
IDD
—
a
a
—
11
20
29
mA
1
Low frequency gain
GL
200kHz,
500mVp-p,
sine wave
a
a
b
–2
0
2
dB
2
fR
200kHz ←→ 4.43MHz,
150mVp-p,
sine wave
←→
b
b
–2
–1
0
dB
3
Frequency response
b
c
Differential gain
DG
5-staircase wave
(See Note 4)
d
a
c
0
3
5
%
4
Differential phase
DP
5-staircase wave
(See Note 4)
d
a
c
0
3
5
degree
4
S/H pulse coupling
CP
No signal input
f
b
a
—
—
350 mVp-p
5
SN
50% white
video signal
(See Note 6)
e
a
d
52
56
S/N ratio
—
dB
6
Notes
(1) This is the IC supply current value during clock and signal input.
(2) GL is the output gain of OUT pin when a 500mVp-p, 200kHz sine wave is fed to IN pin.
GL = 20 log
OUT pin output voltage [mVp-p]
[dB]
500 [mVp-p]
(3) Indicates the dissipation at 4.43MHz in relation to 200kHz.
From the output voltage at OUT pin when a 150mVp-p, 200kHz sine wave is fed to IN pin, and from the
output voltage at OUT pin when a 150mVp-p, 4.43MHz sine wave is fed to same, calculation is made
according to the following formula.
fR = 20 log
OUT pin otuput voltage (4.43MHz) [mVp-p]
[dB]
OUT pin output voltage (200kHz) [mVp-p]
–3–
CXL5505M/P
(4) In figure below, differential gain (DG) and differential phase (DP) are tested with a vector scope when
the 5-staircase wave is fed.
150mV
350mV
500mV
150mV
1H 64µs
Input waveform
(5) The internal clock component to the output signal during no-signal input and the leakage of that high
harmonic component are tested.
Test value
(mVp-p)
(6) S/N ratio during a 50% white video signal input shown in figure below is tested at a video noise meter, in
BPF 100kHz to 5MHz, Sub Carrier Trap mode.
175mV
325mV
150mV
1H 64µs
Input waveform
Clock
fsc (4.433619MHz) sine wave
0.3 to 1.0Vp-p
(0.5Vp-p typ.)
–4–
–5–
50% white
video signal
5-staircase wave
f
e
d
c
SW1
b
200kHz
150mVp-p
sine wave
4.43MHz
150mVp-p
sine wave
a
200kHz
500mVp-p
sine wave
Electrical Characteristics Test Circuit
1µ
11
10
1000p
5V
a
1000p
VG1 VG2 OUT VSS
5
2
3
4
IN
1
1M
9
8
9V
2.1k
Note 2)
BPF
Note 2)
LPF
Note 1)
×3
×3
Noise meter
Vector scope
Spectrum
analyzer
Oscilloscope
–50
200
7M
17.7M
Frequency [Hz]
[dB] BPF frequency response
–50
17.7M
d
0
–3
7M
Frequency [Hz]
b
a
SW3 c
[dB] LPF frequency response
Note 1)
VCO
OUT
7
CLK
0.1µ
1000p
0
–3
b
SW2
VSS
6
VDD VCO PC VDD
IN OUT
12
82k
AB
13
1µ
1k
0.1µ 3.3µ
1000p
VSS
14
3.3µ
CLK
fSC (4.433619MHz)
0.5Vp-p
sine wave
CXL5505M/P
–6–
1µ
7
1.8k
1.8k
When VCO OUT (Pin 7)
in used.
Input
(Non-inverted signal)
AA
Application Circuit
1M
1
14
4fSC
2SC403
5V
5V
2
1µ
560k
1µ
330k
5
10
1k
470
7
8
27p
Delay time
190ns
LPF
5V
2200
Transistor used
NPN: 2SC2785
2200
2200
(ex. TH328LNLS-2620 Toukou made)
Transistor used
PNP: 2SA1175
6
9
0.1µ
1000p
A
(Non-inverted signal)
Output
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
AA
4
11
82k
0.1µ 3.3µ
1k
1000p
(Inverted signal)
3
12
1000p
13
3.3µ
fSC (4.433619MHz)
0.5Vp-p
sine wave
CXL5505M/P
CXL5505M/P
Example of Representative Characteristics
Supply current vs. Ambient temperature
Low frequency gain vs. Ambient temperature
2
Low frequency gain [dB]
Supply current [mA]
30
20
10
–20
0
20
40
60
Ambient temperature [°C]
1
0
–1
–2
–20
80
Frequency response vs. Ambient temperature
0
20
40
60
Ambient temperature [°C]
80
Differential gain vs. Ambient temperature
10
0
Differential gain [%]
Frequency response [dB]
8
–1
–2
6
4
2
–3
–20
0
20
40
60
Ambient temperature [°C]
0
–20
80
Supply current vs. Supply voltage
80
2
Low frequency gain [dB]
Supply current [mA]
20
40
60
Ambient temperature [°C]
Low frequency gain vs. Supply voltage
30
20
10
4.75
0
5
Supply voltage [V]
1
0
–1
–2
4.75
5.25
–7–
5
Supply voltage [V]
5.25
CXL5505M/P
Frequency response vs. Supply voltage
Differential gain vs. Supply voltage
10
0
Differential gain [%]
Frequency response [dB]
8
–1
–2
6
4
2
–3
4.75
5
Supply voltage [V]
0
4.75
5.25
5
Supply voltage [V]
Frequency response
2
Gain [dB]
0
–2
–4
–6
10k
100k
Frequency [Hz]
–8–
1M
10M
5.25
CXL5505M/P
Package Outline
Unit: mm
CXL5505M
14PIN SOP (PLASTIC)
+ 0.4
1.85 – 0.15
+ 0.4
9.9 – 0.1
14
8
6.9
7
0.45 ± 0.1
0.5 ± 0.2
1
7.9 ± 0.4
+ 0.3
5.3 – 0.1
0.15
+ 0.2
0.1 – 0.05
+ 0.1
0.2 – 0.05
1.27
M
0.24
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
SOP-14P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
SOP014-P-0300
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
0.2g
JEDEC CODE
CXL5505P
+ 0.1
05
0.25 – 0.
14PIN DIP (PLASTIC)
8
7.62
14
+ 0.3
6.4 – 0.1
+ 0.4
19.2 – 0.1
1
0° to 15°
7
0.5 ± 0.1
+ 0.4
3.7 – 0.1
3.0 MIN
0.5 MIN
2.54
1.2 ± 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
DIP-14P-01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
DIP014-P-0300
LEAD MATERIAL
42/COPPER ALLOY
JEDEC CODE
Similar to MO-001-AH
PACKAGE MASS
0.9g
–9–