CXL1517M/1518M CMOS-CCD Signal Processor Description The CXL1517M/1518M are CMOS-CCD signal processors developed for CCD camera complementary color filter array processing system. CXL1517M 452.5-bit × 2, 453.5-bit 1H CCD delay line CXL1518M 300.5-bit × 2, 301.5-bit 1H CCD delay line Features • Single 5V power supply • Low power consumption (Typ.) CXL1517M 120mW CXL1518M 75mW • Built-in peripheral circuits • Built-in CDS (Correlated Double Sampling) circuit 20 pin SOP (Plastic) Structure CMOS-CCD Functions • Clock driver • Autobias circuit (Center and black) • Pedestal clamp circuit • CDS circuit • Overflow prevention circuit Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VDD 6 • Operating temperature Topr –10 to +65 • Storage temperature Tstg –55 to +150 • Allowable power dissipation PD 500 V °C °C mW Recommended Operating Voltage Range (Ta = 25°C) Supply voltage VDD 4.6 to 5.25 V Item Symbol Min. Typ. Max. Unit Clock voltage Low VL VSS 0.3 × VDD V Clock voltage High VH 0.7 × VDD VDD V Clock frequency Remarks CXL1517M fCL 7.16 MHz NTSC: 455fH CCIR: 454fH CXL1518M fCL 4.77 MHz NTSC: 910fH/3 CCIR: 908fH/3 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E91777A78-PS CXL1517M/1518M XDL1 XDL2 VDD VDD VDD VSS VSS VSS Block Diagram and Pin Configuration (Top View) 16 15 4 7 17 1 13 14 TIMING GENERATOR ABBL 3 A.B. BLACK ABCN 18 A.B. CENTER DRIVER PRECHARGE DRAIN PG. GEN. IN-A 20 (n bit) CLP DL A CDS OUTPUT CIRCUIT 11 OUT-A CDS OUTPUT CIRCUIT 10 OUT-B CDS OUTPUT CIRCUIT 8 OUT-C PG. GEN. IN-B 2 (n bit) CLP DL B PG. GEN. C OVERFLOW PREVENTION CIRCUIT 6 19 POTENTIAL CONTROL ABOVF CLP PULSE GEN. VSS 1 20 IN-A 19 ABOVF IN-B 2 18 ABCN ABBL 3 VDD 4 17 VDD IN-C 5 16 XDL1 CLP 6 15 XDL2 VDD 7 14 VSS OUT-C 8 13 VSS 12 CDS VGG 9 OUT-B 10 11 OUT-A –2– CDS 9 12 CDS DL VGG CLP CLP IN-C 5 (n + 1 bit) CXL1517M/1518M Pin Description Pin No. Symbol I/O Description GND Comment 1 VSS — 2 IN-B I Signal input B channel (Y) 3 ABBL O Autobias DC output for Y signal Black level bias 4 VDD — Power supply Analog 5 IN-C I Signal input C channel (Y) Black level bias at no clamp > 100k 6 CLP I Clamp pulse input > 100k 7 VDD — Power supply Output circuit 8 OUT-C O Signal output C channel 9 VGG O Output circuit bias DC output 10 OUT-B O Signal output B channel 11 OUT-A O Signal output A channel 12 CDS O DC output for CDS 13 VSS — GND Output circuit 14 VSS — GND Timing 15 XDL2 I Clock pulse input 2 > 100k 16 XDL1 I Clock pulse input 1 > 100k 17 VDD — Power supply Timing 18 ABCN O Autobias DC output for C signal Center level bias 19 ABOVF O Autobias DC output for overflow prevention circuit 20 IN-A I Signal input A channel (C) Analog –3– Center level bias at no clamp > 100k ABBL ABOVF CDS VGG IDD Autobias black level Overflow prevention circuit Autobias level CDS source level Output circuit bias level Current ∗ supply –4– b b a to c a ↑ ↓ b a ∗ Standard values are different between CXL1517M and CXL1518M. Cross-talk between channels CRT Bch ∆LBC → Cch V6 b a a A → V1 B, C → V2 + 0.25V ↓ A → V1 B, C → V2 + 0.25V 20 log Output amplitude (mVp-p) Input amplitude (SIN 100kHz, 100mVp-p) 15 –4.5 –3.5 — 24 0.8 2.3 3.0 4.3 Note 4) 0 0 0 0 1 1 5 5 Output amplitude (SIN 1MHz, 100mVp-p) –1.5 –0.4 Output amplitude (SIN 100kHz, 100mVp-p) –1.8 –0.8 Note 1) 20 log 0.3 a — 1.2 a a 2.6 a 3.9 a 4.6 3 5 12 12 — — — 25 35 3.0 3.5 3.3 4.5 4.8 Min. Typ. Max. 4.2 V1 Conditions Ratings % % % % dB dB mA V V V V V Unit fCL = 7.16MHz (CXL1517M) fCL = 4.77MHz (CXL1518M) a Note 3) b b b ↑ ↓ c a to c a to c a to c a a a a a a Linearity difference between channels V6 b a a a b b b b b a a a a a E1 Bias conditions Note 2) Lin. V6 V6 A1 V5 V4 V3 V2 V1 SW4 SW1 SW2 SW3 to 6 SW conditions Ta = 25°C, VDD = 5.0V, VSS = 0V The insertion gain difference ∆G between channels Linearity fG Frequency ∗ response CXL1518M IG Insertion gain CXL1517M CXL1518M CXL1517M ABCN Test Symbol point Autobias center level Item Electrical Characteristics CXL1517M/1518M CXL1517M/1518M Notes) 1) Linearity testing For A channel, set input bias to ABCN – 0.2V first, and then set it to ABCN and ABCN + 0.2V. Then input a sine wave of 100kHz and 100mVp-p, and compare the three output amplitudes. For B channel and C channel, set input bias to ABBL + 0.45V first, and then set it to ABBL + 0.25V and ABBL + 0.05V. Then input a sine wave of 100kHz and 100mVp-p, and compare the three output amplitudes. The maximum output amplitude for the respective A, B and C channels is taken as Sout max and the minimum output amplitude as Sout min. The linearity of the respective channels is defined as: Lin. = Sout max – Sout min × 200 [%] Sout max + Sout min 2) Calculation of insertion gain difference As the maximum insertion gain among A, B and C channels is taken as Gmax and the minimum as Gmin, the insertion gain difference between channels ∆G as: ∆G = | 1 – 10 ( Gmax20– Gmin ) | × 100 [%] 3) Calculation of linearity difference Define B channel linearity as LB and C channel linearily as LC we obtain the difference ∆LBC as: ∆LBC = | LB – LC | [%] 4) Cross-talk calculation CRTa : The cross-talk value of A channel when B and C channels are input : The output value of A channel when A channel is input OUTA-a SW3-a, SW4-a, SW5, 6-b OUTA-bc : The output value of A channel when B and C channels are input (Cross-talk component) SW3-a, SW4-b, SW5, 6-a CRTa = OUTA-bc OUTA-a × 100 [%] Clock Waveform Timing (140) ∗ 210ns (52.5) ∗ 87.5ns 10ns XDL1 10ns 90% 90% 50% 50% 10% 10% 17.5ns (52.5) ∗ 87.5ns 10ns XDL2 10ns 90% 90% 50% 50% 10% 10% –5– ∗ The value in brackets is for CXL1517M. CXL1517M/1518M Electrical Characteristics Test Circuit a b a 100kHz, 100mVp-p sine wave c SW1 a No signal (GND) b 1MHz, 100mVp-p sine wave a b b SW6 SW5 SW4 V3 V1 V4 1µ 1µ 16V 16V 19 20 18 17 13 14 15 16 VDD 1µ 16V XDL XDL 2 1 12 3.3k 11 a SW3 b VDD 1 5 4 3 2 6 9 8 7 ×1 L.P.F c 3.3k 10 1µ 16V 1µ 16V ×1 V5 V6 VDD 3.3k V2 10k 10k 10k SW2 A1 VDD E1 a b Application Circuit XDL XDL VDD 1 2 47µ 16V Input A 0.1µ 16V 1µ 1µ 16V 16V VDD 3.3k 1µ 16V Output A 100p 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 VDD 1µ 16V 0.1µ 16V Input B 100p 3.3k Output B 100p 1µ 16V 0.1µ 4.7µ 16V 4.7µ 16V 16V VDD Input CLP VDD C input VDD 3.3k Output C Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. –6– CXL1517M/1518M Package Outline Unit: mm 20PIN SOP (PLASTIC) + 0.4 12.45 – 0.1 20 + 0.4 1.85 – 0.15 11 6.9 10 + 0.1 0.2 – 0.05 1.27 0.24 0.5 ± 0.2 1 0.45 ± 0.1 + 0.2 0.1 – 0.05 7.9 ± 0.4 + 0.3 5.3 – 0.1 0.15 M PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE SOP-20P-L01 LEAD TREATMENT SOLDER PLATING EIAJ CODE SOP020-P-0300 LEAD MATERIAL COPPER ALLOY PACKAGE MASS 0.3g JEDEC CODE –7–