CXD1159AQ
Sync Signal Generator for Camera
Description
The CXD1159AQ is a sync signal generator for
consumer video cameras.
32 pin QFP (Plastic)
Features
• Adapts to NTSC or PAL through mode switching
• Low power consumption
• Phase comparator and built-in inverter for active
filter (Power supply according to inverter for filter)
• Supports external synchronization
Structure
Silicon gate CMOS
Application
Video cameras
Functions
Generation of various sync signals
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VDD
VSS∗1 – 0.5 to +7.0
• Input voltage
VI
VSS∗1 – 0.5 to VDD + 0.5
• Output voltage
VO
VSS∗1 – 0.5 to VDD + 0.5
• Storage temperature
Tstg
–55 to +150
∗1 VSS = 0V
Recommended Operating Conditions
• Supply voltage
VDD
4.50 to 5.50
• Operating temperature
Topr
–20 to +75
V
V
V
°C
V
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E01103-PS
CXD1159AQ
Block Diagram
FSCI 22
1/4
24 SC
FSCO 23
1/5
1/227
PHASE
COMPARATOR
17 COMP
16 PSEL
20 AOUT
SUB-CARRIER
CONTROL
19 AIN
1/4
6
CLKO
7
1/7 or 6
1/65
1/525 or 625
H-DECODER
V-DECODER
14 MODE
TEST
GENERATOR
CLKI
RESET
GENERATOR
V-CONTROL
FSCI
VSS2
AOUT
AIN
VDD2
COMP
26
FSCO
25
SC
11
WND
8
WNDE
1
LALT
32
FLD
VSS2
31
BFO
VDD2
30
BLKO
VSS1
Pin Configuration
29
SYNC
21
VDO
18
HDO
12
VDD1
OUTPUT CONTROL
28
24
23
22
21
20
19
18
17
WNDE 25
16 PSEL
WND 26
15 VINT
TEST 27
14 MODE
VDD1 28
13 SCOF
HDO 29
12 VSS1
VDO 30
11 LALT
1
2
3
4
5
6
7
8
LR
EXT
CLKI
CLKO
FLD
9
VR
BLKO 32
HR
10 NC
BFO
SYNC 31
–2–
13 SCOF
NC
27 TEST
5
EXT
2
HR
3
VR
4
LR
15 VINT
CXD1159AQ
Pin Description
Pin
No.
Symbol
I/O
Description
1
BFO
O
Burst flag pulse
2
HR
I
H reset input
3
VR
I
V reset input
4
LR
I
LALT reset input
5
EXT
I
Internal/External mode switching INT/EXT
6
CLKI
I
Clock input (NTSC: 14.31818MHz, PAL: 14.1875MHz)
7
CLKO
O
Clock output
8
FLD
O
Field pulse
9
NC
—
10
NC
—
11
LALT
O
Line alternate pulse
12
VSS1
—
GND
13
SCOF
I
Sub carrier suppress input L: OFF
14
MODE
I
NTSC/PAL mode switching NTSC/PAL
15
VINT
I
Initialize input
16
PSEL
I
Phase comparator polarity switch
17
COMP
O
Phase comparator output
18
VDD2
—
Filter inverter +5V
19
AIN
I
Filter inverter input
20
AOUT
O
Filter inverter output
21
VSS2
—
Filter inverter GND
22
FSCI
I
4fsc clock input
23
FSCO
O
4fsc clock output
24
SC
O
Sub carrier output
25
WNDE
I
WND output enable input (at L: Enable)
26
WND
O
Window output
27
TEST
I
Test input (Normally "L")
28
VDD1
—
+5V
29
HDO
O
Horizontal drive pulse
30
VDO
O
Vertical drive pulse
31
SYNC
O
Composite sync pulse
32
BLKO
O
Composite blanking pulse
–3–
CXD1159AQ
Electrical Characteristics
(VDD = 5V ± 10%, VSS = 0V, Topr = –20 to +75°C)
DC Characteristics
Item
Symbol
Conditions
Min.
Typ.
IDD
Supply current
IDDS
Static
High level
VOH
IOH = –2mA
Low level
VOL
IOL = 4mA
Output voltage II∗3
High level
VOH
IOH = –1.5mA
Low level
VOL
IOL = 1.5mA
High level
VIH
Low level
VIL
Input leak current
ILI
Input leak current∗4
ILZ
∗1
∗2
∗3
∗4
Unit
4.5
state∗1
Output voltage I∗2
Input voltage
Max.
mA
0
0.1
mA
VDD – 0.8
VDD
V
VSS
0.4
V
VDD/2
VDD
V
VSS
VDD/2
V
0.7VDD
VI = 0V to VDD
V
0.3VDD
V
–10
10
µA
–10
10
µA
VIH = VDD, VIL = VSS
Output pins except "AOUT"
"AOUT" pin
Tri-state pin
AC Characteristics
Item
Fall delay time
Rise delay time
CLKI
Symbol
Conditions
tPDL
tPDH
Min.
Typ.
Max.
Unit
VOL = 0.4V
45
ns
VOH = 2.4V
45
ns
2.5V
2.4V
HDO
0.4V
tPDH
tPDL
I/O Capacitance
Item
Symbol
Input pin
Output pin
Min.
Typ.
Max.
Unit
CIN
9
pF
COUT
11
pF
Test Circuit
1MΩ
VDD
Test conditions: VDD = VI = 0V, fM = 1MHz
18
0.1µF
Filter Amplifier Characteristics
600Ω
Voltage gain
GV
25dB (Typ.)
1µF
19
20
21
VI
VO
1kHz
Gv = 20 log
–4–
VO
VI
CXD1159AQ
Functions
1. Generation of various sync signals (See the Timing Chart.)
Various sync signals are generated from clocks.
• Clock frequencies
NTSC: 910fH (14.31818MHz)
PAL: 908fH (14.1875MHz)
4fsc (17.734475MHz)
For the system clock
NTSC: 910fH/7
PAL: 908fH/7 or 6
2. PAL PLL for 4fsc
To the master clock of 908fH is matched a phase of 4fsc. The polarity of the phase comparator can be switched
according to the type of external filter (passive or active).
Filter
PSEL
Passive
L
Active
H
Master
(908fH)
4fsc
COMP
Fast
Delay
H
Slow
Fast
L
Fast
Delay
L
Slow
Fast
H
3. SC (Sub-Carrier) generation
Mode
INT or EXT
SC
NTSC
INT
910fH/4
NTSC
EXT
4fsc/4
PAL
x
4fsc/4
INT: Internal mode
(EXT = L)
EXT: External mode
(EXT = H)
In either mode unused counters are stopped. When SC is not required, by setting SCOF to L all SC counters
are stopped and SC is not output.
4. Initialization and Reset
In INT mode the circuit is initialized with the fall of VINT. At that time, H, V and LALT resets are not accepted.
In EXT mode, VINT is not accepted, whereas H, V and LALT resets are accepted.
–5–
CXD1159AQ
• Initialize (VINT)
When EXT = L, VINT fall is detected and operation is started as the circuit is initialized at the VD fall position
just before field I. (Initialization is completed within 100ns after the fall is detected).
NTSC VINT
PAL VINT
VD
VD
HD
HD
FLD
FLD
Initialize point
Initialize point
• H reset (HR)
Reset is performed with the first fall. However reset is not done anymore unless there is a deviation of more
than 2 clocks (0.98µs) to the subsequent edges.
The minimum reset pulse width is 0.98µs.
HD is reset 2.94 to 3.43µs in advance of HR input.
more than 0.98µs
HR
HD
2.94 to 3.43µs
• V reset (VR)
VD is reset 3.5H in advance of VR input.
The minimum reset pulse width is 32µs.
• LALT reset (LR)
LALT is reset in the same phase as LR reset.
The minimum reset pulse width is 32µs.
LR
LALT
–6–
CXD1159AQ
Timing Chart H (NTSC)
1/2H
1H
6.36
HDO
10.76
BLKO
HSYNC
(SYNC)
4.89
1.47
EO
(SYNC)
2.45
1.47
26.89
VSYNC
(SYNC)
4.89
2.45
BFO
6.85
VD
FLD
ODD
EVEN
28.36
WND
17.6
(Unit: µs)
Timing Chart H (PAL)
1/2H
1H
6.41
HDO
10.70
BLKO
4.93
HSYNC
(SYNC)
1.48
EO
(SYNC)
2.47
1.48
27.07
VSYNC
(SYNC)
4.93
2.47
BFO
6.91
VD
FLD
ODD
EVEN
LALT
28.55
WND
17.69
(Unit: µs)
–7–
CXD1159AQ
Timing Chart V (NTSC)
FIELD E
O: ODD
E: EVEN
FIELD O
HDO
9H
VDO
SYNC
20H
BLKO
BFO
FLD
121H
80H
WND
FIELD O
FIELD E
HDO
9H
VDO
SYNC
20H
BLKO
BFO
FLD
121H
80.5H
WND
Timing Chart V (PAL)
FIELD I, III
FIELD II, IV
HDO
7.5H
VDO
SYNC
25H
BLKO
BFO (III – IV)
BFO (I – II)
LALT (III – IV)
LALT (I – II)
144H
FLD
97H
WND
FIELD II, IV
FIELD I, III
HDO
VDO
7.5H
SYNC
25H
BLKO
BFO (IV – I)
BFO (II – III)
LALT (IV – I)
LALT (II – III)
144H
FLD
96.5H
WND
–8–
CXD1159AQ
Application Circuit
PAL (Filter configuration 1, Internal mode)
NTSC (Internal mode)
1M
4fsc
{17.73MHz} 1000p 100k 10k 0.01µ
VSS2
AOUT
AIN
VDD2
23
22
21
20
19
18
17
COMP
FSCI
24
VDD2
FSCO
17
AIN
SC
1000p
18
AOUT
19
VSS2
20
FSCI
21
FSCO
22
SC
23
COMP
24
100
68k
PSEL 16
PSEL 16
25 WNDE
26 WND
VINT 15
26 WND
VINT 15
27 TEST
MODE 14
27 TEST
MODE 14
28 VDD1
SCOF 13
28 VDD1
SCOF 13
29 HDO
VSS1 12
29 HDO
VSS1 12
30 VDO
LALT 11
30 VDO
LALT 11
CLKO
FLD
6
7
8
FLD
CLKI
5
CLKO
EXT
4
CLKI
LR
3
32 BLKO
EXT
VR
2
NC 9
NC 10
LR
HR
1
31 SYNC
VR
BFO
32 BLKO
NC 10
HR
31 SYNC
BFO
25 WNDE
1
2
3
4
5
6
7
8
NC 9
908fH
{14.1875MHz}
910fH
{14.31818MHz}
PAL (Filter configuration 2, Internal mode)
2SC945
10k
4.7k
0.1µ
1.5µ
10k
24
23
22
21
20
19
18
SC
FSCO
FSCI
VSS2
AOUT
AIN
VDD2
220k
25 WNDE
17
COMP
4fsc
{17.73MHz} 1000p 100k
PSEL 16
26 WND
VINT 15
27 TEST
MODE 14
28 VDD1
SCOF 13
29 HDO
VSS1 12
30 VDO
LALT 11
NC 10
31 SYNC
BFO
HR
VR
LR
EXT
CLKI
CLKO
FLD
32 BLKO
1
2
3
4
5
6
7
8
908fH
{14.1875MHz}
NC 9
Application circuits shown are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any
infringement of third party patent and other right due to same.
–9–
CXD1159AQ
Package Outline
Unit: mm
32PIN QFP (PLASTIC)
9.0 ± 0.2
0.1
+ 0.35
1.5 – 0.15
+ 0.3
7.0 – 0.1
24
17
16
25
(8.0)
A
9
32
1
+ 0.2
0.1 – 0.1
0.24
0˚ to 10˚
M
+ 0.15
b = 0.30 – 0.10
(0.127)
( 0.30)
+ 0.10
0.127 – 0.05
b
0.50
8
0.8
DETAIL A : SOLDER
SONY CODE
QFP-32P-L01
EIAJ CODE
P-QFP32-7x7-0.8
JEDEC CODE
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
LEAD MATERIAL
42 / COPPER ALLOY
PACKAGE MASS
0.2g
LEAD SPECIFICATIONS
ITEM
LEAD MATERIAL
SPEC.
ALLOY 42
LEAD TREATMENT
Sn-Pb 10%
LEAD TREATMENT THICKNESS
5-18µm
– 10 –
Sony Corporation