SONY CXL5504P

CXL5504M/P
CMOS-CCD 1H Delay Line for NTSC
For the availability of this product, please contact the sales office.
Description
The CXL5504M/P are CMOS-CCD delay line ICs
that provide 1H delay time for NTSC signals including
the external low-pass filter.
CXL5504M
8 pin SOP (Plastic)
CXL5504P
8 pin DIP (Plastic)
Features
• Single power supply (5V)
• Low power consumption 90mW (Typ.)
• Built-in peripheral circuits
• Clamp level of I/O signal can be selected
Functions
• 905-bit CCD register
• Clock driver
• Autobias circuit
• Input clamp circuit
• Sample and hold circuit
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VDD
6
V
• Operating temperature Topr
–10 to +60
°C
• Storage temperature Tstg
–55 to +150 °C
• Allowable power dissipation
PD
CXL5504M
350
mW
CXL5504P
480
mW
Structure
CMOS-CCD
Recommended Operating Condition (Ta = 25°C)
Supply voltage
VDD
5 ± 5%
V
Recommended Clock Conditions (Ta = 25°C)
• Input clock amplitude VCLK
0.4 to 1.0
Vp-p
(0.5Vp-p typ.)
• Clock frequency
fCLK
14.318182
MHz
• Input clock waveform Sine wave
Input Signal Amplitude
VSIG 500mVp-p (Typ.), 572mVp-p (Max.)
(at internal clamp condition)
AB
VDD
I/O1
CLK
Blook Diagram and Pin Configration (Top View)
8
7
6
5
Autobias circuit
Timing circuit
Bias circuit
Clock driver
CCD
(905bit)
Bias circuit (A)
Output circuit
Bias circuit (B)
(S/H 1bit)
3
4
VSS
2
OUT
1
I/O2
I/O control
IN
Clamp circuit
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E89931C79-PS
CXL5504M/P
Pin Description
Pin No.
Symbol
I/O
Description
1
IN
I
Signal input
2
I/O2
I
I/O control 2
3
OUT
O
Signal output
4
VSS
—
GND
5
CLK
I
Clock input
6
I/O1
I
I/O control 1
7
VDD
—
Power supply (5V)
8
AB
O
Autobias DC output
Impedance
> 10kΩ at no clamp
40 to 500Ω
> 100kΩ
600 to 200kΩ
Description of Function
In the CXL5504M/P, the condition of I/O control pins (Pins 2 and 6) control the input signal clamp condition and
the mode of the output signal with relation to its input signal.
There are 2 modes for the I/O signal.
Input waveform
Output waveform
(1) PN mode
(Low level clamp/reverse phase output mode)
(2) NP mode
(High level clamp/positive phase output mode)
Clamp
level
Clamp
level
I/O Control Pin
(1) I/O1 (Pin 6)
Control of the I/O signal condition
DC open ..... Input signal is low level clamped and the output signal is inverted in relation to the input
signal. As the pin is biased to 2.5V by means of the resistance inside the IC, a decoupling
capacitor of around 1000pF is necessary.
GND ............. Input signal is high level clamped and the output signal turns into an inverted signal.
(2) I/O2 (Pin 2)
Control of the input signal clamp condition
0V ................. Internal clamp condition
5V ................. Non internal clamp condition
Center biased to approx. 2.1V by means of the IC internal resistance (several 10kΩ).
Usage in this mode is limited to APL 50% signals and in this mode, the maximum input
signal amplitude is 200mVp-p.
–2–
CXL5504M/P
Electrical Characteristics
Item
Symbol
Supply
current
IDDPN
Low
frequency
gain
GLPN
Frequency
response
fPN
Differential
gain
DGPN
Differential
phase
DPPN
S/H pulse
coupling
CPPN
(Ta = 25°C, VDD = 5V, fCLK = 14.318182MHz, VCLK = 500mVp-p, Sine wave)
See "Electrical Characteristics Test Circuit"
Test condition
Bias condition
Vbias1 (V)
Min.
1 2 3 4 5 6 7
(Note 1)
SW condition
DGNP
DPNP
SNPN
SNNP
Note
—
10
18
28
mA
2
a b
—
–2
0
2
dB
3
200kHz ←→ 3.57MHz, b
b b
150mVp-p,
a a
b b
a a
sine wave
c
2.1
–2
–1
0
dB
4
a c
—
0
5
7
%
5
a c
—
0
5
7
degree
5
—
—
350 mVp-p
6
52
56
200kHz,
500mVp-p,
sine wave
a a b
a
5-staircase wave
(See Note 5)
d
5-staircase wave
(See Note 5)
d
No signal input
— c a
CPNP
S/N ratio
Unit
a a
b b
a a
←→
fNP
Max.
a —
— c b
—
IDDNP
GLNP
b b
Typ.
50% white
video signal
(See Note 7)
e
b
b
a
b
b
a
b
b
b b
a a
b b
a a
b b
a a
b b
a a
VINPN + 0.5
b a
a d
VINNP
—
—
dB
7
Notes
(1) VINPN and VINNP are defined as follows.
VINPN and VINNP are the input signal clamp levels of PN and NP modes clamping the video signal sync
tip level.
CXL5504
1
Input
(IN)
VINPN
VINNP
Testing of VINPN and VINNP is executed with a voltmeter under the following SW conditions.
Item
SW condition
1
2
3
4
5
6
7
VINPN
—
c
b
b
b
a
—
VINNP
—
c
b
a
a
a
—
Test
point
V1
–3–
CXL5504M/P
(2) This is the IC supply current value during clock and signal input.
(3) GLPN, GLNP are output gain of OUT pin when a 500mVp-p, 200kHz sine wave is fed to IN pin.
(Example of calculation)
GLPN = 20 log
OUT pin output voltage (PN mode) [mVp-p]
500 [mVp-p]
[dB]
(4) Indicates the dissipation at 3.57MHz in relation to 200kHz.
From the output voltage at OUT pin when a 150mVp-p, 200kHz sine wave is fed to IN pin, and from the
output voltage at OUT pin when a 150mVp-p, 3.57MHz sine wave is fed to same, calculation is made
according to the following formula. The input part bias is tested at 2.1V.
(Example of calculation)
fPN = 20 log
OUT pin otuput voltage (PN mode, 3.57MHz) [mVp-p]
OUT pin output voltage (PN mode, 200kHz) [mVp-p]
[dB]
(5) The differential gain (DG) and the differential phase (DP), when the 5-staircase wave in the figure below is
input are tested at the vector scope.
143mV
357mV
500mV
143mV
1H 63.56µs
Input waveform (Input waveform of NP mode is the inverted waveform in the figure above)
(6) The internal clock component to the output signal during no-signal input and the leakage of that high
harmonic component are tested. The input part bias is tested at VINPN + 0.5V and VINNP for PN and NP
modes respectively.
Test value
(mVp-p)
–4–
CXL5504M/P
(7) S/N ratio during a 50% white video signal input shown in figure below is tested at a video noise meter, in
BPF 100kHz to 4MHz, Sub Carrier Trap mode.
178mV
321mV
143mV
1H 63.56µs
Input waveform (Input waveform of NP mode is the inverted waveform in the figure above)
Clock
fsc (14.318182MHz) sine wave
0.4 to 1.0Vp-p
(0.5Vp-p typ.)
–5–
–6–
50% white
video signal
5-staircase wave
e
d
c
SW1
b
200kHz
150mVp-p
sine wave
3.57MHz
150mVp-p
sine wave
a
200kHz
500mVp-p
sine wave
–1
1
Electrical Characteristics Test Circuit
c
Vbias1
b SW2
a
a
SW4
1k
a
SW3
1µ
8
2
1
b
1M
b
6
I/O1
SW5
b
1000p
5V
a
1000p
3
a
0.1µ
9V
2.1k
BPF
Note 2)
LPF
Note 1)
×3
×3
Noise meter
Vector scope
Spectrum
analyzer
Osilloscope
–50
200
6M
14.3M
Frequency [Hz]
Note 2)
[dB] BPF frequency response
–50
14.3M
d
0
–3
6M
Frequency [Hz]
b
a
SW7 c
Note 1)
[dB] LPF frequency response
4
VSS
CLK
5
1000p
0
–3
b
SW6
OUT
CXL5504M/P
I/O2
1
7
VDD
IN
AB
1µ
3.3µ
CLK
4fSC (14.318182MHz)
0.5Vp-p
sine wave
CXL5504M/P
–7–
Input
(Positive phase signal)
AA
1µ
5V
1M
Application Circuit (Using PN mode)
1
8
1µ
3.3µ
AA
CXL5504M/P
3
6
10
1k
470
27p
33p
2700
Delay time
250ns
LPF
5V
2200
Transistor used
NPN: 2SC403
2200
2200
(ex. TH356LSM-4303ZED Toukou made)
Transistor used
PNP: 2SA1175
4
5
0.1µ
(Positive phase signal)
AA
Output
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
560k
1µ
330k
1000p
(Reverse phase signal)
2
12
7
1000p
4fSC
0.5Vp-p
sine wave
CXL5504M/P
CXL5504M/P
Example of Representative Characteristics
Supply current vs. Ambient temprature
Low frequency gain vs. Ambient temprature
1
Low frequency gain [dB]
Supply current [mA]
30
20
10
–20
0
20
40
60
Ambient temprature [°C]
0
–1
–2
–3
–20
80
Frequency response vs. Ambient temprature
0
20
40
60
Ambient temprature [°C]
80
Differential gain vs. Ambient temprature
10
0
Differential gain [%]
Frequency response [dB]
8
–1
–2
6
4
2
–3
–20
0
20
40
60
Ambient temprature [°C]
0
–20
80
Supply current vs. Supply voltage
80
1
Low frequency gain [dB]
Supply current [mA]
20
40
60
Ambient temprature [°C]
Low frequency gain vs. Supply voltage
30
20
10
4.75
0
5
Supply voltage [V]
0
–1
–2
–3
4.75
5.25
–8–
5
Supply voltage [V]
5.25
CXL5504M/P
Frequency response vs. Supply voltage
Differential gain vs. Supply voltage
10
0
Differential gain [%]
Frequency response [dB]
8
–1
–2
6
4
2
–3
4.75
5
Supply voltage [V]
0
4.75
5.25
5
Supply voltage [V]
Frequency response
2
Gain [dB]
0
–2
–4
–6
10k
100k
Frequency [Hz]
–9–
1M
10M
5.25
CXL5504M/P
Unit: mm
CXL5504M
8PIN SOP (PLASTIC)
+ 0.4
1.85 – 0.15
+ 0.4
6.1 – 0.1
8
5
0.15
6.9
7.9 ± 0.4
+ 0.3
5.3 – 0.1
1
+ 0.2
0.1 – 0.05
0.5 ± 0.2
4
+ 0.1
0.2 – 0.05
0.45 ± 0.1
1.27
0.24 M
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
SOP-8P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
SOP008-P-0300
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
0.1g
JEDEC CODE
8PIN SOP (PLASTIC)
S
6.2 ± 0.3
0.15
1
7.8 ± 0.4
5
5.3 ± 0.3
8
S
A
4
+ 0.05
0.15 – 0.02
0.4 ± 0.1
1.27
0.75 ± 0.2
0.05 MIN
2.0MAX
Package Outline
0.13
M
S
10° MAX
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
SOP-8P-L121
LEAD TREATMENT
PALLADIUM PLATING
EIAJ CODE
SOP008-P-0300
LEAD MATERIAL
COPPER ALLOY
PACKAGE MASS
0.1g
JEDEC CODE
– 10 –
CXL5504M/P
CXL5504P
+ 0.3
6.4 – 0.1
+ 0.4
9.4 – 0.1
5
7.62
8
+ 0.1
0.05
0.25 –
8PIN DIP (PLASTIC)
0° to 15°
4
1
+ 0.4
3.7 – 0.1
3.0 MIN
0.5 MIN
2.54
0.5 ± 0.1
1.2 ± 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
DIP-8P-01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
DIP008-P-0300
LEAD MATERIAL
COPPER ALLOY
PACKAGE MASS
0.5g
JEDEC CODE
– 11 –