SONY CXL5509M

CXL5509M/P
CMOS-CCD 1H/2H Delay Line for NTSC
Description
The CXL5509M/P is a CMOS-CCD delay line
developed for video signal processing. Usage in
conjunction with an external low-pass filter provide 1H
and 2H delay signals simultaneously (For NTSC
signals).
CXL5509M
16 pin SOP (Plastic)
Features
• Single power supply (5V)
• Low power consumption 130mW (Typ.)
• Built-in peripheral circuits
• Built-in quadruple PLL circuit
• For NTSC signals
• 1 input and 2 outputs
(Outputs for both 1H and 2H delays)
CXL5509P
16 pin DIP (Plastic)
Absolute Maximum Ratings (Ta = 25°C)
6
V
• Supply voltage
VDD
• Operating temperature Topr
–10 to +60
°C
• Storage temperature Tstg
–55 to +150 °C
• Allowable power dissipation
PD
CXL5509M
400
mW
CXL5509P
800
mW
Functions
• 906-bit (1H) and 1816-bit (2H) CCD register
• Clock driver
• Auto-bias circuit
• Sync tip clamp circuit
• Sample-and-hold circuit
• Quadruple PLL circuit
Recommended Operating Condition (Ta = 25°C)
Supply voltage
VDD
5 ± 5%
V
Structure
CMOS-CCD
Recommended Clock Conditions (Ta = 25°C)
• Input clock amplitude VCLK
0.3 to 1.0
Vp-p
(0.5Vp-p typ.)
• Clock frequency
fCLK
3.579545
MHz
• Input clock waveform sine wave
Input Signal Amplitude
VSIG 571mVp-p (Max.) (at internal clamp condition)
VSS
AB
VDD
VCO IN
PC OUT
VSS
CLK
VDD
Blook Diagram and Pin Configuration (Top View)
16
15
14
13
12
11
10
9
Auto-bias circuit
PLL
Timing circuit
Driver
CCD
(1816bit)
Clamp circuit
906bit
1816bit
Output circuit
VG1
VG2
OUT1 (1H)
5
6
7
8
VSS
4
VSS
(VCO OUT)
3
OUT2 (2H)
2
Bias circuit
Output circuit
(S/H 1bit)
VSS
1
IN
(S/H 1bit)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E91401B7X-PS
CXL5509M/P
Pin Description
Pin No.
Symbol
Description
I/O
1
IN
I
Signal input
(Non-inverted signal)
2
VG1
O
Gate bias 1 DC output
3∗
VG2
I
Gate bias 2 DC input
4
OUT1
O
1H signal output
(Inverted signal)
5
VSS
—
GND
6
OUT2
O
2H signal output
(Inverted signal)
7
VSS (VCO OUT)
(O)
GND or VCO output (4fsc)
8
VSS
—
GND
9
VDD
—
Power supply (5V)
10
CLK
I
11
VSS
—
GND
12
PC OUT
O
Phase comparator output
13
VCO IN
I
VCO input
14
VDD
—
Power supply (5V)
15
AB
O
Autobias DC output
16
VSS
—
GND
Clock input (fsc)
Impedance
> 10kΩ (at no clamp)
40 to 500Ω
40 to 500Ω
> 10kΩ
600 to 200kΩ
∗ Description of Pin 3 (VG2)
Control of input signal clamp condition
0V ........ Sync tip clamp condition
5V ........ Center bias condition
The input signal is biased to approx. 2.1V by means of the IC internal resistance (approx. 10kΩ).
In this mode, the input signal is limited to APL 50% and the maximum input signal amplitude is at
200mVp-p.
–2–
CXL5509M/P
Electrical Characteristics
(Ta = 25°C, VDD = 5V, fCLK = 3.579545MHz, VCLK = 500mVp-p, sine wave)
See "Electrical Characteristics Test Circuit"
Item
Symbol
Supply current
IDD
Low frequency
gain
GL1
Frequency
response
fR1
Differential
gain
DG1
Differential
phase
DP1
S/N ratio
S/H pulse coupling
GL2
fR2
DG2
DP2
SN1
SN2
SW conditions
Test conditions
(Note 1)
1
2
3
4
—
a
b
a
a
16
26
36
200kHz,
500mVp-p,
sine wave
a
b
a
b
–2
0
2
a
b
b
b
–2
0
2
b ←→ c
a
a
b
–2.0 –1.0
0
b ←→ c
a
b
b
–2.0 –1.0
0
d
b
a
c
—
3
5
d
b
b
c
—
3
5
d
b
a
c
—
3
5
d
b
b
c
—
3
5
e
b
a
d
52
56
—
e
b
b
d
52
56
—
f
b
a
a
—
—
350
f
b
b
a
—
—
350
200kHz ←→ 3.58MHz,
150mVp-p,
sine wave
5-staircase wave
5-staircase wave
50% white
video signal
CP1
CP2
No signal input
–3–
Min. Typ. Max. Unit Note
mA
2
dB
3
dB
4
%
5
degree
5
dB
6
mVp-p
7
–4–
SW1
3.58MHz
150mVp-p
sine wave
50% white
video signal
5-staircase wave
b
200kHz
150mVp-p
sine wave
f
e
d
c
a
200kHz
500mVp-p
sine wave
1µ
14
13
12
1M
SW2
a
11
6M
14.3M
Frequency [Hz]
×3
×3
Noise meter
Vector scope
Spectrum
analyzer
Oscilloscope
6M
14.3M
Frequency [Hz]
BPF frequency response
Note 2)
BPF
Note 2)
LPF
Note 1)
0 200
–50
–50
0
0
–3
0
–3
SW3
d
c
b
[dB]
a
b
SW4
a
[dB] LPF frequency response
Note 1)
VSS
(VCO
OUT2 OUT) VSS
6
8
7
CXL5509M/P
b
9
CLK VDD
10
3.3µ
1000p
CLK
fSC (3.579545MHz), 500mVp-p
sine wave
0.1µ
VCO PC VSS
IN OUT
VG1 VG2 OUT1 VSS
5
2
3
4
VDD
120
0.1µ
IN
1
15
1µ
82k
1000p
AB
1000p
VSS
16
3.3µ
1000p
Electrical Characteristics Test Circuit
5V
CXL5509M/P
–5–
1M
7
1.8k
Transistor used
NPN: 2SC403
1.8k
5V
1000p
3
2
1
6
5
Transistor used
PNP: 2SA1175
1k
510
1k
510
30p
1k
Delay time
170ns
LPF
Transistor used
PNP: 2SA1175
8
9
30p
1k
2.2k
5V
2.2k
5V
A
(Non-inverted signal)
2H
Output
(Non-inverted signal)
AA
1H
Output
Transistor used
NPN: 2SC403
2.2k
Transistor used
NPN: 2SC403
2.2k
2.2k
Delay time
170ns
LPF
2.2k
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
560k
1µ
330k
560k
1µ
330k
7
10
3.3µ
1000p
CLK
fSC (3.579545MHz), 500mVp-p
sine wave
0.1µ
(Inverted signal)
11
12
120
0.1µ
AA
4
13
82k
1000p
(Inverted signal)
A
V1
1000p
14
1µ
15
3.3µ
5V
16
4fSC OUT
Note) When VCO OUT (Pin 7) is
used the circuit below.
When not used, GND.
Signal input
1µ
(Non-inverted signal)
AA
Application Circuit
CXL5509M/P
CXL5509M/P
Notes
(1) By switching SW2, input condition turns out as follows.
SW2 condition
Input condition
a
Center bias condition (approx. 2.1V)
Approx. 2.1V bias is applied internally to the input signal
b
Sync tip clamp conditions
(2) This is the IC supply current value during clock and signal input.
(3) GL is the output gain of OUT pin when a 500mVp-p, 200kHz sine wave is fed to IN pin.
GL = 20 log
OUT pin output voltage [mVp-p]
[dB]
500 [mVp-p]
(4) Indicates the dissipation at 3.58MHz in relation to 200kHz.
From the output voltage at OUT pin when a 150mVp-p, 200kHz sine wave is fed to IN pin, and from the
output voltage at OUT pin when a 150mVp-p, 3.58MHz sine wave is fed to same, calculation is made
according to the following formula.
fR = 20 log
OUT pin otuput voltage (3.58MHz) [mVp-p]
[dB]
OUT pin output voltage (200kHz) [mVp-p]
(5) The differential gain (DG) and the differential phase (DP), when the 5-staircase wave in the following
figure is fed, are tested with a vector scope:
143mV
285.5mV
500mV
143mV
1H 63.56µs
(6) S/N ratio during 50% white video signal input shown in figure below is tested at video noise meter, in BPF
100kHz to 4MHz, Sub Carrier Trap mode.
178mV
321mV
143mV
1H 63.56µs
–6–
CXL5509M/P
(7) The internal clock component to the output signal during no-signal input and the leakage of that high
harmonic component are tested.
Test value (mVp-p)
Clock
fsc (3.579545MHz) sine wave
500mVp-p
(Typ.)
–7–
CXL5509M/P
Example of Representative Characteristics
Supply current vs. Supply voltage
Supply current [mA]
36
26
5.0
Supply voltage [V]
Low frequency gain (1H) vs. Supply voltage
Low frequency gain (2H) vs. Supply voltage
2
1
0
–1
–2
4.75
5.0
Supply voltage [V]
Frequency response (1H) vs. Supply voltage
0
–1
5.0
Supply voltage [V]
5.25
Frequency response (2H) vs. Supply voltage
Frequency response (2H) [dB]
1
0
–1
–2
–3
4.75
1
–2
4.75
5.25
1
Frequency response (1H) [dB]
5.25
2
Low frequency gain (2H) [dB]
Low frequency gain (1H) [dB]
16
4.75
5.0
Supply voltage [V]
0
–1
–2
–3
4.75
5.25
–8–
5.0
Supply voltage [V]
5.25
CXL5509M/P
Differential gain (1H) vs. Supply voltage
Differential gain (2H) vs. Supply voltage
5
Differential gain (2H) [%]
Differential gain (1H) [%]
5
4
3
2
1
4.75
5.0
Supply voltage [V]
4
3
2
1
4.75
5.25
5.0
Supply voltage [V]
5.25
Supply current vs. Ambient temperature
Supply current [mA]
36
26
16
–20
0
20
40
60
Ambient temperature [°C]
Low frequency gain (1H) vs. Ambient temperature
Low frequency gain (2H) vs. Ambient temperature
2
Low frequency gain (2H) [dB]
Low frequency gain (1H) [dB]
2
1
0
–1
–2
–20
80
0
20
40
60
Ambient temperature [°C]
1
0
–1
–2
–20
80
–9–
0
20
40
60
Ambient temperature [°C]
80
CXL5509M/P
Frequency response (1H) vs. Ambient temperature
Frequency response (2H) vs. Ambient temperature
1
Frequency response (2H) [dB]
Frequency response (1H) [dB]
1
0
–1
–2
–3
–20
0
20
40
60
Ambient temperature [°C]
–2
0
20
40
60
Ambient temperature [°C]
80
Differential gain (2H) vs. Ambient temperature
8
Differential gain (2H) [%]
8
Differential gain (1H) [%]
–1
–3
–20
80
Differential gain (1H) vs. Ambient temperature
6
4
2
0
–20
0
0
20
40
60
Ambient temperature [°C]
6
4
2
0
–20
80
– 10 –
0
20
40
60
Ambient temperature [°C]
80
CXL5509M/P
Frequency responses (1H)
2
Gian [dB]
0
–2
–4
–6
10k
100k
Frequency [Hz]
1M
10M
1M
10M
Frequency responses (2H)
2
Gian [dB]
0
–2
–4
–6
10k
100k
Frequency [Hz]
Note) 1H means 1H output; 2H means 2H output.
– 11 –
CXL5509M/P
Package Outline
Unit: mm
CXL5509M
16PIN SOP (PLASTIC)
+ 0.4
1.85 – 0.15
+ 0.4
9.9 – 0.1
16
9
6.9
8
+ 0.1
0.2 – 0.05
1.27
0.45 ± 0.1
0.5 ± 0.2
1
+ 0.2
0.1 – 0.05
7.9 ± 0.4
+ 0.3
5.3 – 0.1
0.15
0.24 M
PACKAGE STRUCTURE
PACKAGE MATERIAL
SONY CODE
SOP-16P-L01
EIAJ CODE
SOP016-P-0300
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
LEAD MATERIAL
COPPER ALLOY
PACKAGE MASS
0.2g
JEDEC CODE
CXL5509P
16
+ 0.3
6.4 – 0.1
+ 0.4
19.2 – 0.1
+ 0.1
0.05
0.25 –
16PIN DIP (PLASTIC)
7.62
9
1
0° to 15°
8
+ 0.4
3.7 – 0.1
3.0 MIN
0.5 MIN
2.54
0.5 ± 0.1
Two kinds of package surface:
1.All mat surface type.
2.All mirror surface type.
1.2 ± 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
DIP-16P-01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
DIP016-P-0300
LEAD MATERIAL
COPPER ALLOY
JEDEC CODE
Similar to MO-001-AE
PACKAGE MASS
1.0 g
SONY CODE
– 12 –