SONY CXP83624

CXP83620/83624
CXP83621/83625
CMOS 8-bit Single Chip Microcomputer
Description
The CXP83620/83624 and the CXP83621/83625
are CMOS 8-bit single chip microcomputer integrating
on a single chip an A/D converter, serial interface,
timer/counter, time-base timer, sub timer/counter, LCD
controller/driver and remote control reception circuit
besides the basic configurations of 8-bit CPU, ROM,
RAM, and I/O port.
The CXP83620/83624 and the CXP83621/83625 also
provide a sleep/stop function that enables lower power
consumption.
CXP83620/83624
80 pin QFP (Plastic)
80 pin LQFP (Plastic)
CXP83621/83625
80 pin QFP (Plastic)
Features
• Wide-range instruction system (213 instructions) to
cover various types of data.
— 16-bit arithmetic/multiplication and division/boolean
bit operation instructions
• Minimum instruction cycle
400ns at 10MHz operation (4.5 to 5.5V)
1µs at 4MHz operation (2.7 to 5.5V)
122µs at 32kHz operation (2.7 to 5.5V)
• Incorporated ROM capacity
20K bytes (CXP83620, 83621)
24K bytes (CXP83624, 83625)
• Incorporated RAM capacity
736 bytes (includes LCD display data area and serial interface RAM)
• Peripheral functions
— A/D converter
8-bit, 8-channel, successive approximation method
(Conversion time of 12.4µs/10MHz)
— Serial interface
Incorporated buffer RAM
(Auto transfer for 1 to 32 bytes), 1 channel
8-bit clock synchronized type (MSB/LSB first selectable), 1 channel
— Timer
8-bit timer, 8-bit timer/counter, 19-bit time-base timer,
Sub timer/counter
— LCD controller/driver
Maximum 128 segment display possible (during 1/4 duty)
4 common output, 32 segment output
Display method static, 1/2, 1/3, 1/4 duty
Bias method 1/2, 1/3 bias
— Remote control reception circuit
8-bit pulse measuring counter, 6-stage FIFO
• Interruption
14 factors, 14 vectors, multi-interruption possible
• Standby mode
Sleep/stop
• Package
80-pin plastic QFP/LQFP
• Piggy/evaluation chip
CXP83600 (CXP83620, 83624)
CXP83601 (CXP83621, 83625)
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E98134B96
–2–
4
COM0 to COM3
8-BIT TIMER 1
TO
ADJ
8-BIT TIMER/COUNTER 0
EC
BUFFER
RAM
FIFO
SERIAL INTERFACE UNIT
(CH1)
SERIAL
INTERFACE
UNIT (CH0)
REMOCON
LCD
CONTROLLER/
DRIVER
A/D CONVERTER
SI1
SO1
SCK1
CS0
SI0
SO0
SCK0
RMC
VL
VLC1
VLC2
VLC3
32
SEG0 to SEG31
8
INT0
INT1
INT2
INT3
INT4
2
3
PRESCALER/
TIME-BASE TIMER
ROM
20K/24K BYTES
SPC700
CPU CORE
Vss
RST
VDD
XTAL
TX
EXTAL
TEX
SUB TIMER/
COUNTER
RAM
736 BYTES
CLOCK GENERATOR/
SYSTEM CONTROL
PB0 to PB7
8
PE0 to PE4
PE5 to PE6
PF0 to PF7
PH0
5
2
8
1
2
PI0 to PI1
PD0 to PD7
8
PC0 to PC7
PA0 to PA7
8
8
PORT E
PORT F
AN0 to AN7
PORT A
PORT B
PORT C
PORT D
PORT H
PORT I
INTERRUPT CONTROLLER
Block Diagram
CXP83620/83624, CXP83621/83625
CXP83620/83624, CXP83621/83625
PD7/SEG23
PF0/SEG24
PF1/SEG25
PF2/SEG26
PF3/SEG27
PF4/SEG28
PF5/SEG29
VDD
PI0/TX
PI1/TEX
NC
PF6/SEG30
PF7/SEG31
PE0/INT0/EC
PE1/INT1
PE2/INT2
Pin Assignment (Top View) CXP83620/83624 (QFP package)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
PE3/INT3
1
64
PD6/SEG22
PE4/RMC
2
63
PD5/SEG21
PE5/TO
3
62
PD4/SEG20
PE6/ADJ
4
61
PD3/SEG19
PB0
5
60
PD2/SEG18
PB1/CS0
6
59
PD1/SEG17
PB2/SCK0
7
58
PD0/SEG16
PB3/SI0
8
57
SEG15
PB4/SO0
9
56
SEG14
PB5/SCK1
10
55
SEG13
PB6/SI1
11
54
SEG12
PB7/SO1
12
53
SEG11
PC0
13
52
SEG10
PC1
14
51
SEG9
PC2
15
50
SEG8
PC3
16
49
SEG7
PC4
17
48
SEG6
PC5
18
47
SEG5
PC6
19
46
SEG4
PC7
20
45
SEG3
PH0/INT4
21
44
SEG2
PA0/AN0
22
43
SEG1
PA1/AN1
23
42
SEG0
PA2/AN2
24
41
COM3
COM2
COM1
COM0
VLC1
VLC2
VL
VLC3
VSS
XTAL
RST
EXTAL
PA7/AN7
PA6/AN6
PA5/AN5
PA4/AN4
PA3/AN3
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Note) Do not make any connections to NC (Pin 75).
–3–
CXP83620/83624, CXP83621/83625
PD5/SEG21
PD6/SEG22
PD7/SEG23
PF0/SEG24
PF1/SEG25
PF2/SEG26
PF3/SEG27
PF4/SEG28
PF5/SEG29
VDD
PI0/TX
PI1/TEX
NC
PF6/SEG30
PF7/SEG31
PE0/INT0/EC
PE1/INT1
PE2/INT2
PE3/INT3
PE4/RMC
Pin Assignment (Top View) CXP83620/83624 (LQFP package)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
PE5/TO
1
60
PD4/SEG20
PE6/ADJ
2
59
PD3/SEG19
PB0
3
58
PD2/SEG18
PB1/CS0
4
57
PD1/SEG17
PB2/SCK0
5
56
PD0/SEG16
PB3/SI0
6
55
SEG15
PB4/SO0
7
54
SEG14
PB5/SCK1
8
53
SEG13
PB6/SI1
9
52
SEG12
PB7/SO1
10
51
SEG11
PC0
11
50
SEG10
PC1
12
49
SEG9
PC2
13
48
SEG8
PC3
14
47
SEG7
PC4
15
46
SEG6
PC5
16
45
SEG5
PC6
17
44
SEG4
PC7
18
43
SEG3
PH0/INT4
19
42
SEG2
PA0/AN0
20
41
SEG1
Note) Do not make any connections to NC (Pin 73).
–4–
SEG0
COM3
COM2
COM1
COM0
VLC1
VLC2
VLC3
VL
VSS
XTAL
EXTAL
RST
PA7/AN7
PA6/AN6
PA5/AN5
PA4/AN4
PA3/AN3
PA2/AN2
PA1/AN1
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
CXP83620/83624, CXP83621/83625
PD5/SEG21
PD6/SEG22
PD7/SEG23
PF0/SEG24
PF1/SEG25
PF2/SEG26
PF3/SEG27
PF4/SEG28
PF5/SEG29
VDD
PI0/TX
PI1/TEX
NC
PF6/SEG30
PF7/SEG31
PE0/INT0/EC
PE1/INT1
PE2/INT2
PE3/INT3
PE4/RMC
Pin Assignment (Top View) CXP83621/83625 (QFP package)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
60
PD4/SEG20
PE6/ADJ
2
59
PD3/SEG19
PB0
3
58
PD2/SEG18
PD1/SEG17
PE5/TO
4
57
PB2/SCK0
5
56
PD0/SEG16
PB3/SI0
6
55
SEG15
PB4/SO0
7
54
SEG14
PB5/SCK1
8
53
SEG13
PB6/SI1
9
52
SEG12
PB7/SO1
10
51
SEG11
PC0
11
50
SEG10
PC1
12
49
SEG9
PC2
13
48
SEG8
PC3
14
47
SEG7
PC4
15
46
SEG6
PC5
16
45
SEG5
PC6
17
44
SEG4
PC7
18
43
SEG3
PH0/INT4
19
42
SEG2
PA0/AN0
20
41
SEG1
Note) Do not make any connections to NC (Pin 73).
–5–
SEG0
COM3
COM2
COM1
COM0
VLC1
VLC2
VLC3
VL
VSS
XTAL
RST
EXTAL
PA7/AN7
PA6/AN6
PA5/AN5
PA4/AN4
PA3/AN3
PA2/AN2
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
PA1/AN1
PB1/CS0
CXP83620/83624, CXP83621/83625
Pin Description
Symbol
I/O
PA0/AN0
to
PA7/AN7
I/O/Analog input
PB0
I/O
PB1/CS0
I/O/Input
PB2/SCK0
I/O/I/O
PB3/SI0
I/O/Input
PB4/SO0
I/O/Output
PB5/SCK1
I/O/I/O
PB6/SI1
I/O/Input
PB7/SO1
I/O/Output
Functions
(Port A)
8-bit I/O port. I/O can
be set in a bit unit.
Standby release input
can be set in a bit unit.
Incorporation of pull-up
resistor can be set
through the program in
a bit unit.
(8 pins)
(Port B)
8-bit I/O port. I/O can
be set in a bit unit.
Incorporation of pull-up
resistor can be set
through the program in
a bit unit.
(8 pins)
Analog inputs to A/D converter.
(8 pins)
Chip select input for serial interface (CH0).
Serial clock I/O (CH0).
Serial data input (CH0).
Serial data output (CH0).
Serial clock I/O (CH1).
Serial data input (CH1).
Serial data output (CH1).
(Port C)
8-bit I/O port. I/O can be set in a bit unit. Capable of driving 12mA sink
current. Incorporation of pull-up resistor can be set through the program
in a bit unit.
(8 pins)
PC0 to PC7
I/O
PE0/INT0/EC
Input/Input/Input
PE1/INT1
Input/Input
PE2/INT2
Input/Input
PE3/INT3
Input/Input
PE4/RMC
Input/Input
PE5/TO
Output/Output
Output for 8-bit timer/counter rectangular wave.
PE6/ADJ
Output/Output
Output for TEX oscillation frequency division.
PH0/INT4
I/O/Input
PI0/TX
Input
PI1/TEX
Input/Input
External event inputs for 8-bit timer/counter.
(Port E)
7-bit port. Lower 5 bits
are for inputs; upper 2
bits are for outputs.
(7 pins)
External interruption request inputs.
(4 pins)
Remote control reception circuit input.
(Port H)
1-bit I/O port.
Incorporation of pull-up
resistor can be set
through the program.
(1 pin)
External interruption request input.
(1 pin)
(Port I)
2-bit input port.
(2 pins)
Crystal connectors for sub timer/counter clock
oscillation. For usage as event counter, input to
TEX, and leave TX open.
–6–
CXP83620/83624, CXP83621/83625
Symbol
I/O
Functions
PD0/SEG16
to
PD7/SEG23
Output/Output
PF0/SEG24
to
PF7/SEG31
Output/Output
(Port F)
8-bit output port.
(8 pins)
SEG0 to SEG15
Output
LCD segment signal output. (16 pins)
COM0 to COM3
Output
LCD common signal output. (4 pins)
VLC1 to VLC3
(Port D)
8-bit output port.
(8 pins)
LCD segment signal outputs.
(16 pins)
LCD bias power supply. (3 pins)
Control pin to cut off the current flowing to external LCD bias resistor
during standby.
VL
Output
EXTAL
Input
Crystal connectors for system clock oscillation. When the clock is supplied
externally, input to EXTAL; opposite phase clock should be input to XTAL.
Input
Low-level active system reset.
XTAL
RST
NC
NC. Do not make any connections to NC.
VDD
Positive power supply.
VSS
GND.
–7–
CXP83620/83624, CXP83621/83625
I/O Circuit Format for Pins
Pin
After a reset
Circuit format
Port A
∗
Pull-up resistor
"0" after a reset
Port A data
PA0/AN0
to
PA7/AN7
Port A direction
Input protection
circuit
IP
"0" after a reset
Internal data bus
Hi-Z
RD (Port A)
Port A function select
"0" after a reset
Edge detection
circuit
Standby release
Input multiplexer
A/D converter
∗ Pull-up transistor
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)
8 pins
Port B
∗
Pull-up resistor
"0" after a reset
Port B data
PB0
Hi-Z
Port B direction
IP
"0" after a reset
Internal data bus
RD (Port B)
∗ Pull-up transistor
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)
1 pin
Port B
∗
Pull-up resistor
"0" after a reset
Port B data
PB1/CS0
PB3/SI0
PB6/SI1
Hi-Z
Port B direction
IP
"0" after a reset
Schmitt input
Internal data bus
RD (Port B)
3 pins
CS0
SI0
SI1
–8–
∗ Pull-up transistor
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)
CXP83620/83624, CXP83621/83625
Pin
After a reset
Circuit format
Port B
∗
Pull-up resistor
"0" after a reset
Output buffer capability
"0" after a reset
PB2/SCK0
PB5/SCK1
SCK out
Serial clock output ebable
Port B function select
Hi-Z
"0" after a reset
Port B data
IP
Port B direction
"0" after a reset
Schmitt input
Internal
data bus
RD (Port B)
∗ Pull-up transistor
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)
2 pins
SCK in
Port B
∗
Pull-up resistor
"0" after a reset
Output buffer capability
"0" after a reset
PB4/SO0
PB7/SO1
SO
Serial data output ebable
Port B function select
Hi-Z
"0" after a reset
Port B data
IP
Port B direction
"0" after a reset
Internal
data bus
RD (Port B)
∗ Pull-up transistor
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)
2 pins
Port C
∗2
Pull-up resistor
"0" after a reset
Port C data
PC0 to PC7
∗1
Port C direction
IP
"0" after a reset
Internal data bus
RD (Port C)
∗1 High current drive
12mA (VDD = 4.5 to 5.5V)
4.5mA (VDD = 2.7 to 3.3V)
∗2 Pull-up transistor
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)
8 pins
–9–
Hi-Z
CXP83620/83624, CXP83621/83625
Pin
PE0/INT0/EC
PE1/INT1
PE2/INT2
PE3/INT3
PE4/RMC
After a reset
Circuit format
Port E
INT0/EC
INT1
INT2
INT3
RMC
Schmitt input
IP
Hi-Z
Internal data bus
RD (Port E)
5 pins
Port E
TO
Port E function select
"0" after a reset
PE5/TO
High level
Port E data
"1" after a reset
Internal data bus
1 pin
RD (Port E)
Port E
∗2
Internal reset signal
00
Port E data
"1" after a reset
∗1 ADJ32K
ADJ16K
PE6/ADJ
ADJ2K
MPX
01
10
11
Port E function select (upper)
Port E function select (lower)
∗1 ADJ signals are frequency driver
outputs for TEX oscillation frequency
adjustment.
ADJ2K provides usage as buzzer output.
∗2 Pull-up transistor
approx. 150kΩ (VDD = 4.5 to 5.5V)
approx. 200kΩ (VDD = 2.7 to 3.3V)
"00" after a reset
Internal data bus
RD (Port E)
1 pin
High level
High level
at ON
resistance
of pull-up
transistor
during a
reset.
Port H
∗
Pull-up resistor
"0" after a reset
Port H data
PH0/INT4
Hi-Z
Port H direction
IP
"0" after a reset
Schmitt input
Internal data bus
RD (Port H)
1 pin
INT4
– 10 –
∗ Pull-up transistor
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)
CXP83620/83624, CXP83621/83625
Pin
After a reset
Circuit format
Port I
TEX oscillation control circuit
"1" after a reset
Internal data bus
RD (Port I)
Internal data bus
PI0/TX
PI1/TEX
RD (Port I)
Schmitt input
IP
PI1/TEX
2 pins
IP
Clock input
Oscillation
halted port
input
PI0/TX
Port D
PD0/SEG16
to
PD7/SEG23
PF0/SEG24
to
PF7/SEG31
Port F
Port D, F data
Segment
Output
(VDD level)
Port/segment output select
"0" after a reset
Segment
driver
Segment data
16 pins
Segment
VCH
SEG0 to SEG15
VDD level
VCL
16 pins
Common
VDD
VLC1
COM0 to COM3
VDD level
VLC2
VLC3
4 pins
– 11 –
CXP83620/83624, CXP83621/83625
Pin
VL
LCD control
(DSP bit)
2 pins
RST
Hi-Z
"0" after a reset
1 pin
EXTAL
XTAL
After a reset
Circuit format
• Diagram shows circuit
composition during
oscillation.
EXTAL
IP
IP
• Feedback resistor is
removed during stop.
XTAL becomes high
level.
XTAL
A
Oscillation
Pull-up resistor
Low level
(during a reset)
Mask option OP
1 pin
IP
Schmitt input
– 12 –
CXP83620/83624, CXP83621/83625
Absolute Maximum Ratings
Item
(Vss = 0V)
Symbol
Rating
Unit
–0.3 to +7.0
V
Remarks
Supply voltage
VDD
LCD bias voltage
VLC1, VLC2,
–0.3 to +7.0∗1
VLC3
Input voltage
VIN
Output voltage
VOUT
High level output current
IOH
–5
mA
Output per pin
High level total output current
ΣIOH
–50
mA
Total for all output pins
IOL
15
mA
Value per pin, excluding high current
output pins
IOLC
20
mA
Value per pin for high current output pins∗2
Low level total output current
ΣIOL
100
mA
Total for all output pins
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +150
°C
600
mW
QFP-80P-L01
380
mW
LQFP-80P-L01
380
mW
QFP-80P-L03
Low level output current
Allowable power dissipation
PD
–0.3 to +7.0∗1
–0.3 to +7.0∗1
V
V
V
∗1 VIN and VOUT must not exceed VDD + 0.3V.
∗2 The high current drive transistor is the N-ch transistor of Port C (PC).
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
be conducted under the recommended operating conditions. Exceeding these conditions may adversely
affect the reliability of the LSI.
– 13 –
CXP83620/83624, CXP83621/83625
Recommended Operating Conditions
Item
Supply voltage
Symbol
(Vss = 0V)
Min.
Max.
4.5
5.5
2.7
5.5
2.7
5.5
2.7
5.5
Guaranteed operation range with TEX clock
2.5
5.5
Guaranteed data hold range during stop
Vss
VDD
V
LCD power supply range∗4
VIH
0.7VDD
VDD
V
∗1
VIHS
0.8VDD
VDD
V
VDD
Unit
Remarks
fc = 10MHz or less Guaranteed operation range
during 1/2 and 1/4 frequency
fc = 4MHz or less dividing mode
V
Guaranteed operation range during 1/16
frequency dividing mode or sleep mode
VLC1
LCD bias voltage
VLC2
VLC3
High level
input voltage
VIHEX
Low level
input voltage
Operating temperature
∗1
∗2
∗3
∗4
∗5
VDD – 0.4 VDD + 0.3
V
Hysteresis input∗2
EXTAL∗3, TEX∗5
∗1
VIL
0
0.3VDD
V
VILS
0
0.2VDD
V
VILEX
–0.3
0.4
V
Topr
–20
+75
°C
Hysteresis input∗2
EXTAL∗3, TEX∗5
Value for each pin of normal input ports (PA, PB0, PB4, PB7, PC and PI).
Value of the following pins; RST, CS0, SI0, SI1, SCK0, SCK1, EC/INT0, INT1, INT2, INT3, INT4 and RMC.
Specifies only during external clock input.
Optimal values are determined by LCD used.
Specifies only during external event count input.
– 14 –
CXP83620/83624, CXP83621/83625
Electrical Characteristics
DC Characteristics (VDD = 4.5 to 5.5V)
Item
Symbol
High level
VOH
output voltage
Low level
VOL
output voltage
IIHE
Pins
Input current
IIL
IIH
I/O leakage
current
IIZ
Common
output
impedance
RCOM
RSEG
Typ.
Max.
Unit
4.0
V
VDD = 4.5V, IOH = –2.4mA
3.5
V
PA, PB, PC,
PD∗2, PE5,
PE6,
PF∗2, PH0,
VL (VOL only)
VDD = 4.5V, IOH = –0.5mA
4.0
V
VDD = 4.5V, IOH = –1.2mA
3.5
V
VDD = 4.5V, IOL = 1.8mA
0.4
V
VDD = 4.5V, IOL = 3.6mA
0.6
V
PC
VDD = 4.5V, IOL = 12.0mA
1.5
V
EXTAL
TEX
RST∗3
VDD = 5.5V, VIH = 5.5V
0.5
40
V
VDD = 5.5V, VIL = 0.4V
–0.5
–40
µA
VDD = 5.5V, VIH = 5.5V
0.1
10
µA
–0.1
–10
µA
–1.5
–400
µA
–45
µA
VDD = 5.5V
VIL = 0.4V
PA to PC∗4,
PE0 to PE4, VDD = 4.5V, VIH = 4.0V
PH∗4, PI,
VDD = 5.5V
RST∗3
VI = 0, 5.5V
COM0 to
COM3
SEG0 to
SEG15,
SEG16 to
SEG31∗2
VDD = 5V
VLC1 = 3.75V
VLC2 = 2.5V
VLC3 = 1.25V
High-speed mode operation
(1/2 frequency dividing clock)
IDD1
Supply
current∗5
Min.
VDD = 4.5V, IOH = –1.0mA
IILT
IILR
Segment
output
impedance
Conditions
SCK0∗1, SO0∗1
SCK1∗1, SO1∗1
IILE
IIHT
(Ta = –20 to +75°C, Vss = 0V)
VDD = 5.5V, 10MHz crystal oscillation
(C1 = C2 = 15pF)
–2.78
µA
±10
µA
3
5
kΩ
5
15
kΩ
12
40
mA
2.6
8
mA
10
µA
Sleep mode
IDDS1
VDD
VDD = 5.5V, 10MHz crystal oscillation
(C1 = C2 = 15pF)
Stop mode
IDDS3
VDD = 5.5V, 10MHz and termination
of TEX oscillation
– 15 –
CXP83620/83624, CXP83621/83625
Item
Symbol
Input capacity CIN
Pins
Conditions
Clock 1MHz
PA to PC,
PE0 to PE4, PH, 0V for all pins excluding
PI, EXTAL, RST measured pins
Min.
Typ.
Max.
Unit
10
20
pF
∗1 Specifies when Port B output buffer capability switching register (BUFB: 01F4h) selects the buffer capability
to high.
∗2 Common pins of PD0/SEG16 to PD7/SEG23, PF0/SEG24 to PF7/SEG31, PD and PF is the case when the
common pin is selected as port; SEG16 to SEG31 is when the common pin is selected as segment output.
∗3 RST specifies the input current when pull-up resistor has been selected; leakage current when no resistor
has been selected.
∗4 Pins PA to PC, and PH0 specifies the input current when pull-up resistor has been selected; leakage
current when no resistor has been selected.
∗5 When all output pins are left open.
– 16 –
CXP83620/83624, CXP83621/83625
Electrical Characteristics
DC Characteristics (VDD = 2.7 to 3.3V)
Item
Symbol
High level
output voltage VOH
Low level
VOL
output voltage
Pins
IILE
IIHT
Input current
IILT
IILR
IIL
IIH
I/O leakage
current
IIZ
Common
output
impedance
RCOM
Segment
output
impedance
RSEG
Min.
Typ.
Max.
Unit
2.5
V
2.1
V
VDD = 2.7V, IOH = –0.12mA
2.5
V
VDD = 2.7V, IOH = –0.45mA
2.1
V
PA, PB, PC,
PD∗2, PE5,
PE6,
PF∗2, PH0,
VL (VOL only)
EXTAL
TEX
RST∗3
VDD = 2.7V, IOL = 1.0mA
0.25
V
VDD = 2.7V, IOL = 1.4mA
0.4
V
VDD = 2.7V, IOL = 4.5mA
0.9
V
VDD = 3.3V, VIH = 3.3V
0.3
20
V
VDD = 3.3V, VIL = 0.3V
–0.3
–20
µA
VDD = 3.3V, VIH = 3.3V
0.1
10
µA
–0.1
–10
µA
–0.9
–200
µA
–20
µA
VDD = 3.3V
VIL = 0.3V
PA to PC∗4,
PE0 to PE4, VDD = 2.7V, VIH = 2.4V
PH∗4, PI,
VDD = 3.3V
RST∗3
VI = 0, 3.3V
COM0 to
COM3
SEG0 to
SEG15,
SEG16 to
SEG31∗2
VDD = 3V
VLC1 = 2.25V
VLC2 = 1.5V
VLC3 = 0.75V
High-speed mode operation
(1/2 frequency dividing clock)
IDD1
VDD = 3.3V, 4MHz crystal oscillation
(C1 = C2 = 15pF)
VDD = 3.3V, TEX∗6 crystal oscillation
(C1 = C2 = 47pF)
IDD2
Supply
current∗5
Conditions
SCK0∗1, SO0∗1 VDD = 2.7V, IOH = –0.24mA
SCK1∗1, SO1∗1 VDD = 2.7V, IOH = –0.90mA
PC
IIHE
(Ta = –20 to +75°C, Vss = 0V)
0.9
µA
±10
µA
4.5
7.5
kΩ
10
30
kΩ
2.5
8
mA
30
100
µA
0.6
2
mA
16
30
µA
10
µA
Sleep mode
IDDS1
IDDS2
VDD
VDD = 3.3V, 4MHz crystal oscillation
(C1 = C2 = 15pF)
VDD = 3.3V, TEX∗6 crystal oscillation
(C1 = C2 = 47pF)
Stop mode
IDDS3
VDD = 3.3V, 4MHz and
termination of TEX oscillation
– 17 –
CXP83620/83624, CXP83621/83625
Item
Symbol
Input capacity CIN
Pins
Conditions
Clock 1MHz
PA to PC,
PE0 to PE4, PH, 0V for all pins excluding
PI, EXTAL, RST measured pins
Min.
Typ.
Max.
Unit
10
20
pF
∗1 Specifies when Port B output buffer capability switching register (BUFB: 01F4h) selects the buffer capability
to high.
∗2 Common pins of PD0/SEG16 to PD7/SEG23, PF0/SEG24 to PF7/SEG31, PD and PF is the case when the
common pin is selected as port; SEG16 to SEG31 is when the common pin is selected as segment output.
∗3 RST specifies the input current when pull-up resistor has been selected; leakage current when no resistor
has been selected.
∗4 Pins PA to PC, and PH0 specifies the input current when pull-up resistor has been selected; leakage
current when no resistor has been selected.
∗5 When all output pins are left open.
∗6 The value when 32.768kHz oscillator is connected to TEX.
– 18 –
CXP83620/83624, CXP83621/83625
AC Characteristics
(1) Clock timing
(Ta = –20 to +75°C, VDD = 2.7 to 5.5V, Vss = 0V)
Item
Symbol
Pin
Conditions
Min.
VDD = 4.5 to 5.5V
System clock frequency
fC
XTAL
EXTAL
Fig. 1, Fig. 2
System clock input pulse
width
tXL,
tXH
EXTAL
Fig. 1, Fig. 2 VDD = 4.5 to 5.5V
external clock drive
System clock input rise and
fall time
EXTAL
Fig. 1, Fig. 2
external clock drive
EC
Fig. 3
Event count input clock rise
and fall time
tCR,
tCF
tEH,
tEL
tER,
tEF
EC
Fig. 3
System clock frequency
fC
TEX
TX
VDD = 2.7 to 5.5V
Fig. 2 (32kHz clock
applied condition)
Event count input clock input
pulse width
tTL,
tTH
tTR,
tTF
TEX
Fig. 3
TEX
Fig. 3
Event count input clock pulse
width
Event count input clock rise
and fall time
Typ.
Max.
1
10
1
5
37.5
Unit
MHz
ns
77.5
200
tsys + 50∗1
ns
ns
20
ms
kHz
32.768
µs
10
20
ms
∗1 tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock
control register (CLC: 00FEh).
tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”).
1/fc
VDD – 0.4V
EXTAL
0.4V
tXH
tCF
tXL
tCR
Fig. 1. Clock timing
AAAA
AAAA
AAAA
AAAAAAAAAAAA
Crystal oscillation
Ceramic oscillation
EXTAL
C1
TEX clock applied condition
Crystal oscillation
External clock
EXTAL
XTAL
C2
TEX
XTAL
74HC04
TX
C2
C1
Fig. 2. Clock applied conditions
0.8VDD
TEX
EC
0.2VDD
tEH
tTH
tEF
tTF
tEL
tTL
Fig. 3. Event count clock timing
– 19 –
tER
tTR
CXP83620/83624, CXP83621/83625
(2) Serial transfer (CH0)
Item
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Symbol
Pin
Conditions
Max.
Unit
CS ↓ → SCK
delay time
tDCSK
SCK0
Chip select transfer mode
(SCK = output mode)
tsys + 200
ns
CS ↑ → SCK
float delay time
tDCSKF
SCK0
Chip select transfer mode
(SCK = output mode)
tsys + 200
ns
CS ↓ → SO
delay time
tDCSO
SO0
Chip select transfer mode
tsys + 200
ns
CS ↓ → SO
float delay time
tDCSOF SO0
Chip select transfer mode
tsys + 200
ns
CS high level width
tWHCS
CS0
Chip select transfer mode
SCK cycle time
tKCY
SCK0
SCK high and low
level widths
tKH
tKL
SCK0
SI input setup time
(for SCK ↑)
tSIK
SI0
SI input hold time
(for SCK ↑)
tKSI
SI0
SCK ↓ → SO
delay time
tKSO
SO0
Input mode
Output mode
Input mode
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
Min.
tsys + 200
2tsys + 200
ns
16000/fc
ns
tsys + 100
ns
8000/fc – 100
ns
–tsys + 100
ns
200
ns
2tsys + 100
ns
100
ns
ns
2tsys + 200
ns
100
ns
Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the
clock control register (CLC: 00FEh).
tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”)
Note 2) CS, SCK, SI and SO indicates CS0, SCK0, SI0 and SO0, respectively.
Note 3) The load condition for the SCK output mode, SO output delay time is 50pF + 1TTL.
Note 4) The value when Port B output buffer capability switching register (BUFB: 01F4h) selects buffer
capability to normal.
– 20 –
CXP83620/83624, CXP83621/83625
Serial transfer (CH0)
Item
(Ta = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V)
Symbol
Pin
Conditions
Max.
Unit
CS ↓ → SCK
delay time
tDCSK
SCK0
Chip select transfer mode
(SCK = output mode)
tsys + 250
ns
CS ↑ → SCK
float delay time
tDCSKF
SCK0
Chip select transfer mode
(SCK = output mode)
tsys + 200
ns
CS ↓ → SO
delay time
tDCSO
SO0
Chip select transfer mode
tsys + 250
ns
CS ↓ → SO
float delay time
tDCSOF SO0
Chip select transfer mode
tsys + 200
ns
CS high level width
tWHCS
CS0
Chip select transfer mode
SCK cycle time
tKCY
SCK0
SCK high and low
level widths
tKH
tKL
SCK0
SI input setup time
(for SCK ↑)
tSIK
SI0
SI input hold time
(for SCK ↑)
tKSI
SI0
SCK ↓ → SO
delay time
tKSO
SO0
Input mode
Output mode
Input mode
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
Min.
tsys + 200
2tsys + 200
ns
16000/fc
ns
tsys + 100
ns
8000/fc – 150
ns
–tsys + 100
ns
200
ns
2tsys + 100
ns
100
ns
ns
2tsys + 250
ns
125
ns
Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the
clock control register (CLC: 00FEh).
tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”)
Note 2) CS, SCK, SI and SO indicates CS0, SCK0, SI0 and SO0, respectively.
Note 3) The load condition for the SCK output mode, SO output delay time is 50pF.
Note 4) The value when Port B output buffer capability switching register (BUFB: 01F4h) selects buffer
capability to high.
– 21 –
CXP83620/83624, CXP83621/83625
tWHCS
CS0
0.8VDD
0.2VDD
tKCY
tDCSK
tKL
tDCSKF
tKH
0.8VDD
0.8VDD
SCK0
0.2VDD
tSIK
tKSI
0.8VDD
SI0
Input data
0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD
SO0
Output data
0.2VDD
Fig. 4. Serial transfer CH0 timing
– 22 –
CXP83620/83624, CXP83621/83625
Serial Transfer (CH1)
Item
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Symbol
Pin
SCK cycle time
tKCY
SCK1
SCK high and low level
widths
tKH
tKL
SCK1
SI input setup time
(for SCK ↑)
tSIK
SI1
SI input hold time
(for SCK ↑)
tKSI
SI1
SCK ↓ → SO delay time
tKSO
SO1
Conditions
Min.
Max.
Unit
1000
ns
8000/fc
ns
400
ns
4000/fc – 50
ns
SCK input mode
100
ns
SCK output mode
200
ns
SCK input mode
200
ns
SCK output mode
100
ns
Input mode
Output mode
Input mode
Output mode
SCK input mode
200
ns
SCK output mode
100
ns
Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the
clock control register (CLC: 00FEh).
tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”)
Note 2) SCK, SI and SO indicates SCK1, SI1 and SO1, respectively.
Note 3) The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL.
Note 4) The value when Port B output buffer capability switching register (BUFB: 01F4h) selects buffer
capability to normal.
Serial Transfer (CH1)
Item
(Ta = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V)
Symbol
Pin
SCK cycle time
tKCY
SCK1
SCK high and low level
widths
tKH
tKL
SCK1
SI input setup time
(for SCK ↑)
tSIK
SI1
SI input hold time
(for SCK ↑)
tKSI
SI1
SCK ↓ → SO delay time
tKSO
SO1
Conditions
Min.
Max.
Unit
1000
ns
8000/fc
ns
400
ns
4000/fc – 100
ns
SCK input mode
100
ns
SCK output mode
200
ns
SCK input mode
200
ns
SCK output mode
100
ns
Input mode
Output mode
Input mode
Output mode
SCK input mode
250
ns
SCK output mode
125
ns
Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the
clock control register (CLC: 00FEh).
tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”)
Note 2) SCK, SI and SO indicates SCK1, SI1 and SO1, respectively.
Note 3) The load condition for the SCK1 output mode, SO1 output delay time is 50pF.
Note 4) The value when Port B output buffer capability switching register (BUFB: 01F4h) selects buffer
capability to high.
– 23 –
CXP83620/83624, CXP83621/83625
tKCY
tKL
tKH
0.8VDD
SCK1
0.2VDD
tSIK
tKSI
0.8VDD
SI1
Input data
0.2VDD
tKSO
0.8VDD
SO1
Output data
0.2VDD
Fig. 5. Serial transfer CH1 timing
– 24 –
CXP83620/83624, CXP83621/83625
(3) A/D converter characteristics
Item
Symbol
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Max.
Unit
Resolution
8
Bits
Linearity error
±3
LSB
Zero transition
voltage
VZT∗1
Full-scale transition
voltage
VFT∗2
Conversion time
Sampling time
tCONV
tSAMP
Analog input voltage
VIAN
Pin
Conditions
Ta = 25°C
VDD = 5.0V
VSS = 0V
Min.
Typ.
–10
10
70
mV
4910
4970
5030
mV
31/fADC∗3
10/fADC∗3
AN0 to AN7
µs
µs
0
VDD
V
(Ta = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V)
Item
Symbol
Max.
Unit
Resolution
8
Bits
Linearity error
±3
LSB
Zero transition
voltage
VZT∗1
Full-scale transition
voltage
VFT∗2
Conversion time
Sampling time
tCONV
tSAMP
Analog input voltage
VIAN
Pin
Conditions
Ta = 25°C
VDD = 2.7V
VSS = 0V
Min.
Typ.
–10
11
40
mV
2651
2688
2716
mV
31/fADC∗3
10/fADC∗3
AN0 to AN7
0
µs
µs
VDD
V
Digital conversion value
FFh
FEh
∗1 VZT: Value at which the digital conversion value changes
from 00h to 01h and vice versa.
∗2 VFT: Value at which the digital conversion value changes
from FEh to FFh and vice versa.
∗3 fADC = fc/4
Linearity error
01h
00h
VFT
VZT
Analog input
Fig. 6. Definition of A/D converter terms
– 25 –
CXP83620/83624, CXP83621/83625
(4) Interruption, reset input
Item
(Ta = –20 to +75°C, VDD = 2.7 to 5.5V, Vss = 0V)
Symbol
Pin
External interruption
high and low level widths
tIH
tIL
INT0
INT1
INT2
INT3
INT4
Reset input low level width
tRSL
RST
Conditions
Min.
Max.
Unit
1
µs
32/fc
µs
tIH
tIL
0.8VDD
0.2VDD
INT0
INT1
INT2
INT3
INT4
tIL
tIH
Fig. 7. Interruption input timing
tRSL
RST
0.2VDD
Fig. 8. RST input timing
– 26 –
CXP83620/83624, CXP83621/83625
Appendix
AAAA
AAAA
AAAA
AAAA
EXTAL
AAAA
AAAA
(iii) Sub clock
(ii) Main clock
(i) Main clock
EXTAL
XTAL
EXTAL
TEX
XTAL
Rd
Rd
Rd
C2
C1
XTAL
TX
C2
C1
C1 C2
Fig. 9. SPC700 series recommended oscillation circuit
MURATA MFG
CO., LTD.
C1 (pF)
C2 (pF)
Rd (Ω)
CSA4.19MG
4.19
100
100
0
CSA8.00MG
8.00
30
30
0
CSA10.0MT
10.00
30
30
0
CST4.19MGW∗1
4.19
100
100
0
8.00
30
30
0
10.00
30
30
0
4.19
22
22
1.0k
8.00
15
15
100
10.00
10
10
100
4.19
33
33
2.2k
CL = 12.0pF
8.00
18
18
0
CL = 12.0pF
10.00
15
15
0
CL = 12.0pF
CST8.00MTW∗1
CST10.00MTW∗1
RIVER
ELETEC
CO., LTD.
HC-49/U03
KINSEKI LTD.
CX-5F
FCR4.19MC5∗1
FCR8.0MC5∗1
FCR10.0MC5∗1
CCR4.19MC3∗1
TDK
Corporation
Circuit
example
fc (MHz)
Model
Manufacturer
CCR8.0MC5∗1
CCR10.0MC5∗1
VTC-200
Seiko
Instruments Inc. SP-T
4.19
30 ( ± 20%) 30( ± 20%)
8.00
20 ( ± 20%) 20( ± 20%)
10.00
20 ( ± 20%) 20( ± 20%)
4.19
36 ( ± 20%) 36( ± 20%)
8.00
20 ( ± 20%) 20( ± 20%)
10.00
20 ( ± 20%) 20( ± 20%)
32.768
18
18
330k
75.00
4
4
100k
∗1 Those marked with an ∗1 signify types with
built-in ground capacitance (C1, C2).
Item
Content
Existent
Non-existent
Package List
Product name
(i)
(ii)
(i)
(ii)
(iii)
CL = 12.5pF
CL = 6.0pF
FCR∗∗∗: Lead-type ceramic oscillator
CCR∗∗∗: Surface mounted-type ceramic oscillator
CL
: Load Capacitor
Mask Option Table
Reset pin pull-up resistor
0
Remarks
Package
CXP83620/83624
80-pin plastic QFP/LQFP
CXP83621/83625
80-pin plastic QFP (0.65mm pitch)
– 27 –
CXP83620/83624, CXP83621/83625
Characteristics Curve
IDD vs. VDD
(fc = 10MHz, Ta = 25°C, typical)
1/2 frequency dividing mode
10.0
1/4 frequency dividing mode
IDD – Supply current [mA]
5.0
1/16 frequency dividing mode
Sleep mode
1.0
0.5
0.1
(100µA)
32kHz mode
(instruction)
0.05
(50µA)
0.01
(10µA) 1
32kHz
Sleep mode
2
4
3
5
6
7
VDD – Supply voltage [V]
IDD vs. fc
(VDD = 5V, Ta = 25°C, typical)
IDD – Supply current [mA]
15
10
1/2 frequency dividing mode
1/4 frequency dividing mode
5
1/16 frequency dividing mode
Sleep mode
0
0
5
fc – System clock [MHz]
– 28 –
10
CXP83620/83624, CXP83621/83625
Package Outline
Unit: mm
CXP83620/83624
80PIN QFP (PLASTIC)
23.9 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
20.0 – 0.1
64
0.15
41
65
16.3
17.9 ± 0.4
+ 0.4
14.0 – 0.1
40
A
+ 0.2
0.1 – 0.05
25
1
24
+ 0.15
0.35 – 0.1
0.8
0.2
M
0.8 ± 0.2
80
+ 0.35
2.75 – 0.15
0° to 10°
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SOLDER PLATING
SONY CODE
QFP-80P-L01
LEAD TREATMENT
EIAJ CODE
QFP080-P-1420
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
1.6g
JEDEC CODE
CXP83620/83624
80PIN LQFP (PLASTIC)
14.0 ± 0.2
∗
12.0 ± 0.1
60
41
40
(13.0)
61
21
(0.22)
80
0.5
0.5 ± 0.2
A
1
+ 0.08
0.18 – 0.03
20
0.13 M
+ 0.2
1.5 – 0.1
+ 0.05
0.127 – 0.02
0.1
0° to 10°
0.5 ± 0.2
0.1 ± 0.1
NOTE: Dimension “∗” does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
LQFP-80P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
LQFP080-P-1212
LEAD MATERIAL
42 ALLOY
PACKAGE MASS
0.5g
JEDEC CODE
– 29 –
CXP83620/83624, CXP83621/83625
CXP83621/83625
80PIN QFP (PLASTIC)
+ 0.35
1.5 – 0.15
+ 0.1
0.127 – 0.05
16.0 ± 0.4
+ 0.4
14.0 – 0.1
60
0.1
41
40
80
21
(15.0)
61
+ 0.15
0.3 – 0.1
20
0.24
M
0° to 10°
0.5 ± 0.2
1
0.65
+ 0.15
0.1 – 0.1
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-80P-L03
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
QFP080-P-1414
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
0.6g
JEDEC CODE
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