SONY CXP875P40

CXP875P40
CMOS 8-bit Single Chip Microcomputer
Description
The CXP875P40 is a CMOS 8-bit micro-computer
which consists of arithmetic coprocessor, A/D
converter, serial interface, timer/counter, time base
timer, vector interruption, high precision timing
pattern generation circuit, PWM generator and the
measuring circuit which measure signals of capstan
FG, drum FG/PG, reel FG and other servo systems,
as well as basic configurations like 8-bit CPU,
PROM, RAM and I/O port. They are integrated into a
single chip.
Also this IC provides power on reset function,
sleep/stop function which enables to lower power
consumption.
The CXP875P40 is the one-chip PROM version of
the CXP87532/87540 with mask ROM, providing the
function of being able to write directly into the
program. It is suitable for evaluation use during
system development and for small quantity
production.
100 pin QFP (Plastic)
100 pin LQFP (Plastic)
Structure
Silicon gate CMOS IC
Features
• A wide instruction set (213 instructions) which cover various types of data
— 16-bit operation code/multiplying instruction/boolean bit operation instruction
• Minimum instruction cycle
During operation 326ns/12.288MHz
• Incorporated PROM capacity
40K bytes
• Incorporated RAM capacity
1344 bytes
• Peripheral functions
— Arithmetic coprocessor
Multiplying with code, sum of products with code, high speed
execution of many bits shift rotation operation
— A/D converter
8-bit, 8-channel, successive approximation system
(Conversion time 13µs/12.288MHz)
Incorporated 3-stage FIFO for A/D conversion data
— Serial interface
Incorporated buffer RAM for data
(1 to 128 bytes auto transfer) 2-channel
— Timer
8-bit timer, 8-bit timer/counter, 19-bit time base timer
— High precision timing pattern generator PPG (11 pins) 32-stage programmable
— PWM output
12-bit, 2-channel (Repeated frequency 48kHz)
8-bit, 3-channel (Repeated frequency 48kHz)
— Servo input control
Capstan FG, Drum FG/PG, Reel FG input
— FRC capture unit
Incorporated 28-bit and 8-stage FIFO
• Interruption
12 factors, 12 vectors, multi-interruption possible
• Standby mode
SLEEP/STOP
• Package
100-pin plastic QFP/LQFP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E94317-PS
8
PE1/EC
PG2/DREF
PG3/DPG
PG4/DFG
PG5/CFG
PG6/RFG0
PG7/RFG1
PA3/PROUT
PG0/EXI0
PG1/EXI1
CS0
SI0
SO0
SCK0
PH3/CS1
PH2/SI1
PH1/SO1
PH0/SCK1
PE7/SWP
PA6/AREA
PA4/ATFS1
PA5/ATFS3
PA7/ATFS2
PK0/RFDT
PK1/MCLK
FIFO
RAM
SERVO
INPUT
CONTROL
8BIT TIMER 1
8BIT TIMER/COUNTER 0
SERIAL
INTERFACE
UNIT
REEL
CAPSTAN
DRUM
SWITCHING PULSE
GENRATOR
ATF SYNC UNIT
A/D CONVERTER
12BIT PWM GENERATOR 2CH
PE5/PWM3
PE6/PWM4
PF0/AN0
to PF7/AN7
AVDD
AVREF
AVSS
8BIT PWM GENERATOR 3CH
PE2/PWM0
PE3/PWM1
PE4/PWM2
6
INTERRUPT CONTROLLER
PROGRAMMABLE
PATTERN
GENERATOR
FRC
CAPTURE
UNIT
PE0/INT0
PE3/INT1
PE1/INT2
NM1
PB0/PPO0
to
PA2/PPO10
RAM
FIFO
PROM
40K BYTES
CO-PROCESSOR
SPC700
CPU CORE
VSS
VPP
EXTAL
XTAL
RST
MP
VDD
PRESCALER/
TIME BASE TIMER
RAM
1120 BYTES
CLOCK GENERATOR/
SYSTEM CONTROL
PORT A
PORT B
PORT C
PORT D
PORT E
PORT F
PORT G
PORT H
PK0 to PK3
PI0 to PI7
PH4 to PH7
PH0 to PH3
PG0 to PG7
PF0 to PF7
PE2 to PE7
PE0 to PE1
PD0 to PD7
PC0 to PC7
PB0 to PB7
PA0 to PA7
PJ0 to PJ7
PORT I
PORT J
–2–
PORT K
Block Diagram
CXP875P40
CXP875P40
PE5/PWM3
PE3/PWM1
PE4/PWM2
PE2/PWM0
PE0/INT0
PE1/INT2/EC
NMI
VDD
VSS
VPP
PA6/AREA
PA7/ATFS2
PA4/ATFS1
PA5/ATFS3
PA2/PPO10
PA3/PROUT
PA0/PPO8
PA1/PPO9
PB7/PPO7
PB6/PPO6
Pin Configuration 1 (Top View) 100pin QFP
A
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
PPO5/PB5
1
PPO4/PB4
2
PPO3/PB3
3
PPO2/PB2
4
PPO1/PB1
5
PPO0/PB0
80
PE6/PWM4
79
PE7/SWP
78
PK0/RFDT
77
PK1/MCLK
76
PK2
6
75
PK3
PC7
7
74
PG0/EXI0
PC6
8
73
PG1/EXI1
PC5
9
72
PG2/DREF
PC4
10
71
PG3/DPG
PC3
11
70
PG4/DFG
PC2
12
69
PG5/CFG
PC1
13
68
PG6/RFG0
PC0
14
67
PG7/RFG1
PD7
15
66
PF0/AN0
PD6
16
65
PF1/AN1
PD5
17
64
PF2/AN2
PD4
18
63
PF3/AN3
PD3
19
62
PF4/AN4
PD2
20
61
PF5/AN5
PD1
21
60
PF6/AN6
PD0
22
59
PF7/AN7
PI7
23
58
AVDD
PI6
24
57
AVREF
PI5
25
56
AVSS
PI4
26
55
SCK0
PI3
27
54
SO0
PI2
28
53
SI0
PI1
29
52
CS0
PI0
30
51
PH0/SCK1
SO1/PH1
SI1/PH2
PH4
CS1/INT1/PH3
PH5
PH7
PH6
EXTAL
VSS
XTAL
MP
RST
PJ0
PJ1
PJ3
PJ2
PJ4
PJ5
PJ7
PJ6
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note) 1. VPP (Pin 90) is always connected to VDD.
2. VSS (Pins 41 and 88) are both connected to GND.
3. MP (Pin 39) is always connected to VSS.
–3–
CXP875P40
PK0/RFDT
PE6/PWM4
PE7/SWP
PE5/PWM3
PE4/PWM2
PE2/PWM0
PE3/PWM1
PE0/INT0
PE1/EC/INT2
NMI
VSS
VPP
VDD
PA6/AREA
PA7/ATFS2
PA4/ATFS1
PA5/ATFS3
PA2/PPO10
PA3/PROUT
PA0/PPO8
PA1/PPO9
PB7/PPO7
PB5/PPO5
PB6/PPO6
PB4/PPO4
Pin Configuration 2 (Top View) 100pin LQFP
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
PBO3/PB3
1
PPO2/PB2
2
PPO1/PB1
3
PPO0/PB0
4
PC7
5
PC6
6
PC5
7
PC4
AA
AA
75
PK1/MCLK
74
PK2
73
PK3
72
PG0/EXI0
71
PG1/EXI1
70
PG2/DREF
69
PG3/DPG
8
68
PG4/DFG
PC3
9
67
PG5/CFG
PC2
10
66
PG6/RFG0
PC1
11
65
PG7/RFG1
PC0
12
64
PF0/AN0
PD7
13
63
PF1/AN1
PD6
14
62
PF2/AN2
PD5
15
61
PF3/AN3
PD4
16
60
PF4/AN4
PD3
17
59
PF5/AN5
PD2
18
58
PF6/AN6
PD1
19
57
PF7/AN7
PD0
20
56
AVDD
PI7
21
55
AVREF
PI6
22
54
AVSS
PI5
23
53
SCK0
PI4
24
52
SO0
PI3
25
51
SI0
Note) 1. VPP (Pin 88) is always connected to VDD.
2. VSS (Pins 39 and 86) are both connected to GND.
3. MP (Pin 37) is always connected to VSS.
–4–
CS0
SCK1/PH0
SO1/PH1
SI1/PH2
CS1/INT1/PH3
PH5
PH4
PH6
PH7
XTAL
EXTAL
VSS
RST
MP
PJ0
PJ1
PJ2
PJ4
PJ3
PJ5
PJ6
PJ7
PI0
PI2
PI1
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
CXP875P40
Pin Description
Symbol
I/O
Description
PA0/PPO8
PA1/PPO9
PA2/PPO10
PA3/PROUT
Output/
Real time output
PA4/ATFS1
PA5/ATFS3
PA6/AREA
PA7/ATFS2
Output/
Monitor output
PB0/PPO0
to
PB7/PPO7
Output/
Real time output
(Port B)
8-bit output port. Data is gated Programmable pattern generator (PPG)
output. (8 pins)
with PPO by OR-gate and
they are output. (8 pins)
PC0 to PC7
I/O
(Port C)
8-bit input/output port, enables to specify input/output by 4-bit unit.
(8 pins)
PD0 to PD7
I/O
(Port D)
8-bit input/output port. Lower 4 bits can be specified as input/output by
bit unit and upper 4 bits can be specified as input/output by 4-bit unit.
(8 pins)
PE0/INT0
Input/Input
PE1/EC/INT2
Input/Input/
Input
PE2/PWM0
to
PE6/PWM4
Output/Output
PE7/SWP
Output/Output
(Port A)
8-bit output port.
Data is gated with PPO
(3 pins), monitor signal
(4 pins) in relation to ATF,
control signal (1 pin) for
capstan servo by OR-gate
and they are output. (8 pins)
Programmable pattern generator (PPG)
Output (3 pins) and capstan servo control
signal (1 pin).
Monitor output in relation to ATF.
(4 pins)
Input pin to request external interruption.
Active when falling edge.
(Port E)
8-bit port. Lower 2 bits
are input pins and upper
6 bits are output pins.
(8 pins)
External event
input pin for
timer/counter.
Input pin to request external
interruption. Active when
falling edge.
PWM output pins (5 pins)
SWP output pin.
(Port F)
8-bit input port. (8 pins)
Upper 4 bits serve as
standby release input pin.
PF0/AN0
to
PF7/AN7
Input/Input
PG0/EXI0
Input/Input
External input pin 0.
PG1/EXI1
Input/Input
External input pin 1.
PG2/DREF
Input/Input
Drum reference signal input pin.
PG3/DPG
Input/Input
PG4/DFG
Input/Input
PG5/CFG
Input/Input
PG6/RFG0
Input/Input
PG7/RFG1
Input/Input
(Port G)
8-bit input port.
(8 pins)
Analog input pins to A/D converter.
(8 pins)
Drum PG input pin.
Drum FG input pin.
Capstan FG input pin.
Reel FG input pin.
–5–
CXP875P40
Symbol
I/O
Description
PH0/SCK1
Input/I/O
PH1/SO1
Input/Output
PH2/SI1
Input/Input
PH3/INT1/
CS1
Input/Input/Input
PH7 to PH4
Output
(Port H)
4-bit output port. N-ch open drain output of middle tension proof (12V)
and high current (12mA). (4 pins)
PI0 to PI7
I/O
(Port I)
8-bit input/output port, enables to specify input/output by 4-bit unit.
(8 pins)
PJ0 to PJ7
I/O
(Port J)
8-bit input/output port, enables to specify input/output by 4-bit unit.
(8 pins)
PK0/RFDT
I/O/Input
PK1/MCLK
I/O/Input
PK2 to PK3
I/O
(Port K)
4-bit input/output port,
enables to specify input/
output by bit unit. (4 pins)
SCK0
I/O
Serial clock input/output pin.
SO0
Output
Serial data output pin.
SI0
Input
Serial data input pin.
CS0
Input
Chip select input pin to serial interface.
NMI
Input
Non-maskable interrupt request pin. Active during falling edge.
EXTAL
Input
XTAL
Output
Connecting pin of crystal oscillator for system clock. When supplying
the external clock, input the external clock to EXTAL pin and set XTAL
pin to open.
RST
I/O
System reset pin of active “L” level. RST pin is input/output pin, which
output “L” level by incorporated power on reset function when power
ON. (Mask option)
MP
Input
Test mode pin. This pin is always connected to GND.
Serial clock input/output pin.
Serial data output pin.
Serial data input pin.
Input pin to request
external interruption.
Chip select input pin to serial interface.
Active when falling edge.
Playback data input pin.
Channel clock input pin.
Positive power supply pin of A/D converter.
Set the same voltage as VDD.
AVDD
AVREF
(Port H)
4-bit input port.
(4 pins)
Input
Reference voltage input pin of A/D converter.
AVSS
GND pin of A/D converter.
VDD
Positive power supply pin.
VPP
Positive power supply pin for incorporated PROM writing.
In normal operation, connect to VDD.
VSS
GND pin. Connect both VSS pins to GND.
–6–
CXP875P40
I/O Circuit Formats for Pins
Pin
PA0/PPO8
to
PA2/PPO10
PA3/PROUT
PA4/ATFS1
PA5/ATFS3
PA6/AREA
PA7/ATFS2
PB0/PPO0
to
PB7/PPO7
16 pins
Circuit format
Port B
PPO, PROUT,
ATFS1 to ATFS3,
AREA, data
AAA
Port A or Port B
Hi-Z
Output becomes active from high impedance
by data writing to port register.
Data bus
RD
AAAA
AAAA
AAAA
AAAA
Port C
Port C data
PC0
to
PC7
AA
AA
Port A
When reset
AA
AA
AA
IP
Port C direction
(Every 4 bits)
Data bus
Input protection
circuit
Hi-Z
RD (Port C)
Buffer
8 pins
AAAA
AAAA
AAAA
AAAA
AA
AA
AA
Port D
Port D data
PD0
to
PD7
Large current
12mA
IP
Port D direction
Lower 4 bits are by bit unit
and upper 4 bits are by 4bit unit
Data bus
8 pins
Hi-Z
RD (Port D)
Port E
AAAA
AA
Schmitt input
PE0/INT0
PE1/EC/
INT2
IP
Data bus
RD (Port E)
2 pins
–7–
Hi-Z
CXP875P40
Pin
AAA
AAA
AAAAA
AAA
AAAAA
AAA
AAAAA
AA
AA
AAA
AAA
AAAAA
AAA
AAAAA
AAA
AAAAA
AA
AA
Circuit format
When reset
Port E
PWM output
MPX
Hi-Z control
PE2/PWM0
PE3/PWM1
PE4/PWM2
PE5/PWM3
Port E data
Hi-Z
Port/PWM output
select
Data bus
RD (Port E)
4 pins
Port E
PWM, SWP output
MPX
PE6/PWM4
PE7/SWP
Port E data
H level
Port/PWM, SWP
output select
Data bus
RD (Port E)
2 pins
Port F
AAAA
AA AAAAA
AAAAA
Input multiplexer
IP
PF0/AN0
to
PF7/AN7
A/D converter
Analog/Digial
tinput select
Hi-Z
Data bus
RD (Port F)
8 pins
Port G
PG0/EXI0
PG1/EXI1
PG2/DREF
PG3/DPG
PG4/DFG
PG5/CFG
PG6/RFG0
PG7/RFG1
AA
AA
AAAA
Schmitt input
Servo input
IP
Data bus
RD (Port G)
For PG0/EXI0 to PG7/RFG1, TTL schmitt input can be
selected with the mask option.
8 pins
–8–
Hi-Z
CXP875P40
Pin
Circuit format
AA
AA
AA
AA
Port H
Internal serial clock from SI0
When reset
IP
SCK1 output enable
PH0/SCK1
Hi-Z
Schmitt input
External serial clock to SI0
Data bus
RD (Port H)
1 pin
Port H
AA
AA
AA
AA
SO1 from SI0
PH1/SO1
IP
SO1 output enable
Data bus
Hi-Z
RD (Port H)
1 pin
Port H
AA
AA
AAAA
Schmitt input
PH2/SI1
PH3/CS1/
INT1
IP
Hi-Z
Data bus
RD (Port H)
2 pins
AA
AA
Port H
PH4
to
PH7
Middle tension
proof 12V
AAAA
AAAA
Port H data
Large current
12mA
Data bus
RD (Port H)
4 pins
–9–
Open
CXP875P40
Pin
Circuit format
Port I
AAAA
AAAA
AAAA
AAAA
Port I data
PI0
to
PI7
When reset
AA
AA
AA
IP
Port I direction
(Every 4 bits)
Data bus
Input protection
circuit
Hi-Z
RD (Port I)
Buffer
8 pins
Port J
AAAA
AAAA
AAAA
AAAA
Port J data
PJ0
to
PJ7
AA
AA
AA
Hi-Z
IP
Port J direction
(Every 4 bits)
Data bus
RD (Port J)
8 pins
AAAA
AAAA
AAAA
AAAA
Port K
Port K data
PK0/RFDT
IP
Port K direction
(Every bit)
Data bus
RD (Port K)
1 pin
AA
AA
AA
Servo input
Buffer amplifier input can be selected with the mask option.
– 10 –
Input protection
circuit
Hi-Z
When buffer
amplifier input is
selected, pulled
up interually
during standby.
CXP875P40
Pin
Port K
AAA
AAA
AAA
AAA
AA
AA
AA
AA
Circuit format
Port K data
PK1/MCLK
IP
Port K direction
(Every bit)
Data bus
RD (Port K)
Hi-Z
Servo input
TTL schmitt input can be selected
with the mask option.
1 pin
Port K
AAAA
AAAA
AAAA
AAAA
AA
AA
AA
Port K data
PK2
to
PK3
Input protection
circuit
When reset
Hi-Z
IP
Port K direction
(Every bit)
Data bus
RD (Port K)
2 pins
CS0
SI0
2 pins
SO0
AA
A
AAA
Schmitt input
Hi-Z
To SI0
IP
AA
AA
SO0 from SI0
SO0 output enable
Hi-Z
1 pin
Internal serial clock
from SI0
SCK0
AA
AA
AA
IP
SCK0 output enable
External serial clock to SI0
Schmitt input
1 pin
– 11 –
Hi-Z
CXP875P40
Pin
EXTAL
XTAL
Circuit format
AA
A
AA
AA
AA
AA
AA
When reset
• Shows the circuit
composition during
oscillation.
• Feedback resistor is
removed during stop.
IP
EXTAL
Oscillation
XTAL
2 pins
Pull-up resistor
Mask option
RST
1 pin
NMI
OP
AA
A
AAA
Schmitt input
L level
From power on reset circuit
(Mask option)
Schmitt input
IP
Interruption circuit
1 pin
– 12 –
Hi-Z
CXP875P40
Absolute Maximum Ratings
Item
Power supply voltage
(VSS = 0V)
Symbol
Ratings
Unit
VDD
–0.3 to +7.0
V
VPP
–0.3 to +13.0
AVSS to +7.0∗1
V
V
AVDD
AVSS
V
Remarks
PROM version only
Input voltage
VIN
–0.3 to +0.3
–0.3 to +7.0∗2
Output voltage
VOUT
–0.3 to +7.0∗2
V
Middle tension proof output voltage
VOUTP
–0.3 to +15.0
mA
High level output current
IOH
–5
mA
High level total output current
∑IOH
–50
mA
Total of entire output pins
IOL
15
mA
IOLC
20
mA
Other than large current output pins : per pin
Large current port pin ∗3 : per pin
Low level total output current
∑IOL
130
°C
Total of entire output pins
Operating temperature
Topr
–10 to +75
°C
Storage temperature
Tstg
–55 to +150
Allowable power dissipation
PD
Low level output current
V
600
380
PH pin
QFP package
mW
LQFP package
∗1 AVDD and VDD should be set to the same voltage.
∗2 VIN and VOUT should not exceed VDD + 0.3V
∗3 The large current operation transistors are the N-ch transistors of the PD and PH4 to PH7.
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
better take place under the recommended operating conditions. Exceeding those conditions may
adversely affect the reliability of the LSI.
– 13 –
CXP875P40
Recommended Operating Conditions
Item
Power supply voltage
Symbol
VDD
(VSS = 0V)
Min.
Max.
4.5
5.5
2.5
VPP = VDD
VPP
Analog power supply
High level input
voltage
V
Remarks
Guaranteed range during operation
V
Guaranteed data hold operation range during STOP
∗6
4.5
5.5
V
∗1
VIH
0.7VDD
VDD
V
∗2
VIHS
0.8VDD
VDD
V
VIHTS
2.2
VDD
V
AVDD
VIHEX
Low level input
voltage
5.5
Unit
VDD – 0.4 VDD + 0.3
V
CMOS schmitt input ∗3
TTL schmitt input ∗4
EXTAL pin ∗5
∗2
VIL
0
0.3VDD
V
VILS
0
0.2VDD
V
VILTS
0
0.8
V
CMOS schmitt input ∗3
TTL schmitt input ∗4
VILEX
–0.3
0.4
V
EXTAL pin ∗5
+75
–10
°C
Operating temperature Topr
∗1 AVDD and VDD should be set to the same voltage.
∗2 Normal input port (Each pin of PC, PD, PF and PH1).
∗3 Each pin of NMI, CS0, SI0, SCK0, RST, PE0/INT0, PE1/EC/INT2, PH0/SCK1, PH2/SI1, PH3/INT1/CS1,
PG and PK1/MCLK (when CMOS schmitt input is selected with mask option for PG, PK1/MCLK).
∗4 Each pin of PG and PK1/MCLK (when TTL schmitt input is selected with mask option).
∗5 Specified only during external clock input.
∗6 VPP and VDD should be set to same voltage.
– 14 –
CXP875P40
DC Characteristics
Item
High level
output voltage
Low level
output voltage
(Ta = –10 to +75°C, VSS = 0V)
Symbol
VOH
VOL
Pin
Condition
Min.
PA to PD, PE2 to PE7,
PH0, PH1, SO0, SCK0
PH4 to PH7
(VOL only)
RST∗1 (VOL only)
PI to PK
VDD = 4.5V, IOH = –0.5mA
4.0
V
VDD = 4.5V, IOH = –1.2mA
3.5
V
PD, PH4 to PH7
IIHE
Input current
IILE
EXTAL
IILR
RST∗2
I/O leakage
current
IIZ
PA to PG
PH0 to PH3,
CS0, SI0, SO0,
SCK0, NMI,
RST∗2
PI to PK∗3
Open drain output
leakage current
(N-ch Tr OFF in
state)
ILOH
PH4 to PH7
Current power
supply
Input capacity
Typ.
Max. Unit
VDD = 4.5V, IOL = 1.8mA
0.4
V
VDD = 4.5V, IOL = 3.6mA
0.6
V
VDD = 4.5V, IOL = 12.0mA
1.5
V
VDD = 5.5V, VIH = 5.5V
0.5
40
µA
VDD = 5.5V, VIL = 0.4V
–0.5
–40
µA
VDD = 5.5V, VIL = 0.4V
–1.5
–400
µA
VDD = 5.5V
VI = 0, 5.5V
±10
µA
VDD = 5.5V
VOH = 12V
50
µA
Operating mode
(1/2 dividing clock)
12.288MHz crystal
oscillation
(C1 = C2 = 12pF)
Entire output pins open
20
45
mA
IDDSL
SLEEP mode
5
17
mA
IDDST
STOP mode
30
µA
20
pF
IDD
VDD
CIN
Other than VDD,
VSS, AVDD, and
AVSS pins
Clock 1MHz
0V other than the
measured pins
10
∗1 RST pin specifies only when the power on reset circuit is selected with mask option.
∗2 RST pin specifies the input current when the pull-up resistance is selected, and specifies leakage current
when non-resistance is selected.
∗3 PK0 pin specifies only when the normal input circuit is selected with mask option.
– 15 –
CXP875P40
AC Characteristics
(1) Clock timing
Item
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, VSS = 0V)
Symbol
System clock frequency
fC
System clock input pulse
width
tXL,
tXH
tCR,
tCF
tEH,
tEL
tER,
tEF
System clock input rising
and falling times
Event count input clock
pulse width
Event count input clock
rising and falling times
Pin
Condition
Min.
Max.
Unit
12.288
MHz
XTAL
EXTAL
Fig. 1, Fig. 2
1
EXTAL
Fig. 1, Fig. 2
External clock drive
36
EXTAL
Fig. 1, Fig. 2
External clock drive
EC
Fig. 3
EC
Fig. 3
ns
200
tsys + 50∗
ns
ns
20
ms
∗ tsys indicates three values according to the contents of the clock control register (address : 00FEH) upper 2
bits (CPU clock selection).
tsys (ns) = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”)
Fig. 1. Clock timing
1/fc
VDD – 0.4V
EXTAL
0.4V
tXH
tCF
Fig. 2. Clock applying condition
AAAA
AAAA
AAAA
C1
tCR
AAAA
AAAA
AAAA
Crystal oscillation
Ceramic oscillation
EXTAL
tXL
External clock
EXTAL
XTAL
XTAL
74HCO4
C2
Fig. 3. Event count clock timing
0.8VDD
EC
0.2VDD
tEF
tEH
– 16 –
tEL
tER
CXP875P40
(2) Serial transfer
Item
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, VSS = 0V)
Symbol
Pin
Condition
Min.
Max.
Unit
CS ↓ → SCK delay
time
tDCSK
SCK0,
SCK1
Chip select transfer mode
(SCK = Output mode)
tsys + 200
ns
CS ↑ → SCK floating
delay time
tDCSKF
SCK0,
SCK1
Chip select transfer mode
(SCK = Output mode)
tsys + 200
ns
CS ↓ → SO delay time
tDCSO
SO0, SO1 Chip select transfer mode
tsys + 200
ns
CS ↑ → SO floating
delay time
tDCSOF
SO0, SO1 Chip select transfer mode
tsys + 200
ns
CS high level width
tWHCS
CS0, CS1 Chip select transfer mode
tKCY
SCK0,
SCK1
Input mode
SCK cycle time
SCK high and low
level widths
tKH
tKL
SCK0,
SCK1
Input mode
SI input setup time
(against SCK ↑)
tSIK
SI0, SI1
SI input hold time
(against SCK ↑)
tKSI
SI0, SI1
SCK ↓ → SO delay
time
tKSO
SO0, SO1
Note 1)
tsys + 200
2tsys + 200
ns
8000/fc
ns
tsys + 100
ns
Output mode
4000/fc – 50
ns
SCK input mode
–tsys + 100
ns
200
ns
2tsys + 100
ns
100
ns
Output mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
ns
2tsys + 200
ns
100
ns
tsys indicates three values according to the contents of the clock control register (address : 00FEH)
upper 2 bits (CPU clock selection).
tsys (ns) = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”)
Note 2) The marks CS, SCK, SI and SO respectivery mean pins of CS → CS0, CS1, SCK → SCK0, SCK1,
SI → SI0, SI1 and SO → SO0, SO1.
Note 3) The load of SCK output mode and SO output delay time is 50pF + 1TTL.
– 17 –
CXP875P40
Fig. 4. Serial transfer timing
tWHCS
CS0
CS1
0.8VDD
0.2VDD
tKCY
tDCSK
tKL
tDCSKF
tKH
0.8VDD
0.8VDD
SCK0
SCK1
0.2VDD
tKSI
tSIK
0.8VDD
Input
data
SI0
SI1
0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD
SO0
SO1
Output
data
0.2VDD
– 18 –
CXP875P40
(3) A/D converter characteristics
(Ta = –10 to +75°C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, VSS = AVSS = 0V)
Item
Symbol
Max.
Unit
Resolution
8
bits
Linearity error
±1
LSB
Zero transition
voltage
VZT∗1
Full scale
transition voltage
VFT∗2
Conversion time
tCONV
tSAMP
Sampling time
Pin
Condition
Ta = 25°C
VDD = AVDD = 5.0V
VSS = AVSS = 0V
Min.
Typ.
–10
30
70
mV
4930
4970
5010
mV
160/fC
µs
12/fC
µs
Reference input
voltage
VREF
AVREF
AVDD – 0.5
AVDD
V
Analog input
voltage
VIAN
AN0 to
AN7
0
AVREF
V
1.0
mA
10
µA
Operating mode
IREF
AVREF current
IREFS
AVREF
0.6
SLEEP mode
STOP mode
Fig. 5. Definitions of A/D converter terms
Digital conversion value
FFH
FEH
∗1 VZT :Indicates the value that digital conversion value
changes from 00 H to 01H and vice versa.
∗2 VFT :Indicates the value that digital conversion value
Linearity
error
changes from FE H to FFH and vice versa.
01H
00H
VFT
VZT
Analog input
– 19 –
CXP875P40
(4) Interruption, reset input
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, VSS = 0V)
Item
Symbol
Pin
Condition
Min.
Max.
Unit
External interruption high
and low level widths
tIH
tIL
INT0
INT1
INT2
NMI
1
µs
Reset input low level width
tRSL
RST
8/fc
µs
Fig. 6. Interruption input timing
tIH
INT0
INT1
INT2
NMI
(Falling edge)
tIL
0.8VDD
0.2VDD
Fig. 7. RST input timing
tRSL
RST
0.2VDD
(5) Power on reset
Power on reset∗
Item
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, VSS = 0V)
Symbol
Power supply rising
time
tR
Power supply cut-off
time
tOFF
Pin
Condition
Power on reset
Min.
Max.
Unit
0.05
50
ms
VDD
Repetitive power on reset
1
ms
∗ Specifies only when power on reset function is selected.
Fig. 8. Power on reset
4.5V
VDD
0.2V
0.2V
tOFF
tR
The power supply should rise smoothly.
– 20 –
CXP875P40
(6) Others
Item
RFDT input high and
low level widths
MCLK input high and
low level widths
DREF input high and
low level widths
DPG input high and
low level widths
DFG input high and
low level widths
CFG input high and
low level widths
RFG input high and
low level widths
EXI input high and
low level widths
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, VSS = 0V)
Symbol
tRDH
tRDL
tMCH
tMCL
tDRH
tDRL
tDPH
tDPL
tDFH
tDFL
tCFH
tCFL
tRFH
tRFL
tEIH
tEIL
Pin
Condition
Min.
Max.
Unit
RFDT
2.5tMCK∗
ns
MCLK
326/fc
ns
DREF
tsys + 200
ns
DPG
tsys + 200
ns
DFG
tsys + 200
ns
CFG
tsys + 200
ns
RFG0
RFG1
tsys + 200
ns
tsys + 200
ns
EXI0
EXI1
tsys = 2000/fc
∗ tMCK indicates three values according to the contents of the ATF control register (address : 01EEH) bits 5 and
4 (MCLK input control).
tMCK (ns) = tMCH or tMCL (bits 5 and 4 = “00”), 2tMCH or 2tMCL (bits 5 and 4 = “01”), 4tMCH or 4tMCL (bits 5 and 4
= “10”).
– 21 –
CXP875P40
Fig. 9. Other timing
tRDH
tRDL
tMCH
tMCL
tDRH
tDRL
tDPH
tDPL
tDFH
tDFL
tCFH
tCFL
tRFH
tRFL
tEIH
tEIL
RFDT
MCLK
DREF
DPG
DFG
CFG
RFG0
RFG1
EXI0
EXI1
– 22 –
CXP875P40
(7) Buffer amplifier function
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, VSS = 0V)
Item
Buffer amplifier input
voltage∗
(Peak to peak value)
Symbol
VAPP
Pin
Condition
Min.
Max.
Unit
RFDT
When inputting 400kHz
sine wave on Fig. 10
circuit.
2.0
VDD + 0.3
V
∗ When buffer amplifier input circuit format of RFDT pin is selected with option.
Fig. 10.
VAPP (Refer to Fig. 11.)
VDD
C
RFDT
C: 4700pF (±5%)
VSS
Note) VAPP waveform indicates the range like Fig. 11. When composed by circuits other than Fig. 10. (when
DC bias does not become VDD/2), it should not exceed VDD + 0.3 (V) and –0.3 (V) (VSS = 0V).
Fig. 11.
VAPP
VDD/2
– 23 –
CXP875P40
SUPPLEMENT
AAAA
AAAA
AAAA
Fig. 12. SPC700 series recommended oscillation circuit
EXTAL
Manufacturer
Model
XTAL
C2
C1
RIVER ELETEC
CO., LTD.
HC-49/U-03
Frequency
f (MHz)
C1, C2 (pF)
6.00
12
8.00
12
12.000
10
Mask option table
Item
Contents
Reset pin pull-up resistor
Non-existent
Existent
Power on reset circuit
Non-existent
Existent
CMOS Schmitt
TTL Schmitt
Buffer amplifier
Normal input
Input circuit format∗
∗ On PG0/EXI0 pin to PG7/RFG1 pin and PK1/MCLK pin, the input circuit format of CMOS schmitt or TTL
schmitt can be selected to every pin.
On PK0/RFDT pin, buffer amplifier or normal input circuit format can be selected.
– 24 –
CXP875P40
Unit: mm
100PIN QFP (PLASTIC)
+ 0.1
0.15 – 0.05
15.8 ± 0.4
+ 0.4
14.0 – 0.01
17.9 ± 0.4
23.9 ± 0.4
+ 0.4
20.0 – 0.1
A
0.65
+ 0.35
2.75 – 0.15
±0.12 M
0° to 15°
DETAIL A
0.8 ± 0.2
(16.3)
0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SOLDER PLATING
SONY CODE
QFP-100P-L01
LEAD TREATMENT
EIAJ CODE
∗QFP100-P-1420-A
LEAD MATERIAL
COPPER / 42 ALLOY
PACKAGE WEIGHT
1.4g
JEDEC CODE
100PIN LQFP (PLASTIC)
16.0 ± 0.2
∗
14.0 ± 0.1
75
51
76
(15.0)
50
0.5 ± 0.2
A
26 (0.22)
100
1
0.5 ± 0.08
+ 0.08
0.18 – 0.03
25
+ 0.2
1.5 – 0.1
+ 0.05
0.127 – 0.02
0.1
0.1 ± 0.1
0° to 10°
0.5 ± 0.2
Package Outline
DETAIL A
NOTE: Dimension “∗” does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY/PHENOL RESIN
SONY CODE
LQFP-100P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
∗QFP100-P-1414-A
LEAD MATERIAL
42 ALLOY
JEDEC CODE
PACKAGE WEIGHT
– 25 –