CXP80712B/80716B/80720B/80724B CMOS 8-bit Single Chip Microcomputer Description The CXP80712B/80716B/80720B/80724B is a CMOS 8-bit microcomputer which consists of A/D converter, serial interface, timer/counter, time base timer, high precision timing pattern generation circuit, PWM output, VISS/VASS circuit, 32kHz timer/counter, remote control receiving circuit, VSYNC separator and the measurement circuit which measures signals of capstan FG and drum FG/PG and other servo systems, as well as basic configurations like 8-bit CPU, ROM, RAM and I/O port. They are integrated into a single chip. Also CXP80712B/80716B/80720B/80724B provides sleep/stop function which enables to lower power consumption. 100 pin QFP (PIastic) 100 pin LQFP (PIastic) Structure Silicon gate CMOS IC Features • A wide instruction set (213 instructions) which cover various types of data — 16-bit arithmetic/multiplication and division/boolean bit operation instructions • Minimum instruction cycle 250ns at 16MHz operation 122µs at 32kHz operation • Incorporated ROM capacity 12K bytes (CXP80712B) 16K bytes (CXP80716B) 20K bytes (CXP80720B) 24K bytes (CXP80724B) • Incorporated RAM capacity 800 bytes • Peripheral functions — A/D converter 8 bits, 12 channels, successive approximation system (Conversion time of 20.0µs/16MHz) — Serial Interface Incorporated 8-bit and 8-stage FIFO, 1 channel (1 to 8 bytes auto transfer) 8-bit serial I/O, 1 channel — Timer 8-bit timer 8-bit timer/counter 19-bit time base timer 32kHz timer/counter — High precision timing pattern generator PPG for 19 pins, 32-stage programmable RTG for 5 pins, 2 channels — PWM/DA gate output 12 bits, 2 channels (Repetitive frequency of 62.5kHz/16MHz) — Servo input control Capstan FG, Drum FG/PG, CTL input — VSYNC separator — FRC capture unit Incorporated 26-bit and 8-stage FIFO — PWM output 14 bits, 1 channel — VISS/VASS circuit Pulse duty auto detection circuit — Remote control receiving circuit 8-bit pulse measurement counter, 6-stage FIFO • Interruption 21 factors, 15 vectors, multi-interruption possible • Standby mode SLEEP/STOP • Package 100-pin plastic QFP/LQFP • Piggyback/evaluation chip CXP87700 100-pin ceramic PQFP Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E95Z43A71 AVDD ADJ PWM0 DAA0 DAB0 PWM1 DAA1 DAB1 PWM DDO RMC CFG DFG DPG PBCTL EXI0 EXI1 12 BIT PWM GENERATOR CH1 12 BIT PWM GENERATOR CH0 14 BIT PWM GENERATOR VISS/VASS FIFO SERVO INPUT CONTROL REMOCON INPUT CTL DRUM CAPSTAN V SYNC SEPARATOR 8 BIT TIMER 1 TO SYNC0 SYNC1 8 BIT TIMER/COUNTER 0 EC FIFO SERIAL INTERFACE UNIT (CH1) SERIAL INTERFACE UNIT (CH0) 4 2 2 3 2 2 NMI NMI INT0 INT1 INT2 2 2 32kHz TIMER/COUNTER PRESCALER/ TIME BASE TIMER RAM 800 BYTES CH1 REALTIME PULSE GENERATOR CH0 VDD Vss CLOCK GENERATOR/ SYSTEM CONTROL 5 RAM FIFO ROM 12K/16K/20K/24K BYTES SPC700 CPU CORE AA 19 PROGRAMMABLE PATTERN GENERATOR FRC CAPTURE UNIT INTERRUPT CONTROLLER AVREF A/D CONVERTER AVss SI1 SO1 SCK1 CS0 SI0 SO0 SCK0 12 PPO0 to PPO18 AN0 to AN11 TEX TX EXTAL XTAL RST MP RTO3 to RTO7 PORT A PG0 to PG7 PH0 to PH7 8 8 8 PJ0 to PJ7 PI1 to PI7 PF4 to PF7 4 7 PF0 to PF3 PE2 to PE7 PE0 to PE1 4 6 2 8 PD0 to PD7 PC0 to PC7 8 PA0 to PA7 PB0 to PB7 8 8 PORT B PORT C PORT D PORT E PORT F PORT G PORT H PORT I –2– PORT J Block Diagram CXP80712B/80716B/80720B/80724B CXP80712B/80716B/80720B/80724B PI5/SCK1 PI4/INT1/NMI PI3/TO/DDO/ADJ PI2/PWM PI1/RMC TEX TX VDD VSS NC PA7/PPO7 PA6/PPO6 PA5/PPO5 PA4/PPO4 PA3/PPO3 PA2/PPO2 PA1/PPO1 PA0/PPO0 PB7/PPO15 PB6/PPO14 Pin Assignment 1 (Top View) 100 pin QFP package 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PB5/PPO13 1 80 PI6/SO1 PB4/PPO12 2 79 PI7/SI1 PB3/PPO11 3 78 PE0/INT0 PB2/PPO10 4 77 PE1/EC/INT2 PB1/PPO9 5 76 PE2/PWM0 PB0/PPO8 6 75 PE3/PWM1 PC7/RTO7 7 74 PE4/DAA0 PC6/RTO6 8 73 PE5/DAA1 PC5/RTO5 9 72 PE6/DAB0 PC4/RTO4 10 71 PE7/DAB1 PC3/RTO3 11 70 PG0/CFG PC2/PPO18 12 69 PG1/DFG PC1/PPO17 13 68 PG2/DPG PC0/PPO16 14 67 PG3/PBCTL PJ7 15 66 PG4/SYNC0 PJ6 16 65 PG5/SYNC1 PJ5 17 64 PG6/EXI0 PJ4 18 63 PG7/EXI1 PJ3 19 62 AN0 PJ2 20 61 AN1 PJ1 21 60 AN2 PJ0 22 59 AN3 PD7 23 58 PF0/AN4 PD6 24 57 PF1/AN5 PD5 25 56 PF2/AN6 PD4 26 55 PF3/AN7 PD3 27 54 AVDD PD2 28 53 AVREF PD1 29 52 AVSS PD0 30 51 PF4/AN8 Note) PF5/AN9 PF6/AN10 PF7/AN11 SCK0 SO0 SI0 CS0 EXTAL XTAL VSS RST MP PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1. NC (Pin 90) is always connected to VDD. 2. Vss (Pins 41 and 88) are both connected to GND. 3. MP (Pin 39) is always connected to GND. –3– CXP80712B/80716B/80720B/80724B PE0/INT0 PI7/SI1 PI6/SO1 PI5/SCK1 PI4/INT1/NMI PI3/TO/DDO/ADJ PI2/PWM PI1/RMC TEX TX VSS VDD NC PA7/PPO7 PA6/PPO6 PA5/PPO5 PA4/PPO4 PA3/PPO3 PA2/PPO2 PA1/PPO1 PA0/PPO0 PB7/PPO15 PB6/PPO14 PB5/PPO13 PB4/PPO12 Pin Assignment 2 (Top View) 100 pin LQFP package 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PB3/PPO11 1 75 PE1/EC/INT2 PB2/PPO10 2 74 PE2/PWM0 PB1/PPO9 3 73 PE3/PWM1 PB0/PPO8 4 72 PE4/DAA0 PC7/RTO7 5 71 PE5/DAA1 PC6/RTO6 6 70 PE6/DAB0 PC5/RTO5 7 69 PE7/DAB1 PC4/RTO4 8 68 PG0/CFG PC3/RTO3 9 67 PG1/DFG PC2/PPO18 10 66 PG2/DPG PC1/PPO17 11 65 PG3/PBCTL PC0/PPO16 12 64 PG4/SYNC0 PJ7 13 63 PG5/SYNC1 PJ6 14 62 PG6/EXI0 PJ5 15 61 PG7/EXI1 PJ4 16 60 AN0 PJ3 17 59 AN1 PJ2 18 58 AN2 PJ1 19 57 AN3 PJ0 20 56 PF0/AN4 PD7 21 55 PF1/AN5 PD6 22 54 PF2/AN6 PD5 23 53 PF3/AN7 PD4 24 52 AVDD PD3 25 51 AVREF Note) 1. NC (Pin 88) is always connected to VDD. 2. Vss (Pins 39 and 86) are both connected to GND. 3. MP (Pin 37) is always connected to GND. –4– AVSS PF4/AN8 PF5/AN9 PF6/AN10 PF7/AN11 SCK0 SO0 SI0 CS0 XTAL EXTAL VSS RST MP PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 PD0 PD1 PD2 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CXP80712B/80716B/80720B/80724B Pin Description Symbol I/O Description Output/ Real-time output (Port A) 8-bit output port. Data is gated with PPO contents by OR-gate and they are output. (8 pins) PB0/PPO8 to PB7/PPO15 Output/ Real-time output (Port B) 8-bit output port. Data is gated with PPO contents by OR-gate and they are output. (8 pins) PC0/PPO16 to PC2/PPO18 I/O/ Real-time output PC3/RTO3 to PC7/RTO7 I/O/ Real-time output PA0/PPO0 to PA7/PPO7 (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. Data is gated with PPO or RTO contents by OR-gate and they are output. (8 pins) Programmable pattern generator (PPG) output. Functions as high precision real-time pulse output port. (19 pins) Real-time pulse generator (RTG) output. Functions as high precision real-time pulse output port. (5 pins) (Port D) 8-bit I/O port. I/O can be set in a unit of 4 bits. Can 12mA sink current. (8 pins) PD0 to PD7 I/O PE0/INT0 Input/Input Input pin to request external interruption. Active when falling edge. PE1/EC/INT2 Input/Input/Input External event input pin for timer/counter. (Port E) 8-bit port. Lower 2 bits are for inputs; upper 6 bits are for outputs. (8 pins) Input pin to request external interruption. Active when falling edge. PE2/PWM0 Output/Output PE3/PWM1 Output/Output PE4/DAA0 Output/Output PE5/DAA1 Output/Output PE6/DAB0 Output/Output PE7/DAB1 Output/Output AN0 to AN3 Input Analog input pins to A/D converter. (12 pins) PF0/AN4 to PF3/AN7 Input/Input PF4/AN8 to PF7/AN11 Output/Input (Port F) Lower 4 bits are for inputs; upper 4 bits are for outputs. Lower 4 bits also serve as standby release input pin. (8 pins) SCK0 I/O Serial clock (CH0) I/O pin. SO0 Ouput Serial data (CH0) output pin. SI0 Input Serial data (CH0) input pin. CS0 Input Serial chip select (CH0) input pin. PWM output pins. (2 pins) DA gate pulse output pins. (4 pins) –5– CXP80712B/80716B/80720B/80724B Symbol I/O Description PG0/CFG Input/Input Capstan FG input pin. PG1/DFG Input/Input Drum FG input pin. PG2/DPG Input/Input PG3/PBCTL Input/Input PG4/SYNC0 Input/Input PG5/SYNC1 Input/Input PG6/EXI0 Input/Input PG7/EXI1 Input/Input Drum PG input pin. (Port G) 8-bit input port. (8 pins) Playback CTL pulse input pin. Composite sync signal input pin. (2 pins) External input pin to FRC capture unit. (2 pins) (Port H) 8-bit output port; N-ch open drain output of medium drive voltage (12V) and large current (12mA). (8 pins) PH0 to PH7 Output PI1/RMC I/O/Input Remote control receiving circuit input pin. PI2/PWM I/O/Output 14-bit PWM output pin. PI3/TO/ DDO/ADJ I/O/Output/ Output/Output PI4/INT1/ NMI I/O/Input/Input PI5/SCK1 I/O/I/O PI6/SO1 I/O/Output Serial data (CH1) output pin. PI7/SI1 I/O/Input Serial data (CH1) input pin. PJ0 to PJ7 I/O EXTAL Input XTAL Output TEX Input TX Output Connecting pin of crystal oscillator for 32kHz timer clock. When used as event counter, input to TEX pin and leave TX pin open. (Feedback resistor is not removed.) RST Input System reset pin of active Low level. MP Input Test mode input pin. Always connect to GND. Timer/counter, CTL duty detection, 32kHz oscillation adjustment output pin. Input pin to request external interruption and non maskable interruption. Active when falling edge. Serial clock (CH1) I/O pin. (Port J) 8-bit I/O port. Function as standby release input can be set in a unit of single bits. I/O can be set in a unit of single bits. Connecting pin of crystal oscillator for system clock. When supplying the external clock, input the external clock to EXTAL pin and input opposite phase clock to XTAL pin. Positive power supply pin of A/D converter. AVDD AVREF (Port I) 7-bit I/O port. I/O port can be set in a unit of single bits. (7 pins) Input Reference voltage input pin of A/D converter. AVss GND pin of A/D converter. VDD Positive power supply pin. NC NC pin. Connect this pin to VDD for normal operation. Vss GND pin. Connect both Vss pins to GND. –6– CXP80712B/80716B/80720B/80724B Input/Output Circuit Formats for Pins Pin When reset Circuit format Port A AA Port B PA0/PPO0 to PA7/PPO7 PB0/PPO8 to PB7/PPO15 AAAAA AAAAA PPO data Ports A and B data Data bus Hi-Z Output becomes active from high impedance by data writing to port register. RD (Ports A and B) 16 pins AA AA Port C PC0/PPO16 to PC2/PPO18 AAAA AAAA AAAA PPO, RTO data A Port C data PC3/RTO3 to PC7/RTO7 Input protection circuit Hi-Z IP Port C direction Data bus RD (Port C) 8 pins Port D PD0 to PD7 AA AA AA AAAA AAAA AAAA Large current 12mA Port D data IP Port D direction Data bus 8 pins RD (Port D) –7– Hi-Z CXP80712B/80716B/80720B/80724B Pin AAAA AA Port E When reset Circuit format Schmitt input PE0/INT0 PE1/EC/INT2 IP 2 pins Hi-Z Data bus AAA AAA AAAA AAA AAAA AAA AAAA AAAA AA AA AAA AA AAA AA AAA RD (Port E) Port E DA gate output PWM output MPX Hi-Z control PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 Port E data AA AA Hi-Z Port/DA output select Data bus 4 pins RD (Port E) Port E DA gate output Hi-Z control PE6/DAB0 PE7/DAB1 MPX Port E data AA AA High level Port/DA output select Data bus 2 pins RD (Port E) AN0 to AN3 A/D converter IP 4 pins Port F PF0/AN4 to PF3/AN7 AA AA AAAA AA AA AAAA Input multiplexer Input multiplexer IP A/D converter Hi-Z Data bus 4 pins Hi-Z RD (Port F) –8– CXP80712B/80716B/80720B/80724B Pin Circuit format When reset AAAA AA AAAA AA AA AAAA AA AA AAAA Port F PF4/AN8 to PF7/AN11 Port F data Data bus IP RD (Port F) 4 pins PG0/CFG PG1/DFG PG2/DPG PG3/PBCTL PG4/SYNC0 PG5/SYNC1 PG6/EXI0 PG7/EXI1 8 pins Port/AD select Input multiplexer Port G Schmitt input Servo input IP Data bus RD (Port G) AAAA AAAA AAAA AAAAAA AAAA AA AAAA AA AAAA Port H data Data bus 8 pins Hi-Z Note) For PG4/SYNC0 and PG5/SYNC1, CMOS schmitt input or TTL schmitt input can be selected with the mask option. Port H PH0 to PH7 Hi-Z A/D converter AA AA Medium drive voltage 12V Hi-Z Large current 12mA RD (Port H) Port I Port I function select PI2/PWM PI3/TO/ DDO/ADJ PI2: 14-bit PWM PI3: Timer/counter, CTL duty detection circuit, 32kHz timer MPX Port I data Port I direction Data bus 2 pins RD (Port I) –9– AA AA AA AA IP Hi-Z CXP80712B/80716B/80720B/80724B PIn AAAA AAAA AAAA Circuit format Port I When reset AA AA AA Port I data PI1/RMC PI4/INT1/NMI PI7/SI1 Port I direction IP Data bus RD (Port I) 3 pins PI1: Remote control circuit PI4: Interruption circuit PI7: Serial CH1 Hi-Z Schmitt input AAAA AAAAAA AA AA AAAA AA AA AA AAAA AA AA AA AAAA AA AA AA AAAA AAAA AA AAAA AA AAAA AA AA AA AA AAA AA AA Port I Port I function select PI5/SCK1 PI6/SO1 Serial CH1 MPX Port I data Port I direction MPX IP Note) PI5 is schmitt input PI6 is inverter input Data bus 2 pins Hi-Z RD (Port I) Serial CH1 Port J Port J data PJ0 to PJ7 Port J direction Data bus 8 pins CS0 SI0 2 pins SO0 RD (Port J) Edge detection Standby release Schmitt input Hi-Z Serial CH0 IP From Serial CH0 1 pin Hi-Z IP SO0 output enable – 10 – Hi-Z CXP80712B/80716B/80720B/80724B PIn Circuit format Internal serial clock from serial CH0 SCK0 SCK0 output enable Schmitt input 1 pin 2 pins AA AA AA AA AA AA AA A AA A AA AA AA AA AA EXTAL IP 2 pins TEX IP TX • Feedback resistor is removed and XTAL becomes High level during stop. Oscillation • Shows the circuit composition during oscillation. • Feedback resistor is removed during 32kHz oscillation circuit stop by software. At this time TEX pin outputs Low level and TX pin outputs High level. Oscillation Schmitt input OP IP 1 pin • Shows the circuit composition during oscillation. Pull-up resistor Mask option RST Hi-Z XTAL 32kHz timer counter TEX TX AA AA AA AA IP External serial clock to serial CH0 EXTAL XTAL When reset – 11 – Low level CXP80712B/80716B/80720B/80724B Absolute Maximum Ratings Item (Vss = 0V) Symbol Rating Unit –0.3 to +7.0 AVss to +7.0∗1 V V VIN –0.3 to +0.3 –0.3 to +7.0∗1 Output voltage VOUT –0.3 to +7.0∗1 V Medium drive output voltage VOUTP –0.3 to +15.0 V High level output current IOH –5 mA High level total output current ∑IOH –50 mA IOL 15 mA IOLC 20 mA Other than large current output port (value per pin) Large current port∗2 (value per pin) Low level total output current ∑IOL 130 mA Total of output pins Operating temperature Topr –20 to +75 °C Storage temperature Tstg –55 to +150 °C Allowable power dissipation PD VDD Supply voltage AVDD AVSS Input voltage Low level output current V V 600 380 Remarks mW Port H (PH) Total of output pins QFP package type LQFP package type ∗1 AVDD, VIN and VOUT must not exceed VDD + 0.3V. ∗2 The large current output ports are Port D (PD) and Port H (PH). Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should better take place under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI. – 12 – CXP80712B/80716B/80720B/80724B Recommended Operating Conditions Item Supply voltage Analog power supply HIgh level input voltage Symbol (Vss = 0V) Min. Max. Unit 4.5 5.5 V Guaranteed operation range for 1/2, 1/4 frequency dividing clock 3.5 5.5 V Guaranteed operation range for 1/16 frequency dividing clock or during SLEEP mode. 2.7 5.5 V Guaranteed operation range by TEX clock 2.5 5.5 V 4.5 5.5 V Guaranteed data hold operation range during STOP ∗1 VIH 0.7VDD VDD V ∗2 VIHS 0.8VDD VDD V VIHTS 2.2 VDD V VDD AVDD VIHEX VDD – 0.4 VDD + 0.3 V Remarks CMOS schmitt input∗3 TTL schmitt input∗4 EXTAL pin∗5 TEX pin∗6 ∗2 VIL 0 0.3VDD V VILS 0 0.2VDD V VILTS 0 0.8 V CMOS schmitt input∗3 TTL schmitt input∗4 VILEX –0.3 0.4 V EXTAL pin∗5 TEX pin∗6 Operating temperature Topr –20 +75 °C Low level input voltage ∗1 AVDD and VDD should be set to the same voltage. ∗2 Normal input port (each pin of PC, PD, PE0, PE1, PF0 to PF3, PG, PI and PJ), MP pin. ∗3 Each pin of CS0, SI0, SCK0, RST, PE0/INT0, PE1/EC/INT2, PG (For PG4 and PG5, when CMOS schmitt input is selected with mask option), PI1/RMC, PI4/INT1/NMI, PI5/SCK1 and PI7/SI1. ∗4 Each pin of PG4 and PG5 (When TTL schmitt input is selected with mask option) ∗5 Specifies only during external clock input. ∗6 Specifies only during event count clock input. – 13 – CXP80712B/80716B/80720B/80724B Electrical Characteristics DC Characteristics Item High level output voltage Low level output voltage (Ta = –20 to +75°C, Vss = 0V) Pins Symbol VOH VOL PA to PD, PE2 to PE7, PF4 to PF7, PH (VOL only) PI1 to PI7 PJ, SO0, SCK0 PD, PH IIHE Conditions Min. VDD = 4.5V, IOH = –0.5mA 4.0 V VDD = 4.5V, IOH = –1.2mA 3.5 V Typ. Max. Unit VDD = 4.5V, IOL = 1.8mA 0.4 V VDD = 4.5V, IOL = 3.6mA 0.6 V VDD = 4.5V, IOL = 12.0mA 1.5 V VDD = 5.5V, VIH = 5.5V 0.5 40 µA VDD = 5.5V, VIL = 0.4V –0.5 –40 µA VDD = 5.5V, VIH = 5.5V 0.1 10 µA –10 µA IILR VDD = 5.5V, VIL = 0.4V –0.1 RST∗1 –1.5 –400 µA I/O leakage current IIZ PA to PG, PI, PJ, MP AN0 to AN3, CS0, SI0, SO0 SCK0, RST∗1 VDD = 5.5V, VI = 0, 5.5V ±10 µA Open drain output leakage current (N-CH Tr off state) ILOH PH VDD = 5.5V VOH = 12V 50 µA IILE Input current IIHT IILT Supply current∗2 Input capacity EXTAL TEX IDD1 16MHz crystal oscillation (C1 = C2 = 15pF), VDD = 5.5V 20 45 mA IDDS1 16MHz crystal oscillation (C1 = C2 = 15pF), VDD = 5.5V, SLEEP mode 1.1 8 mA 32kHz crystal oscillation (C1 = C2 = 47pF), VDD = 3.3V 35 100 µA IDDS2 32kHz crystal oscillation (C1 = C2 = 47pF), VDD = 3.3V, SLEEP mode 7 30 µA IDDS3 VDD = 5.5V, STOP mode (termination of 32kHz and 16MHz crystal oscillation) 10 µA 20 pF IDD2 CIN VDD PC, PD, PE0 to 1, PF0 to 3, PG, PI, PJ, AN, Clock 1MHz SCK0, SI0, 0V other than the measured pins CS0, EXTAL, XTAL, TEX, TX, RST, MP 10 ∗1 RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current when no resistance is selected. ∗2 When entire output pins are open. ∗3 When setting upper 2 bits (CPU clock selection) of clock control register (CLC: 00FEH) to "00" and operating in high speed mode (1/2 frequency dividing clock). – 14 – CXP80712B/80716B/80720B/80724B AC Characteristics (1) Clock timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Item Symbol System clock frequency fC System clock input pulse width Event count clock input rise and fall times tXL, tXH tCR, tCF tEH, tEL tER, tEF System clock frequency fC Event count clock input pulse width tTL, tTH tTR, tTF System clock input rise and fall times Event count clock input pulse width Event count clock input rise and fall times Pins Conditions Typ. Min. XTAL EXTAL Fig. 1, Fig. 2 1 XTAL EXTAL Fig. 1, Fig. 2 (External clock drive) 28 XTAL EXTAL Fig. 1, Fig. 2 (External clock drive) EC Fig. 3 EC Fig. 3 TEX TX Fig. 2 VDD = 2.7 to 5.5V (32kHz clock applied condition) TEX Fig. 3 TEX Fig. 3 Max. Unit 16 MHz ns 200 4tsys∗1 ns ns 20 32.768 ns kHz 10 µs 20 ms ∗1 tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Fig. 1. Clock timing 1/fc VDD – 0.4V EXTAL 0.4V tCF tXH tXL tCR AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA Fig. 2. Clock applied condition Crystal oscillation Ceramic oscillation EXTAL C1 32kHz clock applied condition crystal oscillation External clock EXTAL XTAL C2 TEX XTAL TX C1 74HC04 C2 Fig. 3. Event count clock timing 0.8VDD TEX EC 0.2VDD tEH tTH tEF tEL tER tTF tTL tTR – 15 – CXP80712B/80716B/80720B/80724B (2) Serial transfer (CH0) Item (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Symbol Pin Condition Min. Max. Unit CS0 ↓ → SCK0 delay time tDCSK SCK0 Chip select transfer mode (SCK0 = output mode) tsys + 200 ns CS0 ↓ → SCK0 float delay time tDCSKF SCK0 Chip select transfer mode (SCK0 = output mode) tsys + 200 ns CS0 ↓ → SO0 delay time tDCSO SO0 Chip select transfer mode tsys + 200 ns CS0 ↓ → SO0 float delay time tDCSOF SO0 Chip select transfer mode tsys + 200 ns CS0 High level width tWHCS CS0 Chip select transfer mode tsys + 200 ns SCK0 cycle time Input mode SCK0 2tsys + 200 ns tKCY 16000/fc ns SCK0 High and Low level widths tKH tKL tsys + 100 ns SCK0 8000/fc – 50 ns SI0 input setup time (for SCK0 ↑) SCK0 input mode 100 ns tSIK SI0 SCK0 output mode 200 ns SI0 input hold time (for SCK0 ↑) SI0 tsys + 200 ns tKSI 100 ns SCK0 ↓ → SO0 delay time tKSO SO0 Output mode Input mode Output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode tsys + 200 ns 100 ns Note 1) tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) The load of SCK0 output mode and SO0 output delay time is 50pF + 1TTL. – 16 – CXP80712B/80716B/80720B/80724B Fig. 4. Serial transfer timing (CH0) tWHCS CS0 0.8VDD 0.2VDD tKCY tDCSK tKL tDCSKF tKH 0.8VDD 0.8VDD SCK0 0.2VDD tSIK tKSI 0.8VDD Input data SI0 0.2VDD tDCSO tKSO tDCSOF 0.8VDD SO0 Output data 0.2VDD – 17 – CXP80712B/80716B/80720B/80724B Serial transfer (CH1) Item (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Symbol Pins Conditions Input mode SCK1 cycle time tKCY SCK1 SCK1 High and Low level widths tKH tKL SCK1 SI1 input setup time (for SCK1 ↑) tSIK SI1 SI1 input hold time (for SCK1 ↑) tKSI SI1 SCK1 ↓ → SO1 delay time tKSO SO1 Min. ns 16000/fc ns 400 ns 8000/fc – 50 ns SCK1 input mode 100 ns SCK1 output mode 200 ns SCK1 input mode 200 ns SCK1 output mode 100 ns Output mode Input mode Output mode SCK1 input mode 200 ns SCK1 output mode 100 ns Fig. 5. Serial transfer timing (CH1) tKCY tKL tKH SCK1 0.8VDD 0.2VDD tSIK tKSI 0.8VDD Input data 0.2VDD tKSO 0.8VDD SO1 Unit 1000 Note) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL. SI1 Max. Output data 0.2VDD – 18 – CXP80712B/80716B/80720B/80724B (3) A/D converter characteristics (Ta = –20 to +75°C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V) Item Symbol Pins Conditions Min. Typ. Resolution Ta = 25°C VDD = AVDD = AVREF = 5.0V VSS = AVSS = 0V Linearity error Absolute error Sampling time Reference input voltage VREF Analog input voltage VIAN IREFS 8 Bits ±1 LSB ±2 LSB µs µs AVREF AVDD – 0.5 AVDD V AN0 to AN11 0 AVREF V 1.0 mA 10 µA IREF AVREF current Unit 160/fADC∗1 12/fADC∗1 tCONV tSAMP Conversion time Max. 0.6 Operating mode AVREF SLEEP mode STOP mode 32kHz operating mode Fig. 6. Definitions of A/D converter terms ∗1 fADC indicates the below values due to the contents of bit 0 (ADCCK) of the ADC operation clock selection (MSC: 01FFH), bits 7 (PCK1) and 6 (PCK0) of the clock control register. Digital conversion value FFH FEH ADCCK 0 (φ/2 selection) 1 (φ selection) 00 (φ = fEX/2) fADC = fC/2 fADC = fC 01 (φ = fEX/4) fADC = fC/4 fADC = fC/2 11 (φ = fEX/16) fADC = fC/16 fADC = fC/8 PCK1, PCK0 Linearity error 01H 00H VFT VZT Analog input – 19 – CXP80712B/80716B/80720B/80724B (4) Interruption, reset input Item (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Symbol Pins Conditions External interruption High and Low level widths tIH tIL INT0 INT1 INT2 NMI PJ0 to PJ7 Reset input Low level width tRSL Min. Max. Unit 1 µs RST 32/fc µs tIH tIL Fig. 7. Interruption input timing INT0 INT1 INT2 NMI PJ0 to PJ7 (During standby release input) (Falling edge) 0.8VDD 0.2VDD Fig. 8. Reset input timing tRSL RST 0.2VDD (5) Others (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Item Symbol tCFH tCFL tDFH DFG input High and Low level widths tDFL DPG minimum pulse width tDPW CFG input High and Low level widths DPG minimum removal time trem tCTH tCTL tEIH EXI input High and Low level widths tEIL PBCTL input High and Low level widths Pins Conditions Min. Max. Unit CFG tFRC × 24 + 200 ns DFG tFRC × 8 + 200 ns DPG 50 ns DPG 50 ns PBCTL tsys = 2000/fc tFRC × 8 + 200 + tsys ns EXI0 EXI1 tsys = 2000/fc tFRC × 8 + 200 + tsys ns Note) tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") tFRC [ns] = 1000/fc – 20 – CXP80712B/80716B/80720B/80724B Fig. 9. Other timings tCFH tCFL 0.8VDD CFG 0.2VDD tDFH tDFL 0.8VDD DFG 0.2VDD trem tDPW trem 0.8VDD DPG tCTH tCTL 0.8VDD PBCTL 0.2VDD tEIH EXI0 EXI1 tEIL 0.8VDD 0.2VDD – 21 – CXP80712B/80716B/80720B/80724B Appendix Fig. 10. Recommended oscillation circuit AAAAA AAAAA AAAAA (i) EXTAL (ii) TEX XTAL C2 Manufacturer Model TX Rd Rd C1 AAAA AAAA C1 fc (MHz) C2 C1 (pF) C2 (pF) 10 10 Rd (Ω) Circuit example 0 (i) 0 (i) 470k (ii) 8.00 RIVER ELETEC CO., LTD. HC-49/U03 10.00 12.00 5 5 8.00 16 12 10.00 16 12 12.00 12 12 16.00 12 12 32.768kHz 30 18 16.00 KINSEKI LTD. HC-49/U (-S) P3 Mask option table Item Reset pin pull-up resistor Input circuit format∗1 Content Non-existent Existent C-MOS schmitt TTL schmitt ∗1 The input circuit format can be selected for PG4/SYNC0 pin and PG5/SYNC1, respectively. – 22 – CXP80712B/80716B/80720B/80724B Characteristics Curve IDD vs. VDD IDD vs. fC (fc = 16MHz, Ta = 25°C, Typical) (VDD = 5V, Ta = 25°C, Typical) 1/2 dividing mode 1/4 dividing mode 20.0 1/16 dividing mode 5.0 SLEEP mode 1.0 0.5 32kHz mode (instruction) 1/2 dividing mode 20 IDD – Supply current [mA] IDD – Supply current [mA] 10.0 15 1/4 dividing mode 10 32kHz SLEEP mode 0.1 (100µA) 0.05 (50µA) 5 1/16 dividing mode 0.01 (10µA) SLEEP mode 2 3 4 5 6 7 0 VDD – Supply voltage [V] – 23 – 5 10 fc – System clock [MHz] 16 CXP80712B/80716B/80720B/80724B Unit: mm 100PIN QFP (PLASTIC) + 0.4 14.0 – 0.01 17.9 ± 0.4 15.8 ± 0.4 + 0.1 0.15 – 0.05 23.9 ± 0.4 + 0.4 20.0 – 0.1 A 0.65 + 0.35 2.75 – 0.15 ±0.12 M 0° to 15° DETAIL A 0.8 ± 0.2 (16.3) 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING SONY CODE QFP-100P-L01 LEAD TREATMENT EIAJ CODE ∗QFP100-P-1420-A LEAD MATERIAL COPPER / 42 ALLOY PACKAGE WEIGHT 1.4g JEDEC CODE 100PIN LQFP (PLASTIC) 16.0 ± 0.2 ∗ 14.0 ± 0.1 75 51 76 (15.0) 50 0.5 ± 0.2 A 26 (0.22) 100 1 0.5 ± 0.08 + 0.08 0.18 – 0.03 25 + 0.2 1.5 – 0.1 + 0.05 0.127 – 0.02 0.1 0.1 ± 0.1 0° to 10° 0.5 ± 0.2 Package Outline DETAIL A NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY/PHENOL RESIN SONY CODE LQFP-100P-L01 LEAD TREATMENT SOLDER PLATING EIAJ CODE ∗QFP100-P-1414-A LEAD MATERIAL 42 ALLOY JEDEC CODE PACKAGE WEIGHT – 24 –