CXP922P032
CMOS 16-bit Single Chip Microcomputer
For the availability of this product, please contact the sales office.
Description
The CXP922P032 is a CMOS 16-bit microcomputer
integrating on a single chip an A/D converter, serial
interface, timer, remote control receive circuit, PWM
output circuit, and as well as basic configurations like a
16-bit CPU, PROM, RAM, and I/O port.
This LSI also provides the sleep/stop functions that
enable lower power consumption.
The CXP922P032 is the PROM-incorporated
version of the CXP922032 with built-in mask ROM.
This provides the additional feature of being able to
write directly into the program. Thus, it is most
suitable for evaluation use during system
development and for small-quantity production.
100 pin QFP (Plastic)
Features
• An efficient instruction set as a controller
— Direct addressing, numerous abbreviated forms, multiplication and division instructions
• Instruction sets for C language and RTOS
— Highly quadratic instruction system, general-purpose register of eight 16-bit × 16-bank configuration
• Minimum instruction cycle
100ns/20MHz operation (3.0 to 5.5V)
167ns/12MHz operation (2.7 to 5.5V)
• Incorporated PROM capacity 128K bytes
• Incorporated RAM capacity 7680 bytes
• Peripheral functions
— A/D converter
8-bit 8 analog input, successive approximation system
(Conversion time: 12.4µs at 20MHz)
— Serial interface
Asynchronous serial interface (Simple UART)
128-byte buffer RAM,3 channels
— Timers
8-bit timer/counter, 2 channels (with timing output)
16-bit capture timer/counter (with timing output)
16-bit timer, 4 channels
— Remote control receive circuit
8-bit pulse measurement counter, 8-stage FIFO
— PWM output circuit
14-bit, 1 channel
• Interruption
24 factors, 24 vectors, multi-interruption and priority selection possible
• Standby mode
Sleep/stop
• Package
100-pin plastic QFP
• Piggy/evaluation chip
CXP922000
• Mask ROM
CXP922032
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E99937-PS
AVSS
CINT
EC1
TO1
TO0
CS0
SI0
SO0
SCK0
CS1
SI1
SO1
SCK1
CS2
SI2
SO2
SCK2
EC0
RMC
BUFFER
RAM
BUFFER
RAM
SERIAL
INTERFACE
UNIT (CH1)
SERIAL
INTERFACE
UNIT (CH2)
16-BIT CAPTURE
TIMER/COUNTER (CH4)
4CH 16-BIT TIMER
8-BIT TIMER (CH1)
8-BIT TIMER/COUNTER (CH0)
BUFFER
RAM
FIFO
SERIAL
INTERFACE
UNIT (CH0)
REMOCON
14-BIT PWM GENERATOR
PWM
A/D CONVERTER
AVREF
UART
8
AVDD
RxD
TxD
AN0 to AN7
2
NMI
2
INT0 to INT4
4
INTERRUPT CONTROLLER
KS0 to KS6
7
PRESCALER/
TIME-BASE TIMER
PROM
128K BYTES
SPC950
CPU CORE
VPP
VSS
VDD
RST
XTAL
EXTAL
RAM
7680 BYTES
CLOCK GENERATOR/
SYSTEM CONTROLLER
PB0 to PB7
8
8
8
PF0 to PF5
PF6, PF7
PG0 to PG7
PH0 to PH7
PI0 to PI7
6
2
8
8
8
7
PJ0 to PJ6
PE0 to PE7
8
PD0 to PD7
PC0 to PC7
PA0 to PA7
8
PORT F
PORT G
–2–
PORT H
5
PORT A
PORT B
PORT C
PORT D
PORT E
PORT I
PORT J
Block Diagram
CXP922P032
CXP922P032
PJ0/KS0
PJ1/KS1
PJ2/KS2
PJ3/KS3
PJ4/KS4
PJ5/KS5
PJ6/KS6
VPP
VDD
VSS
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
Pin Assignment (Top View) 100-pin QFP package
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
PB2
1
80
PI7/RMC
PB3
2
79
PI6/CINT
PB4
3
78
PI5/EC1
PB5
4
77
PI4/EC0
PB6
5
76
PI3
PB7
6
75
PI2
PC0
7
74
PI1/RxD
PC1
8
73
PI0/TxD
PC2
9
72
PH7/SCK2
PC3
10
71
PH6/SO2
PC4
11
70
PH5/SI2
PC5
12
69
PH4/CS2
PC6
13
68
PH3/SCK1
PC7
14
67
PH2/SO1
VSS
15
66
PH1/SI1
PD0
16
65
PH0/CS1
PD1
17
64
VSS
PD2
18
63
SCK0
PD3
19
62
SO0
PD4
20
61
SI0
PD5
21
60
CS0
PD6
22
59
PG7
PD7
23
58
PG6
PE0
24
57
PG5
PE1
25
56
PG4
PE2
26
55
AVDD
PE3
27
54
AVREF
PE4
28
53
AVSS
PE5
29
52
PG3/AN7
PE6
30
51
PG2/AN6
PG1/AN5
PG0/AN4
AN3
AN2
AN1
VDD
AN0
EXTAL
VSS
XTAL
RST
PF6/TO0
PF7/TO1/PWM
PF5/NMI
PF4/INT4
PF3/INT3
PF2/INT2
PF1/INT1
PE7
PF0/INT0
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Notes) 1. Do not make any connections to VPP (Pin 88).
2. VSS (Pins 15, 41, 64 and 90) must be connected to GND.
3. VDD (Pins 44 and 89) must be connected to VDD.
–3–
CXP922P032
Pin Functions
Symbol
Functions
I/O
I/O
(Port A)
8-bit I/O port.
I/O can be specified in 1-bit units.
Pull-up resistor is present or not through program in 4-bit units.
(8 pins)
I/O
(Port B)
8-bit I/O port.
I/O can be specified in 1-bit units.
Pull-up resistor is present or not through program in 4-bit units.
(8 pins)
I/O
(Port C)
8-bit I/O port.
I/O can be specified in 1-bit units.
Pull-up resistor is present or not through program in 4-bit units.
(8 pins)
I/O
(Port D)
8-bit I/O port.
I/O can be specified in 1-bit units.
Pull-up resistor is present or not through program in 4-bit units.
Can drive 12mA sink current (VDD = 4.5 to 5.5V).
(8 pins)
PE0 to PE7
I/O
(Port E)
8-bit I/O port.
I/O can be specified in 1-bit units.
Pull-up resistor is present or not through program in 4-bit units.
Can drive 12mA sink current (VDD = 4.5 to 5.5V).
(8 pins)
PF0/INT0
to PF4/INT4
Input / Input
PA0 to PA7
PB0 to PB7
PC0 to PC7
PD0 to PD7
External interrupt inputs.
(4 pins)
PF7/TO1/
PWM
(Port F)
8-bit port.
Input / Input
Lower 6 bits are for input;
Output / Output upper 2 bits are for output.
Output / Output / (6 pins)
Output
AN0 to AN3
Input
PG0/AN4
to PG3/AN7
I/O / Input
PG4 to PG7
I/O
CS0
Input
Serial chip select (CH0) input.
SI0
Input
Serial data (CH0) input.
SO0
Output
Serial data (CH0) output.
SCK0
I/O
Serial clock (CH0) I/O.
PF5/NMI
PF6/TO0
Non-maskable interrupt input.
8-bit timer/counter output.
16-bit capture timer/
counter output.
14-bit PWM output.
Analog input for A/D converter.
(4 pins)
(Port G)
8-bit I/O port.
I/O can be specified in 1-bit units.
Pull-up resistor is present or not through
program in 4-bit units.
(8 pins)
–4–
Analog input for A/D
converter.
(4 pins)
CXP922P032
Symbol
I/O
Functions
PH0/CS1
I/O / Input
PH1/SI1
I/O / Input
PH2/SO1
I/O / Output
PH3/SCK1
I/O / I/O
PH4/CS2
I/O / Input
PH5/SI2
I/O / Input
PH6/SO2
I/O / Output
PH7/SCK2
I/O / I/O
Serial clock (CH2) I/O.
PI0/TxD
I/O / Output
UART transmission data output.
PI1/RxD
I/O / Input
PI2 to PI3
I/O
PI4/EC0
I/O / Input
PI5/EC1
I/O / Input
PI6/CINT
I/O / Input
PI7/RMC
I/O / Input
Serial chip select (CH1) input.
(Port H)
8-bit I/O port.
I/O can be specified in
1-bit units.
Pull-up resistor is present
or not through
program in 4-bit units.
(8 pins)
(Port I)
8-bit I/O port.
I/O can be specified in
1-bit units.
Pull-up resistor is present
or not through
program in 4-bit units.
(8 pins)
Serial data (CH1) input.
Serial data (CH1) output.
Serial clock (CH1) I/O.
Serial chip select (CH2) input.
Serial data (CH2) input.
Serial data (CH2) output.
UART reception data input.
External event input for 8-bit timer/counter.
External event input for 16-bit capture timer/
counter.
External capture input for 16-bit capture timer/
counter.
Remote control receive circuit input.
(Port J)
7-bit I/O port.
I/O can be specified in
1-bit units.
Standby release input function can be specified
Pull-up resistor is present in 1-bit units.
or not through
(7 pins)
program in lower 4-bit
units and upper 3-bit units.
(7 pins)
PJ0/KS0
to PJ6/KS6
I/O / Input
EXTAL
Input
Connects a crystal for system clock oscillation.
(When the clock is supplied externally, input it to EXTAL and input an
opposite phase clock to XTAL.)
Input
System reset. Active at "L" level.
XTAL
RST
AVDD
AVREF
Positive power supply for A/D converter.
Input
Reference voltage input for A/D converter.
AVSS
GND for A/D converter.
VDD
Positive power supply.
(Connect both VDD pins to positive power supply.)
VSS
GND
(Connect all four VSS pins to GND.)
VPP
Positive power supply pin used for writing inorporated PROM.
(Do not make any cunnection to NC.)
–5–
CXP922P032
I/O Circuit Format for Pins
Pin
Circuit format
After a reset
∗
PUL0 register
"0" after a reset
PA register
Undefined after a reset
PA0 to PA7
Hi-Z
PAD register
IP
Input protection
circuit
"0" after a reset
Internal data bus
RD
∗ Pull-up transistor
approximately 100kΩ (VDD = 4.5 to 5.5V)
approximately 150kΩ (VDD = 3.0 to 3.6V)
∗
PUL0 register
"0" after a reset
PB register
Undefined after a reset
PB0 to PB7
Hi-Z
PBD register
IP
"0" after a reset
Internal data bus
RD
∗ Pull-up transistor
approximately 100kΩ (VDD = 4.5 to 5.5V)
approximately 150kΩ (VDD = 3.0 to 3.6V)
∗
PUL0 register
"0" after a reset
PC register
Undefined after a reset
PC0 to PC7
Hi-Z
PCD register
IP
"0" after a reset
Internal data bus
RD
∗ Pull-up transistor
approximately 100kΩ (VDD = 4.5 to 5.5V)
approximately 150kΩ (VDD = 3.0 to 3.6V)
–6–
CXP922P032
Pin
Circuit format
After a reset
∗1
PUL0 register
"0" after a reset
PD register
Undefined after a reset
PD0 to PD7
∗2
PDD register
IP
Hi-Z
"0" after a reset
Internal data bus
∗1 Pull-up transistor
approximately 100kΩ (VDD = 4.5 to 5.5V)
approximately 150kΩ (VDD = 3.0 to 3.6V)
∗2 Large current drive
12mA (VDD = 4.5 to 5.5V)
4.5mA (VDD = 3.0 to 3.6V)
RD
∗1
PUL1 register
"0" after a reset
PE register
Undefined after a reset
PE0 to PE7
∗2
PED register
IP
Hi-Z
"0" after a reset
Internal data bus
∗1 Pull-up transistor
approximately 100kΩ (VDD = 4.5 to 5.5V)
approximately 150kΩ (VDD = 3.0 to 3.6V)
∗2 Large current drive
12mA (VDD = 4.5 to 5.5V)
4.5mA (VDD = 3.0 to 3.6V)
RD
PF0/INT0
to PF4/INT4
PF5/NMI
INT0, INT1, INT2,
INT3, INT4, NMI
IP
CMOS Schmitt input
Internal data bus
RD
–7–
Hi-Z
CXP922P032
Circuit format
Pin
After a reset
TO0
PFSL register
"0" after a reset
PF6/TO0
"H" level
PF register
"1" after a reset
Internal data bus
RD
RD
Internal data bus
Internal reset signal
PF register
PF7/TO1/
PWM
00
"1" after a reset
TO1
01
PWM
1x
MPX
∗
PFSL register (Bit 7)
"H" level
("H" level at ON
resistance of
pull-up transistor
during a reset.)
PFSL register (Bit 6)
∗ Pull-up transistor
"00" after a reset
approximately 150kΩ (VDD = 4.5 to 5.5V)
approximately 200kΩ (VDD = 3.0 to 3.6V)
TO1 output enable
AN0 to AN3
A/D converter
IP
Input multiplexer
–8–
Hi-Z
CXP922P032
Pin
Circuit format
After a reset
∗
PUL1 register
"0" after a reset
PG register
Undefined after a reset
PGD register
"0" after a reset
PG0/AN4
to PG3/AN7
IP
PGSL register
Hi-Z
"0" after a reset
Internal data bus
RD
A/D converter
Input multiplexer
∗ Pull-up transistor
approximately 100kΩ (VDD = 4.5 to 5.5V)
approximately 150kΩ (VDD = 3.0 to 3.6V)
∗
PUL1 register
"0" after a reset
PG register
Undefined after a reset
PG4 to PG7
Hi-Z
PGD register
IP
"0" after a reset
Internal data bus
RD
∗ Pull-up transistor
approximately 100kΩ (VDD = 4.5 to 5.5V)
approximately 150kΩ (VDD = 3.0 to 3.6V)
–9–
CXP922P032
Circuit format
Pin
CS0
SI0
CS0
SI0
After a reset
IP
Hi-Z
CMOS Schmitt input
SO0
SO0
Hi-Z
SO0 output enable
SCK0
SCK0
SCK0 output enable
IP
"H" level
(Hi-Z during a
reset)
SCK0
CMOS Schmitt input
∗
PUL1 register
"0" after a reset
PH register
Undefined after a reset
PH0/CS1
PH1/SI1
PH4/CS2
PH5/SI2
PHD register
IP
"0" after a reset
Internal data bus
RD
CS1, SI1, CS2, SI2
CMOS Schmitt input
∗ Pull-up transistor
approximately 100kΩ (VDD = 4.5 to 5.5V)
approximately 150kΩ (VDD = 3.0 to 3.6V)
– 10 –
Hi-Z
CXP922P032
Pin
Circuit format
After a reset
∗
PUL1 register
"0" after a reset
SO1, SO2
SO1, SO2 output enable
PHSL register
PH2/SO1
PH6/SO2
"0" after a reset
Hi-Z
IP
PH register
Undefined after a reset
PHD register
"0" after a reset
Internal data bus
RD
∗ Pull-up transistor
approximately 100kΩ (VDD = 4.5 to 5.5V)
approximately 150kΩ (VDD = 3.0 to 3.6V)
∗
PUL1 register
"0" after a reset
SCK1, SCK2
SCK1, SCK2 output enable
PHSL register
"0" after a reset
PH3/SCK1
PH7/SCK2
PH register
IP
Undefined after a reset
Hi-Z
PHD register
"0" after a reset
Internal data bus
RD
SCK1, SCK2
CMOS Schmitt input
∗ Pull-up transistor
approximately 100kΩ (VDD = 4.5 to 5.5V)
approximately 150kΩ (VDD = 3.0 to 3.6V)
∗
PUL2 register
"0" after a reset
TxD
TxD output enable
PI register
PI0/TxD
Undefined after a reset
IP
PID register
"0" after a reset
Internal data bus
∗ Pull-up transistor
RD
approximately 100kΩ (VDD = 4.5 to 5.5V)
approximately 150kΩ (VDD = 3.0 to 3.6V)
– 11 –
Hi-Z
CXP922P032
Pin
Circuit format
After a reset
∗
PUL2 register
"0" after a reset
PI register
Undefined after a reset
PI1/RxD
PI4/EC0
PI5/EC1
PI6/CINT
PI7/RMC
PID register
IP
Hi-Z
"0" after a reset
Internal data bus
RD
RxD, EC0, EC1, CINT, RMC
CMOS Schmitt input
∗ Pull-up transistor
approximately 100kΩ (VDD = 4.5 to 5.5V)
approximately 150kΩ (VDD = 3.0 to 3.6V)
∗
PUL2 register
"0" after a reset
PI register
Undefined after a reset
Hi-Z
PI2 to PI3
PID register
IP
"0" after a reset
Internal data bus
RD
∗ Pull-up transistor
approximately 100kΩ (VDD = 4.5 to 5.5V)
approximately 150kΩ (VDD = 3.0 to 3.6V)
∗
PUL2 register
"0" after a reset
PJ register
Undefined after a reset
PJ0/KS0
to PJ6/KS6
PJD register
IP
"0" after a reset
Internal
data bus
RD
Standby
release
∗ Pull-up transistor
approximately 100kΩ (VDD = 4.5 to 5.5V)
approximately 150kΩ (VDD = 3.0 to 3.6V)
– 12 –
Hi-Z
CXP922P032
Circuit format
Pin
IP
EXTAL
EXTAL
XTAL
• Diagram shows circuit
configuration during
oscillation.
• Feedback resistor is
removed during stop
mode, and XTAL is
driven at "H" level.
Oscillation stop control
XTAL
Mask option
After a reset
Oscillation
∗
OP
RST
"L" level
(during a reset)
IP
CMOS Schmitt input
∗ Pull-up transistor
approximately 300kΩ (VDD = 4.5 to 5.5V)
approximately 500kΩ (VDD = 3.0 to 3.6V)
– 13 –
CXP922P032
(VSS = 0V reference)
Absolute Maximum Ratings
Item
Supply voltage
Symbol
Rating
Unit
VDD
–0.3 to +7.0
V
VPP
–0.3 to +13.0
V
AVDD
AVSS to +7.0∗1
V
AVREF
AVSS to +7.0
V
AVSS
V
Remarks
Unique to version with
incorporated PROM
Input voltage
VIN
–0.3 to +0.3
–0.3 to +7.0∗2
Output voltage
VOUT
–0.3 to +7.0∗2
V
High level output current
IOH
–5
mA
Output (value per pin)
High level total output current
∑IOH
–50
mA
Total for all output pins
IOL
15
mA
IOLC
20
mA
Low level total output current
∑IOL
130
mA
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +150
°C
Allowable power dissipation
PD
600
mW
V
Low level output current
All pins excluding large current
output pins (value per pin)
Large current output pins∗3
(value per pin)
Total for all output pins
QFP-100P-L01
∗1 AVDD must be the same voltage.
∗2 VIN and VOUT must not exceed VDD + 0.3V.
∗3 The large current drive transistor is N-ch transistor of PD and PE.
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
be conducted under the recommended operating conditions. Exceeding these conditions may adversely
affect the reliability of the LSI.
– 14 –
CXP922P032
(VSS = 0V reference)
Recommended Operating Conditions
Item
Symbol
Min.
Max.
Unit
Remarks
3.0
5.5
V
2.7
5.5
V
fEX = 20MHz or less Guaranteed operation range
for 2, 4 and 8 frequency
fEX = 12MHz or less dividing clocks
2.7
5.5
V
2.5
5.5
V
AVDD
2.7
5.5
V
AVREF
2.7
5.5
V
0.7VDD
VDD
V
∗2, ∗4
0.8VDD
VDD
V
∗2, ∗5
VIHS
0.8VDD
VDD
V
CMOS Schmitt input∗3
VIHEX
0.7VDD
VDD + 0.3
V
0
0.3VDD
V
EXTAL
∗2, ∗4
0
0.2VDD
V
∗2, ∗5
0
0.2VDD
V
–0.3
0.3VDD
V
CMOS Schmitt input∗3
EXTAL∗4
–0.3
0.2VDD
V
EXTAL∗5
–20
+75
°C
VDD
Supply voltage
VIH
High level input
voltage
VIL
Low level input
voltage
VILS
VILEX
Operating temperature
Topr
Guaranteed operation range for 1/16 frequency
dividing clock or sleep mode
Guaranteed data hold range during stop mode
∗1
∗1 AVDD and VDD must be the same voltage.
∗2 PA, PB, PC, PD, PE, PG, PH2, PH6, PI0, PI2, PI3, PJ for normal input port.
∗3 PF0 to PF5, PH0, PH1, PH3 to PH5, PH7, PI1, PI4 to PI7, CS0, SI0, SCK0, RST.
∗4 When the supply voltage (VDD) is within the range of 4.5 to 5.5V.
∗5 When the supply voltage (VDD) is within the range of 2.7 to 5.5V.
– 15 –
CXP922P032
Electrical Characteristics
DC Characteristics (VDD = 4.5 to 5.5V)
Item
High level
output
voltage
Low level
output
voltage
Symbol
VOH
VOL
Pins
PA to PE, PF6,
PF7, PG to PJ,
SO0, SCK0
IILE
Input
capacitance
Typ.
Max.
Unit
VDD = 4.5V, IOH = –0.5mA
4.0
V
VDD = 4.5V, IOH = –1.2mA
3.5
V
0.4
V
VDD = 4.5V, IOL = 3.6mA
0.6
V
PD, PE
VDD = 4.5V, IOL = 12.0mA
1.5
V
EXTAL
RST∗1
IIL
PA to PE∗2,
PG to PJ∗2
VDD = 5.5V, VIH = 5.5V
0.5
40
µA
VDD = 5.5V, VIL = 0.4V
–0.5
–40
µA
VDD = 5.5V, VIL = 0.4V
–1.5
–400
µA
–45
µA
VDD = 5.5V, VIL = 0.4V
VDD = 4.5V, VIH = 4.0V
µA
–2.78
PA to PE∗2,
PF0 to PF5, PF7,
PG to PJ∗2,
VDD = 5.5V, VI = 0, 5.5V
AN0 to AN3,
CS0, SI0,
SO0, SCK0,
RST∗1
±10
µA
VDD = 5 ± 0.5V,
20MHz crystal oscillation
(C1 = C2 = 10pF)
45
75
mA
IDDS1
VDD = 5 ± 0.5V,
20MHz crystal oscillation
(C1 = C2 = 10pF), sleep mode
8
14
mA
IDDS2
VDD = 5.5V, stop mode
10
µA
20
pF
IDD∗4
Supply
current∗3
Min.
VDD = 4.5V, IOL = 1.8mA
IILR
I/O leakage
IIZ
current
Conditions
PA to PE, PF6,
PF7, PG to PJ,
SO0, SCK0
IIHE
Input
current
(Topr = –20 to +75°C, VSS = 0V reference)
VDD, VSS
CIN
PA to PE,
PF0 to PF5,
PG to PJ,
AN0 to AN3,
CS0, SI0,
SCK0,
EXTAL, RST
Clock 1MHz
0V for all pins excluding measured
pins
10
∗1 RST specifies the input current when pull-up resistor has been selected; the leakage current when no
resistor has been selected.
∗2 PA to PE and PG to PJ specify the input current when pull-up resistor has been selected; the leakage
current when no resistor has been selected.
∗3 When all output pins are open.
∗4 When the upper two bits (PCK1, PCK0) of the clock control register (CLC: 0002FEh) are set to "00" and
the LSI is operated in high-speed mode (2 frequency dividing clock).
– 16 –
CXP922P032
DC Characteristics (VDD = 3.0 to 3.6V)
Item
High level
output
voltage
Low level
output
voltage
Symbol
VOH
VOL
IIHE
IILE
Input
current
Pins
Min.
Typ.
Max.
Unit
VDD = 3.0V, IOH = –0.15mA
2.7
V
VDD = 3.0V, IOH = –0.5mA
2.3
V
PA to PE, PF6,
PF7, PG to PJ,
SO0, SCK0
VDD = 3.0V, IOL = 1.2mA
0.3
V
VDD = 3.0V, IOL = 1.6mA
0.5
V
PD, PE
VDD = 3.0V, IOL = 5.0mA
1.0
V
EXTAL
RST∗1
IIL
PA to PE∗2,
PG to PJ∗2
VDD = 3.6V, VIH = 3.6V
0.3
20
µA
VDD = 3.6V, VIL = 0.3V
–0.3
–20
µA
VDD = 3.6V, VIL = 0.3V
–0.7
–200
µA
–30
µA
VDD = 3.6V, VIL = 0.3V
VDD = 3.0V, VIH = 2.7V
–1.0
µA
PA to PE∗2,
PF0 to PF5, PF7,
PG to PJ∗2,
VDD = 3.6V, VI = 0, 3.6V
AN0 to AN3,
CS0, SI0,
SO0, SCK0,
RST∗1
±10
µA
VDD = 3.3 ± 0.3V,
20MHz crystal oscillation
(C1 = C2 = 10pF)
25
45
mA
IDDS1
VDD = 3.3 ± 0.3V,
20MHz crystal oscillation
(C1 = C2 = 10pF), sleep mode
4.5
8
mA
IDDS2
VDD = 3.6V, stop mode
10
µA
20
pF
IDD∗4
Supply
current∗3
Conditions
PA to PE, PF6,
PF7, PG to PJ,
SO0, SCK0
IILR
I/O leakage
IIZ
current
(Topr = –20 to +75°C, VSS = 0V reference)
VDD, VSS
Input
CIN
capacitance
PA to PE,
PF0 to PF5,
PG to PJ,
AN0 to AN3,
CS0, SI0,
SCK0,
EXTAL, RST
Clock 1MHz
0V for all pins excluding measured
pins
10
∗1 RST specifies the input current when pull-up resistor has been selected; the leakage current when no
resistor has been selected.
∗2 PA to PE and PG to PJ specify the input current when pull-up resistor has been selected; the leakage
current when no resistor has been selected.
∗3 When all output pins are open.
∗4 When the upper two bits (PCK1, PCK0) of the clock control register (CLC: 0002FEh) are set to "00" and
the LSI is operated in high-speed mode (2 frequency dividing clock).
– 17 –
CXP922P032
AC Characteristics
(1) Clock timing
(Topr = –20 to +75°C, VDD = 2.7 to 5.5V, VSS = 0V reference)
Item
Symbol
Pins
Conditions
Min.
VDD = 3.0 to 5.5V
Typ.
Max.
1
20
1
12
Main clock base oscillation
frequency
fEX
XTAL
EXTAL
Fig.1, Fig.2
Main clock base oscillation
input pulse width
tXL,
tXH
EXTAL
Fig.1, Fig.2 VDD = 3.0 to 5.5V 23
External clock drive
37.5
Main clock base oscillation
input rise time, fall time
tXR,
tXF
EXTAL
Fig.1, Fig.2
External clock drive
Unit
MHz
ns
100
ns
Note) tsys indicates the four values below according to the upper two bits (PCK1,PCK0) of the clock control
register (CLC: 0002FEh).
tsys [ns] = 2/fEX (PCK1, PCK0 = 00), 4/fEX (PCK1, PCK0 = 01), 8/fEX (PCK1, PCK0 = 10), 16/fEX (PCK1,
PCK0 = 11)
1/fEX
0.7VDD
EXTAL
0.3VDD ( VDD = 4.5 to 5.5 V )
0.2VDD ( VDD = 2.7 to 5.5 V )
tXH
tXF
tXL
tXR
Fig.1. Clock timing
Oscillator connection
example of
main oscillation circuit
EXTAL
Connection example of
external clock
XTAL
EXTAL
XTAL
74HC04
C1
C2
Fig.2. Oscillator connection and clock applied conditions
– 18 –
CXP922P032
(2) Event count input
Item
Event count input clock
pulse width
(Topr = –20 to +75°C, VDD = 2.7 to 5.5V, VSS = 0V reference)
Symbol
tEH,
tEL
Pins
Conditions
EC0,
EC1
Min.
Max.
tsys + 100
Fig.3
Unit
ns
0.8VDD
EC0
EC1
0.2VDD
tEH
tEL
Fig.3. Event count input timing
(3) Interruption and reset input
Item
External interruption
high, low level width
Symbol
tIH,
tIL
(Topr = –20 to +75°C, VDD = 2.7 to 5.5V, VSS = 0V reference)
Pins
Conditions
Main mode
NMI
INT0 to INT4 Sleep mode
KS0 to KS6 Stop mode
INT0, INT1,
INT4
Reset input low level
width
tRST
Min.
Noise filter
selected
ns
1
µs
2tsys + 100
PS4
32/fEX + 100
PS6
128/fEX + 100
3tsys + 200
tIH
tIL
0.8VDD
NMI
INT0 to INT7
KS0 to KS6
0.2VDD
Fig.4. Interruption input timing
tRST
RST
0.2VDD
Fig.5. Reset input timing
– 19 –
Unit
tsys + 100
φ
Fig.5
RST
Max.
ns
ns
CXP922P032
(4) A/D converter characteristics
(Topr = –20 to +75°C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, VSS = AVSS = 0V reference)
Item
Symbol
Pins
Conditions
Min.
Typ.
Resolution
Linearity error
VDD = AVDD = AVREF = 5.0V
Absolute error
Conversion time
Sampling time
tCONV
tSAMP
Reference input
voltage
VREF
AVREF
Analog input
voltage
VIAN
AN0 to AN7
AVREF
AVREF current
IREFS
Unit
8
Bits
±2
LSB
±3
LSB
31/fADC∗
10/fADC∗
µs
AVDD – 0.5
V
0
V
Main mode
IREF
Max.
µs
0.6
Sleep mode
Stop mode
1.0
mA
10
µA
(Topr = –20 to +75°C, VDD = AVDD = 3.0 to 3.6V, AVREF = 2.7 to AVDD, VSS = AVSS = 0V reference)
Item
Symbol
Pins
Conditions
Min.
Typ.
Resolution
Linearity error
VDD = AVDD = AVREF = 3.3V
Absolute error
Conversion time
Sampling time
Reference input
voltage
VREF
AVREF
Analog input
voltage
VIAN
AN0 to AN7
Main mode
IREF
AVREF
IREFS
Unit
8
Bits
±2
LSB
±3
LSB
31/fADC∗
10/fADC∗
tCONV
tSAMP
AVREF current
Max.
Sleep mode
Stop mode
– 20 –
µs
µs
AVDD – 0.3
V
0
V
0.4
0.7
mA
10
µA
CXP922P032
∗ fADC indicates the below values due to the contents of Bit 6 (CKS) of the A/D control register (ADC: 000131h).
When PS3 is selected, fADC = fEX/8
When PS4 is selected, fADC = fEX/16
However, when PS3 is selected, fEX is 12MHz or less.
(100h)
FFh
FEh
Digital conversion value
Digital conversion value
FFh
FEh
Linearity error
01h
00h
VZT∗1
Analog input
Absolute error
01h
00h
VFT∗2
Absolute error
Analog input
∗1 VZT: Value at which the digital conversion value changes from 00h to 01h and vice versa.
∗2 VFT: Value at which the digital conversion value changes from FEh to FFh and vice versa.
Fig.6. Definition of A/D converter terms
– 21 –
VREF
CXP922P032
(5) Serial transfer (CH0, CH1, CH2)
Item
(Topr = –20 to +75°C, VDD = 4.5 to 5.5V, VSS = 0V reference)
Symbol
Pins
Conditions
CS ↓ → SCK
delay time
tDCSK
SCK0
SCK1
SCK2
CS ↑ → SCK
float delay time
SCK0
tDCSKF SCK1
CS ↓ → SO
delay time
tDCSO
CS ↑ → SO
float delay time
tDCSOF SO1
CS high level width
tWHCS
CS0
CS1
CS2
SCK cycle time
tKCY
SCK2
SO0
SO1
SO2
Min.
Max.
Unit
External start transfer mode
(SCK = output mode)
1.5tsys + 100
ns
External start transfer mode
(SCK = output mode)
1.5tsys + 100
ns
External start transfer mode
1.5tsys + 100
ns
External start transfer mode
1.5tsys + 100
ns
SO0
SO2
External start transfer mode
tsys + 100
ns
SCK0
SCK1
SCK2
Input mode
2tsys + 150
ns
8/fEX
ns
Output mode
SCK
high, low pulse width
tKH
tKL
SCK0
SCK1
SCK2
Input mode
tsys + 60
ns
Output mode
4/fEX – 25
ns
SI input data setup time
(for SCK ↑)
SI0
SI1
SI2
SCK input mode
50
ns
tSIK
SCK output mode
100
ns
SI input data hold time
(for SCK ↑)
SI0
SI1
SI2
SCK input mode
tsys + 100
ns
tKSI
50
ns
SCK ↓ → SO
delay time
tKSO
SO0
SO1
SO2
SCK input mode
SCK0
SCK1
SCK2
SCK input mode
Minimum interval time
tINT
SCK output mode
tsys + 100
ns
50
ns
SCK output mode
SCK output mode
3tsys + 100
ns
8/fEX
ns
Note) The load condition for the SCK output mode and SO output delay time is 50pF+1TTL.
– 22 –
CXP922P032
(Topr = –20 to +75°C, VDD = 3.0 to 3.6V, VSS = 0V reference)
Item
Symbol
Pins
Conditions
CS ↓ → SCK
delay time
tDCSK
SCK0
SCK1
SCK2
CS ↑ → SCK
float delay time
tDCSKF SCK1
CS ↓ → SO
delay time
tDCSO
CS ↑ → SO
float delay time
tDCSOF SO1
CS high level width
tWHCS
CS0
CS1
CS2
SCK cycle time
tKCY
SCK0
SCK2
SO0
SO1
SO2
Min.
Max.
Unit
External start transfer mode
(SCK = output mode)
1.5tsys + 200
ns
External start transfer mode
(SCK = output mode)
1.5tsys + 200
ns
External start transfer mode
1.5tsys + 200
ns
External start transfer mode
1.5tsys + 200
ns
SO0
SO2
External start transfer mode
tsys + 200
ns
SCK0
SCK1
SCK2
Input mode
2tsys + 200
ns
8/fEX
ns
Output mode
SCK
high, low pulse width
tKH
tKL
SCK0
SCK1
SCK2
Input mode
tsys + 80
ns
Output mode
4/fEX – 50
ns
SI input data setup time
(for SCK ↑)
SI0
SI1
SI2
SCK input mode
80
ns
tSIK
SCK output mode
150
ns
SI input data hold time
(for SCK ↑)
SI0
SI1
SI2
SCK input mode
tsys + 120
ns
tKSI
70
ns
SCK ↓ → SO
delay time
SO0
SO1
SO2
SCK input mode
tKSO
tINT
SCK0
SCK1
SCK2
SCK input mode
Minimum interval time
SCK output mode
SCK output mode
SCK output mode
ns
80
ns
3tsys + 150
ns
8/fEX
ns
Note) The load condition for the SCK output mode and SO output delay time is 50pF.
– 23 –
tsys + 200
CXP922P032
tWHCS
0.8VDD
CS0
CS1
CS2
0.2VDD
tKCY
tDCSK
tKL
tDCSKF
tKH
0.8VDD
SCK0
SCK1
SCK2
0.2VDD
tSIK
tKSI
0.8VDD
SI0
SI1
SI2
Input data
0.2VDD
tDCSO
tDCSOF
tKSO
0.8VDD
SO0
SO1
SO2
Output data
0.2VDD
tINT
0.8VDD
SCK0
SCK1
SCK2
Fig.7. Serial transfer CH0, CH1, CH2 timing
– 24 –
CXP922P032
(6) Remote control reception
Item
Remote control receive
high, low level width
(Topr = –20 to +75°C, VDD = 2.7 to 5.5V, VSS = 0V reference)
Symbol
tRMC
Pins
RMC
Conditions
Main mode
Sleep mode
Min.
PS5 selected
128/fEX + 100
PS6 selected
256/fEX + 100
PS8 selected 1024/fEX + 100
0.8VDD
RMC
0.2VDD
tRMC
tRMC
Fig.8. Remote control signal input timing
– 25 –
Max.
Unit
ns
CXP922P032
Appendix
(i) Main oscillation circuit
EXTAL
(ii) Main oscillation circuit
XTAL
EXTAL
XTAL
Rd
Rd
C2
C1
C1 C2
Fig.9. Recommended oscillation circuit
Model
fEX
(MHz)
CSA4.00MG
CSA8.00MTZ093
CSA10.0MTZ093
CSA12.0MTZ093
CST4.00MGW∗
CST8.00MTW093∗
CST10.0MTW093∗
CST12.0MTW093∗
4
8
10
12
4
8
10
12
16
16
20
20
4
8
10
12
16
20
Manufacturer
MURATA MFG
CO., LTD.
CSA16.00MXZ040
CST16.00MXW0C1∗
CSA20.00MXZ040
CST20.00MXW0H1∗
RIVER ELETEC HC-49/U03
CO., LTD.
C1 (pF)
KINSEKI LTD.
HC49/U-S
CCR4.0MC3∗
CCR8.0MC5∗
CCR10.0MC5∗
CCR12.0MC5∗
CCR16.0MC6∗
CCR20.0MC6∗
Rd
(Ω)
Circuit
example
Remarks
(i)
30
30
0
(ii)
4
8
10
12
16
20
4
8
10
12
16
20
C2 (pF)
5
5
0
27
15
10
10
8
6
27
15
10
10
8
6
560
330
330
180
0
0
22
22
2.2k
10
10
0
(i)
(ii)
(i)
(ii)
(i)
(i)
38 (±20%)
20 (±20%)
20 (±20%)
20 (±20%)
10 (±20%)
10 (±20%)
VDD = 4.0 to 5.5V
CL = 18.5pF
CL = 13.0pF
CL = 10.5pF
CL = 10.5pF
CL = 10.0pF
CL = 8.5pF
CL = 16pF
VDD = 3.0 to 5.5V
CL = 12pF
VDD = 3.5 to 5.5V
38 (±20%)
0
20 (±20%)
0
20 (±20%)
0
TDK
(ii)
Corporation
20 (±20%)
0
10 (±20%)
0
VDD = 3.5 to 5.5V
10 (±20%)
0
∗ Indicates types with on-chip grounding capacitor (C1, C2). CCR∗∗∗ : Surface mounted type ceramic oscillator.
CL
: Load capacitor
Mask option table
Item
Reset pin pull-up resistor
Content
Existent
Non-existent
– 26 –
CXP922P032
Characteristics Curve
IDD vs. VDD
(fEX = 20MHz, Topr = 25°C, Typical)
2 frequency dividing mode
50
IDD – Supply current [mA]
40
30
25
4 frequency dividing mode
20
8 frequency dividing mode
16 frequency dividing mode
15
10
Sleep mode
8
6
5
4
3
2
3
4
5
VDD – Supply voltage [V]
6
IDD vs. fEX
IDD – Supply current [mA]
(VDD = 5V, Topr= 25°C, Typical)
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
0
2 frequency dividing mode
4 frequency dividing mode
8 frequency dividing mode
16 frequency dividing mode
Sleep mode
0
fEX
15
20
5
10
– Main clock base oscillation frequency [MHz]
– 27 –
CXP922P032
Package Outline
Unit: mm
100PIN QFP (PLASTIC)
23.9 ± 0.4
+ 0.4
20.0 – 0.1
+ 0.1
0.15 – 0.05
80
51
+ 0.4
14.0 – 0.1
17.9 ± 0.4
15.8 ± 0.4
50
81
A
31
100
1
0.65
30
+ 0.15
0.3 – 0.1
0.13
+ 0.2
0.1 – 0.05
+ 0.35
2.75 – 0.15
M
0° to 10°
DETAIL A
0.8 ± 0.2
(16.3)
0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-100P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
QFP100-P-1420
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
1.7g
JEDEC CODE
– 28 –