LCX020BK
1.8cm (0.7-inch) Color LCD Panel
Description
The LCX020BK is a 1.8cm diagonal active matrix
TFT-LCD panel addressed by polycrystalline silicon
super thin film transistors with built-in peripheral driving
circuit. This panel provides full-color representation.
RGB dots are arranged in a striped pattern optimum
for data applications and capable of displaying fine
text and vertical lines.
The adoption of an advanced on-chip black matrix
realizes a high luminance screen, and high picture
quality is possible with built-in cross talk free and
ghost free circuits.
This panel has a polysilicon TFT high-speed
scanner and built-in function to display images
up/down and/or right/left inverse. In addition, the
built-in 5V interface circuit leads to lower voltage of
timing and control signals.
The panel contains a display area varying circuit
which supports Macintosh16∗1/SVGA/VGA/PC98∗2
data signals by changing the display area according
to the type of input signal. In addition, double-speed
processed NTSC/PAL/WIDE can also be supported.
∗1 "Macintosh" is a trademark of Apple Company Inc.
∗2 "PC98" is a trademark of NEC.
Features
• Number of active dots: 1,557,000, 1.8cm (0.7-inch) in diagonal
• Supports Macintosh16 (832 × 624), SVGA (800 × 600), VGA (640 × 480) and PC98 (640 × 400) display
• Supports NTSC (640 × 480), PAL (762 × 572) and WIDE (832 × 480) display by processing the video signal
at double speed
• High optical transmittance: 1% (typ.)
• Built-in cross talk free circuit
• High contrast ratio with normally white mode: 70 (typ.)
• Built-in H and V drivers (built-in input level conversion circuit, 5V driving possible)
• Up/down and/or right/left inverse display function
Element Structure
• Dots: 2496 (H) × 624 (V) = 1,557,504
• Built-in peripheral driving circuit using polycrystalline silicon super thin film transistors
Applications
• Liquid crystal EVFs for personal PCs/DVDs
• Small monitors, etc.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E99210-PS
PSIGG
3
PSIGR
2
4
PSIGB
Up/Down and/or Right/Left
Inversion Control Circuit
24 35
BLK
32
Input Signal
Level Shifter
Circuit
RGT
HCK2
28 29 30
V Shift Register (Bidirectional Scanning)
Black Frame Control Circuit
33
27
26
25
23
Black Frame Control Circuit
36
38
H Shift Register (Bidirectional Scanning)
34 37
31
5
6
7
8
COM
Pad
9 10 11 12 13 14 15 16 17 18 19 20 21 22 1
Black Frame Control Circuit
V Shift Register (Bidirectional Scanning)
HST
HCK1
VST
VCK
Block Diagram
The Block Diagram of the panel is shown below.
Precharge
Control Circuit
–2–
PCG
DWN
ENB
MODE1
MODE2
MODE3
HVDD
VVDD
VSS
SIGR1
SIGR2
SIGR3
SIGR4
SIGR5
SIGR6
SIGG1
SIGG2
SIGG3
SIGG4
SIGG5
SIGG6
SIGB1
SIGB2
SIGB3
SIGB4
SIGB5
SIGB6
COM
LCX020BK
LCX020BK
Absolute Maximum Ratings (Vss = 0V)
• H driver supply voltage
HVDD
• V driver supply voltage
VVDD
• Common pad voltage
COM
• H shift register input pin voltage
HST, HCK1, HCK2,
RGT
• V shift register input pin voltage
VST, VCK, PCG,
BLK, ENB, DWN
MODE1, MODE2, MODE3
• Video signal input pin voltage
SIGR1 to SIGR6,
SIGG1 to SIGG6,
SIGB1 to SIGB6,
PSIGR, PSIGG, PSIGB
• Operating temperature
Topr
• Storage temperature
Tstg
–1.0 to +20
–1.0 to +20
–1.0 to +17
–1.0 to +17
V
V
V
V
–1.0 to +17
V
–1.0 to +15
V
–10 to +70
–30 to +85
°C
°C
Operating Conditions (Vss = 0V)
• Supply voltage
15.5 ± 0.3V
HVDD
VVDD
15.5 ± 0.3V
• Input pulse voltage (Vp-p of all input pins except video signal and uniformity improvement signal input pins)
Vin
5.0 ± 0.5V
Pin Description
Pin
No.
Symbol
Description
1
COM
Common voltage of panel
2
PSIGR
Uniformity improvement signal input (R)
3
PSIGG
Uniformity improvement signal input (G)
4
PSIGB
Uniformity improvement signal input (B)
5
SIGR1
Video signal input to panel (R-1)
6
SIGR2
Video signal input to panel (R-2)
7
SIGR3
Video signal input to panel (R-3)
8
SIGR4
Video signal input to panel (R-4)
9
SIGR5
Video signal input to panel (R-5)
10
SIGR6
Video signal input to panel (R-6)
11
SIGG1
Video signal input to panel (G-1)
12
SIGG2
Video signal input to panel (G-2)
13
SIGG3
Video signal input to panel (G-3)
14
SIGG4
Video signal input to panel (G-4)
–3–
LCX020BK
Pin
No.
Symbol
15
SIGG5
Video signal input to panel (G-5)
16
SIGG6
Video signal input to panel (G-6)
17
SIGB1
Video signal input to panel (B-1)
18
SIGB2
Video signal input to panel (B-2)
19
SIGB3
Video signal input to panel (B-3)
20
SIGB4
Video signal input to panel (B-4)
21
SIGB5
Video signal input to panel (B-5)
22
SIGB6
Video signal input to panel (B-6)
23
HVDD
Power supply input for H driver
24
RGT
Drive direction input for H shift register (H: normal, L: reverse)
25
MODE3
Display area switching 3 input
26
MODE2
Display area switching 2 input
27
MODE1
Display area switching 1 input
28
HST
Start pulse input for H shift register drive
29
HCK1
Clock pulse input for H shift register drive
30
HCK2
Clock pulse input for H shift register drive
31
VSS
GND (H, V drivers)
32
BLK
Black frame display pulse input
33
ENB
Gate selection pulse enable input
34
VCK
Clock pulse input for V shift register drive
35
VST
Start pulse input for V shift register drive
36
DWN
Drive direction input for V shift register (H: normal, L: reverse)
37
PCG
Uniformity improvement pulse input
38
VVDD
Power supply input for V driver
39
SOUT
H and V shift register drive checking (Test pin; no connection.)
Description
–4–
LCX020BK
Input Equivalent Circuits
To prevent static charges, protective diodes are provided for each pin except the power supplies. In addition,
protective resistors are added to all pins except video signal inputs. All pins are connected to Vss with a high
resistance of 1MΩ (typ.). The equivalent circuit of each input pin is shown below: (Resistor value: typ.)
(1) SIGR1 to SIGR6, SIGG1 to SIGG6, SIGB1 to SIGB6, PSIGR, PSIGG, PSIGB
HVDD
Input
1MΩ
Signal line
(2) HCK1, HCK2
HVDD
250Ω
250Ω
Input
Level conversion circuit
(2-phase input)
1MΩ
250Ω
250Ω
1MΩ
(3) RGT, MODE1, MODE2, MODE3
HVDD
2.5kΩ
2.5kΩ
Level conversion circuit
(single-phase input)
Input
1MΩ
(4) HST
HVDD
250Ω
250Ω
Input
Level conversion circuit
(single-phase input)
1MΩ
(5) PCG, VCK
VVDD
250Ω
250Ω
Level conversion circuit
(single-phase input)
Input
1MW
(6) VST, BLK, ENB, DWN
VVDD
2.5kΩ
2.5kΩ
Input
Level conversion circuit
(single-phase input)
1MΩ
(7) COM
VVDD
Input
LC
1MΩ
–5–
LCX020BK
Input Signals
1. Input signal voltage conditions (Vss = 0V)
Item
Symbol
H shift register input voltage (Low)
HST, HCK1, HCK2, RGT
(High)
V shift register input voltage (Low)
MODE1, MODE2, MODE3,
BLK, VST, VCK, PCG,
(High)
ENB, DWN
Video signal center voltage
Video signal input range∗1
Common pad voltage of panel∗2
Uniformity improvement signal input
voltage (PSIGR, PSIGG, PSIGB)∗3
Min.
Typ.
Max.
Unit
VHIL
–0.5
0.0
0.4
V
VHIH
4.5
5.0
5.5
V
VVIL
–0.5
0.0
0.4
V
VVIH
4.5
5.0
5.5
V
VVC
6.9
7.0
7.1
V
Vsig
VVC – 4.5
7.0
VVC + 4.5
V
Vcom
VVC – 0.5
VVC – 0.4
VVC – 0.3
V
Vpsig1
VVC ± 2.0
VVC ± 3.0
VVC ± 4.0
V
Vpsig2
VVC ± 4.0
VVC ± 4.5
VVC ± 4.6
V
∗1 Video input signal shall be symmetrical to VVC.
∗2 The optimum typical value of the common pad voltage may lower its suitable voltage according to the set
construction to use. In this case, use the voltage of which has maximum contrast as typical value. When the
typical value is lowered, the maximum and minimum values may lower.
∗3 Input a uniformity improvement signals PSIGR, PSIGG and PSIGB in the same polarity with video signals
SIGR1 to 6, SIGG1 to 6 and SIGB1 to 6 and which is symmetrical to VVC. PSIGR, PSIGG and PSIGB have
two steps as shown by the waveform in the figure below, and in the table above, the upper value indicates
the signal level of the first step, and the lower value, the signal level of the second step.
Here, the rising and falling of PSIGR, PSIGG and PSIGB are synchronized with the rising of PCG pulse,
and the rise and fall times trPSIGR, trPSIGG, trPSIGB, tfPSIGR, tfPSIGG and tfPSIGB are suppressed
within 800ns.
Input waveform of uniformity improvement signal PSIG
PRG
90%
PSIGR,
PSIGG,
PSIGB
Vpsig2
VVC
Vpsig1
10%
trPSIGR,
trPSIGG,
trPSIGB
tfPSIGR,
tfPSIGG,
tfPSIGB
LCX020BK level conversion circuit
The LCX020BK has a built-in level conversion circuit in the clock input unit on the panel. The input signal level
increases to HVDD or VVDD. The Vcc of external ICs are applicable to 5 ± 0.5V.
–6–
LCX020BK
2. Clock timing conditions (Ta = 25°C)
(Macintosh16 mode: fHckn = 4.8MHz, fVck = 24.9kHz)
Item
HST
HCK
VST
VCK
ENB
PCG
BLK∗5
Symbol
Min.
Typ.
Max.
Hst rise time
trHst
—
—
30
Hst fall time
tfHst
—
—
30
Hst data setup time
tdHst
70
80
90
Hst data hold time
Hckn rise time∗4
thHst
15
25
35
trHckn
—
—
30
Hckn fall time∗4
tfHckn
—
—
30
Hck1 fall to Hck2 rise time
to1Hck
–15
0
15
Hck1 rise to Hck2 fall time
to2Hck
–15
0
15
Vst rise time
trVst
—
—
100
Vst fall time
tfVst
—
—
100
Vst data setup time
tdVst
5
10
15
Vst data hold time
thVst
5
10
15
Vck rise time
trVck
—
—
100
Vck fall time
tfVck
—
—
100
Enb rise time
trEnb
—
—
100
Enb fall time
tfEnb
—
—
100
Vck rise/fall to Enb rise time
toEnb
400
500
—
Horizontal video period end to Enb fall time
tdEnb
900
1000
—
Enb fall to Pcg rise time
toPcg
900
1000
—
Pcg rise time
trPcg
—
—
30
Pcg fall time
tfPcg
—
—
30
Pcg rise to Prg rise time
toPrgr
0
—
—
Pcg fall to Prg fall time
toPrgf
200
250
—
Pcg rise to Vck rise/fall time
toVck
0
1000
1100
Pcg pulse width
twPcg
1100
1200
1300
Blk rise time
trBlk
—
—
100
Blk fall time
tfBlk
—
—
100
Blk fall to Vst rise time
toVst
1
—
2
Blk pulse width
twBlk
1
—
—
∗4 Hckn means Hck1 and Hck2.
∗5 Blk is the timing during SVGA mode (fHckn = 4.0MHz, fVck = 24.0kHz).
This pulse is positive polarity other than in Macintosh16 mode. Set to L level in Macintosh16 mode.
–7–
Unit
ns
µs
ns
line
LCX020BK
<Horizontal Shift Register Driving Waveform>
Item
Hst rise time
Symbol
Waveform
90%
trHst
Hst
Hst fall time
HST
Conditions
90%
10%
tfHst
10%
trHst
tfHst
∗6
Hst data setup time
tdHst
50%
50%
Hst
Hck1
Hst data hold time
50%
thHst
50%
tdHst
Hckn rise time∗3
∗3
Hckn fall time∗3
Hck1 fall
to Hck2 rise time
10%
trHckn
∗6
to1Hck
90%
10%
tfHckn
50%
∗6 Definitions:
The right-pointing arrow (
The left-pointing arrow (
The black dot at an arrow (
tfHckn
50%
Hck1
50%
Hck1 rise
to Hck2 fall time
50%
Hck2
to2Hck
to2Hck
to1Hck
) means +.
) means –.
) indicates the start of measurement.
–8–
• Hckn∗3
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
thHst
90%
trHckn
Hckn
HCK
• Hckn∗3
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
• Hckn∗3
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
LCX020BK
<Vertical Shift Register Driving Waveform>
Item
Vst rise time
Symbol
Waveform
90%
trVst
Vst
Vst fall time
90%
10%
10%
tfVst
trVst
tfVst
∗6
VST
50%
Vst data setup time
tdVst
50%
Vst
50%
50%
Vck
Vst data hold time
Vck rise time
thVst
trVck
Vck fall time
tfVck
Enb rise time
trEnb
thVst
90%
90%
10%
Vck
VCK
tdVst
10%
trVckn
90%
10%
tfVckn
10%
90%
Enb
Enb fall time
tfEnb
tfEn
ENB
Vck rise/fall
to Enb rise time
toEnb
trEn
Horizontal blanking period
Horizontal video period
Vck
Horizontal video period end
to Enb fall time
50%
tdEnb
Enb
toEnb
50%
toPcg
Enb fall to Pcg rise time
toPcg
Pcg rise time
trPcg
Pcg fall time
tfPcg
PCG∗7 Pcg rise
to Vck rise/fall time
BLK
trPcg
Blk rise time
twBlk
Blk fall time
tfBlk
Blk fall to Vst rise time
toVst
Blk pulse width
twBlk
tdEnb
50%
Pcg
∗6
50%
Vck
toVck
toVck
Pcg pulse width
50%
50%
Pcg
∗6
50%
twPcg
Vst
Blk 50%
∗6
50%
50%
twBlk
toVst
∗7 Input the pulse obtained by taking the OR of the above pulses and BLK to the PCG input pin.
–9–
LCX020BK
Electrical Characteristics (Ta = 25°C, HVDD = 15.5V, VVDD = 15.5V)
1. Horizontal drivers
Item
Input pin capacitance
Input pin current
Symbol
Min.
Typ. Max. Unit
HCKn
CHckn
—
8
13
pF
HST
CHst
—
8
13
pF
HCK1
–500
–110
—
µA
HCK1 = GND
HCK2
–1000 –350
—
µA
HCK2 = GND
HST
–500
–180
—
µA
HST = GND
RGT
–150
–30
—
µA
RGT = GND
Video signal input pin capacitance
Csig
—
150
270
pF
Current consumption
IH
—
16.0 30.0
mA
Condition
HCKn: HCK1, HCK2 (4.8MHz)
2. Vertical drivers
Item
Input pin capacitance
Input pin current
Symbol Min.
Typ. Max. Unit
VCK
CVck
—
8
13
pF
VST
CVst
—
8
13
pF
–1000 –160
—
µA
VCK = GND
–150
–30
—
µA
PCG, VST, ENB, DWN, BLK,
MODE1, MODE2, MODE3 = GND
—
3.0
5.0
mA
VCK: (24.9kHz)
VCK
PCG, VST, ENB, DWN, BLK,
MODE1, MODE2, MODE3
Current consumption
IV
3. Total power consumption of the panel
Item
Symbol Min.
Total power consumption of the panel
PWR
(MAC16)
—
Typ. Max. Unit
300
600
mW
Typ.
Max. Unit
4. Pin input resistance
Item
Pin – Vss input resistance
Symbol Min.
Rpin
0.4
1
—
MΩ
5. Uniformity improvement signal input capacitance
Item
Condition
Symbol Min.
Uniformity improvement signal input
CPSIGon
capacitance
—
Typ.
7
– 10 –
Max. Unit
16
nF
LCX020BK
Electro-optical Characteristics
(Ta = 25°C, NTSC mode)
Symbol
Item
Contrast ratio
25°C
CR25
60°C
CR60
Optical transmittance
G
B
V90
V-T
characteristics
V50
V10
Half tone color reproduction
range
ON time
Response time
OFF time
Flicker
Image retention time
1
2
T
R
Chromaticity
Measurement method
Min.
Typ.
Max.
40
70
—
40
70
—
0.85
1.0
—
Unit
—
%
X
Rx
0.560
0.600 0.670
Y
Ry
0.300
0.360 0.410
X
Gx
0.260
Y
Gy
0.541
0.300 0.350 CIE
0.595 0.650 standards
X
Bx
0.120
0.148 0.187
Y
By
0.040
0.148 0.187
3
25°C
V90-25
0.9
1.4
2.0
60°C
V90-60
1.0
1.6
2.2
25°C
V50-25
1.2
1.8
2.4
60°C
V50-60
1.3
1.9
2.5
25°C
V10-25
1.9
2.4
3.0
60°C
V10-60
1.8
2.3
3.0
R-G
V50RG
—
–0.10
0.25
B-G
V50BG
—
0.05
0.45
0°C
ton0
—
20
100
25°C
ton25
—
14
40
0°C
toff0
—
45
150
25°C
toff25
—
35
70
60°C
F
7
—
—
–40
dB
YT60
8
—
—
20
s
60 min.
4
5
6
– 11 –
V
V
ms
LCX020BK
<Electro-optical Characteristics Measurement>
Basic measurement conditions
(1) Driving voltage
HVDD = 15.5V, VVDD = 15.5V
VVC = 7.0V, Vcom = 6.6V
(2) Measurement temperature
25°C unless otherwise specified.
(3) Measurement point
One point in the center of the screen unless otherwise specified.
(4) Measurement systems
Two types of measurement system are used as shown below.
(5) Video input signal voltage (Vsig)
Vsig = 7.0 ± VAC [V] (VAC = signal amplitude)
Back Light
∗ Measurement system I
Measurement
Equipment
Luminance
Meter
3.5mm
Back light: color temperature 6800K ± 700K (25°C)
∗ Back light spectrum (reference) is listed on another page.
LCD panel
∗ Measurement system II
Optical fiber
Light receptor lens
Light Detector
Measurement
Equipment
LCD panel
Drive Circuit
Light Source
1. Contrast Ratio
Contrast Ratio (CR) is given by the following formula (1).
CR =
L (White)
... (1)
L (Black)
L (White): Surface luminance of the TFT-LCD panel at the input signal amplitude VAC = 0.5V.
L (Black): Surface luminance of the panel at VAC = 4.5V.
Both luminosities are measured by System I.
– 12 –
LCX020BK
2. Optical Transmittance
Optical Transmittance (T) is given by the following formula (2).
T=
L (White)
× 100 [%] ... (2)
Luminance of Back Light
L (White) is the same expression as defined in the "Contrast Ratio" section.
Optical transmittance is measured by System I.
3. Chromaticity
Chromaticity of the panel is measured by System I. Raster modes of each color are defined by the
representations at the input signal amplitude conditions shown in the table below. System I uses x and y of
the CIE standards as the chromaticity here.
Raster
Signal amplitudes (VAC) supplied to each input
R input
G input
B input
R
0.5
4.5
4.5
G
4.5
0.5
4.5
B
4.5
4.5
0.5
4. V-T Characteristics
V-T characteristics, or the relationship between signal
amplitude and the transmittance of the panel, are
measured by System II by inputting the same signal
amplitude VAC to each input pin. V90, V50, and V10
correspond to each voltage which defines 90%, 50%,
and 10% of transmittance respectively.
Transmittance [%]
(Unit: V)
90
50
10
V90
V50 V10
VAC – Signal amplitude [V]
V50RG = V50R – V50G ... (3)
V50BG = V50B – V50G ... (4)
100
Transmittance [%]
5. Half Tone Color Reproduction Range
The half tone color reproduction range of the LCD
panel is characterized by the differences between the
V-T characteristics of R, G and B. The differences of
these V-T characteristics are measured by System II.
System II defines signal voltages of each R, G and B
raster mode which correspond to 50% of transmittance,
V50R, V50G and V50B respectively. V50RG and V50BG
represent the differences between V50R and V50G and
between V50B and V50G, and are given by the following
formulas (3) and (4) respectively.
V50RG
V50BG
50
G raster
R raster
0
B raster
V50R V50B
V50G
VAC – Signal amplitude [V]
– 13 –
LCX020BK
6. Response Time
Response time ton and toff are defined
by formulas (5) and (6) respectively.
ton = t1 – tON ... (5)
toff = t2 – tOFF ... (6)
t1: time which gives 10% transmittance
of the panel.
t2: time which gives 90% transmittance
of the panel.
The relationships between t1, t2, tON
and tOFF are shown in the right figure.
Input signal voltage (Waveform applied to the measured pixels)
4.5V
0.5V
7.0V
0V
Optical transmittance output waveform
100%
90%
10%
0%
tON
t1
ton
tOFF
t2
toff
7. Flicker
Flicker (F) is given by the formula (7). DC and AC (MAC16/SVGA/VGA/PC98/NTSC: 30Hz, rms, PAL:
25Hz, rms) components of the panel output signal for gray raster∗ mode are measured by a DC voltmeter
and a spectrum analyzer in System II.
F [dB] = 20log {
AC component
} ... (7)
DC component
∗ R, G, B input signal voltage for gray raster mode is given by
Vsig = 7.0 ± V50 [V]
where: V50 is the signal amplitude which gives 50% of
transmittance in V-T curve.
8. Image Retention Time
Image retention time is given by the following procedures.
Apply a monoscope signal to the LCD panel for 60 minutes and then change this signal to the gray scale of
Vsig = 7.0 ± VAC [V] (VAC: 3 to 4V) so as to give the maximum image retention. Hold input signal VAC. The
time for the residual image to disappear gives the image retention time.
∗ Monoscope signal conditions
Vsig = 7.0 ± 4.5 or 7.0 ± 2.0 [V]
(shown in the right figure)
Vcom = 6.6V
Black level
4.5V
White level
2.0V
7.0V
2.0V
4.5V
0V
Vsig waveform
– 14 –
LCX020BK
Example of Back Light Spectrum (Reference)
Spectral distribution data
5.000E – 01
A.U.
0.000E + 00
300.00
800.00
Wavelength [nm]
– 15 –
G1
G1
G1
G1
G1
G1
G1
G1
G1
G1
R1
R1
R1
R1
R1
R1
R1
R1
R1
– 16 –
R1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
Gate SW
R6
R6
R6
R6
R6
R6
R6
R6
R6
R6
G6
G6
G6
G6
G6
G6
G6
G6
G6
G6
B6
B6
B6
B6
B6
B6
B6
B6
B6
B6
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
G1
G1
G1
G1
G1
G1
G1
G1
G1
G1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
Gate SW
R6
R6
R6
R6
R6
R6
R6
R6
R6
R6
G6
G6
G6
G6
G6
G6
G6
G6
G6
G6
B6
B6
B6
B6
B6
B6
B6
B6
B6
B6
G1
G1
G1
G1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
Photoshielding
G1
G1
G1
G1
G1
G1
48 dots
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R2
R2
R2
R2
R2
R2
R2
R2
R2
R2
G2
G2
G2
G2
G2
G2
G2
G2
G2
G2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
R3
R3
R3
R3
R3
R3
R3
R3
R3
R3
G3
G3
G3
G3
G3
G3
G3
G3
G3
G3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
Gate SW
R4
R4
R4
R4
R4
R4
R4
R4
R4
R4
G4
G4
G4
G4
G4
G4
G4
G4
G4
G4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
R5
R5
R5
R5
R5
R5
R5
R5
R5
R5
G5
G5
G5
G5
G5
G5
G5
G5
G5
G5
R6
R6
R6
B5
B5
B5
B5
B5
B5
G6
G6
G6
G6
G6
G6
G6
G6
G6
G6
B6
B6
B6
B6
B6
B6
B6
B6
B6
B6
G1
G1
G1
G1
G1
G1
R1
R1
R1
R1
R1
R1
G1
R1
G1
G1
R1
R1
G1
R1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
R2
R2
R2
R2
R2
R2
R2
R2
R2
R2
2592 dots
2496 dots (effective 14.23mm)
R6
R6
R6
R6
R6
R6
Active
B5 area
R6
B5
B5
B5
G2
G2
G2
G2
G2
G2
G2
G2
G2
G2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
R3
R3
R3
R3
R3
R3
R3
R3
R3
R3
G3
G3
G3
G3
G3
G3
G3
G3
G3
G3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
Gate SW
R4
R4
R4
R4
R4
R4
R4
R4
R4
R4
G4
G4
G4
G4
G4
G4
G4
G4
G4
G4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
R5
R5
R5
R5
R5
R5
R5
R5
R5
R5
G5
G5
G5
G5
G5
G5
G5
G5
G5
G5
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
R6
R6
R6
R6
R6
R6
R6
R6
R6
R6
G6
G6
G6
G6
G6
G6
G6
G6
G6
G6
G1
G1
G1
G1
G1
G1
R1
R1
R1
R1
R1
R1
G1
R1
G1
G1
R1
R1
G1
R1
48 dots
B6
B6
B6
B6
B6
B6
B6
B6
B6
B6
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
R6
R6
R6
R6
R6
R6
R6
R6
R6
R6
G6
G6
G6
G6
G6
G6
G6
G6
G6
G6
Gate SW
B6
B6
B6
B6
B6
B6
B6
B6
B6
B6
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
G1
G1
G1
G1
G1
G1
G1
G1
G1
G1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
R6
R6
R6
R6
R6
R6
R6
R6
R6
R6
G6
G6
G6
G6
G6
G6
G6
G6
G6
G6
Gate SW
A
B6
B6
B6
B6
B6
B6
B6
B6
B6
B6
2 dots
624 dots (effective 10.61mm)
2 dots
1. Dot Arrangement
RGB dots are arranged in a stripe pattern. The shaded area is used for the dark border around the display.
LCX020BK
628 dots
LCX020BK
2. LCD Panel Operations
[Description of basic operations]
• A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse
to every 624 gate lines sequentially in every single horizontal scanning period. (in Macintosh16 mode)
• A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuits,
applies selected pulses to every 2496 signal electrodes sequentially in a single horizontal scanning period.
These pulses are used to supply the sampled video signal to the row signal lines.
• Vertical and horizontal shift registers address one pixel, and then Thin Film Transistors (TFTs; two TFTs for
one dot) turn on to apply a video signal to the dot. The same procedures lead to the entire 2496 × 832 dots to
display a picture in a single vertical scanning period.
• The data and video signals shall be input with polarity-inverted system in every horizontal cycle.
[Description of operating mode]
The LCD panel can change the angle of view by displaying a black frame to support various signal systems.
The angle of view is switched by MODE1, 2 and 3. However, the picture center does not change. The angle of
view mode settings are shown below.
MODE1
MODE2
MODE3
Display mode
L
L
L
Macintosh16: 832 × 624
L
L
H
SVGA: 800 × 600
L
H
L
PAL: 762 × 572
L
H
H
VGA/NTSC: 640 × 480
H
L
L
PC98: 640 × 400
H
L
H
WIDE: 832 × 480
The LCD panel has the following functions to easily apply to various uses, as well as various signal systems.
• Right/left inverse mode
• Up/down inverse mode
These modes are controlled by two signals (RGT and DWN). The right/left and up/down mode settings are
shown in the tables below.
RGT
Mode
DWN
Mode
H
Right scan
H
Down scan
L
Left scan
L
Up scan
Right/left and up/down mean the direction when the Pin 1 marking is located at the right side with the pin block
facing upward.
Since the display area is located in the center of the panel in each mode, the start pulse, clock phase and
polarity for both the H and V systems must be varied. The phase relationship between the start pulse and the
clock for each mode is shown on the following pages.
– 17 –
LCX020BK
(1) Vertical direction display cycle
(1.1) Macintosh 16
VD
VST (DWN = H)
VST (DWN = L)
VCK
1
2
3
621 622 623 624
4
Vertical display cycle 624H
(1.2) SVGA
VD
VST (DWN = H)
VST (DWN = L)
VCK
1
2
3
597 598 599 600
4
Vertical display cycle 600H
(1.3) PAL
VD
VST (DWN = H)
VST (DWN = L)
1
VCK
2
3
4
569 570 571 572
Vertical display cycle 572H
(1.4) VGA/NTSC, WIDE
VD
VST (DWN = H)
VST (DWN = L)
VCK
1
2
3
4
477 478 479 480
Vertical display cycle 480H
(1.5) PC98
VD
VST (DWN = H)
VST (DWN = L)
VCK
1
2
3
4
397 398 399 400
Vertical display cycle 400H
– 18 –
LCX020BK
(2) Horizontal direction display cycle
(2.1.1) Macintosh 16, WIDE, RGT = H
HD
HST
1
HCK1
2
3
4
137 138 139 140
HCK2
Horizontal display cycle
(2.1.2) Macintosh 16, WIDE, RGT = L
HD
HST
1
HCK1
2
3
4
137 138 139 140
HCK2
Horizontal display cycle
(2.2.1) SVGA, RGT = H
HD
HST
HCK1
1
2
3
HCK2
4
131 132 133 134
Horizontal display cycle
(2.2.2) SVGA, RGT = L
HD
HST
HCK1
HCK2
1
2
3
4
131 132 133 134
Horizontal display cycle
– 19 –
LCX020BK
(2.3.1) PAL, RGT = H
HD
HST
HCK1
1
2
3
HCK2
4
125 126 127 128
Horizontal display cycle
(2.3.2) PAL, RGT = L
HD
HST
HCK1
1
2
3
HCK2
4
125 126 127 128
Horizontal display cycle
(2.4.1) VGA/NTSC/PC98, RGT = H
HD
HST
HCK1
1
2
3
HCK2
4
105 106 107 108
Horizontal display cycle
(2.4.2) VGA/NTSC/PC98, RGT = L
HD
HST
HCK1
HCK2
1
2
3
4
105 106 107 108
Horizontal display cycle
– 20 –
LCX020BK
3. 18-dot Simultaneous Sampling
The horizontal shift register performs SIGR1 to SIGR6, SIGG1 to SIGG6 and SIGB1 to SIGB6 signal sampling
simultaneously, which requires phase matching between each signal to prevent the horizontal resolution from
deteriorating. Phase matching by an external signal delaying circuit is needed before applying video signals to
the LCD panel.
SIGR1, SIGG1, SIGB1
SIGR2, SIGG2, SIGB2
S/H
CK1
S/H
S/H
SIGR1, SIGG1, SIGB1
S/H
SIGR2, SIGG2, SIGB2
S/H
SIGR3, SIGG3, SIGB3
S/H
SIGR4, SIGG4, SIGB4
S/H
SIGR5, SIGG5, SIGB5
S/H
SIGR6, SIGG6, SIGB6
CK2
SIGR3, SIGG3, SIGB3
SIGR4, SIGG4, SIGB4
S/H
CK3
S/H
CK4
SIGR5, SIGG5, SIGB5
SIGR6, SIGG6, SIGB6
S/H
CK5
CK6
<Phase relationship of delaying sample-and-hold pulses> (right-direction scanning)
HCKn
CK1
CK2
CK3
CK4
CK5
CK6
– 21 –
LCX020BK
The block diagram of the delaying procedure using the sample-and-hold method is as follows. The following
phase relationship diagram indicates the phase setting for right-direction scanning (RGT = High level). For leftdirection scanning (RGT = Low level), the phase settings should be inverted for the SIGR1 to SIGR6, SIGG1 to
SIGG6 and SIGB1 to SIGB6 signals.
LCX020BK
Display System Block Diagram
An example display system configuration is shown below.
R
CXA2112R
R
G
G
CXA2111R
CXA2112R
LCX020BK
B
B
CXA2112R
HSYNC
PLL
MCK
FRP
CXD3500R
TIMING PULSE
VSYNC
– 22 –
LCX020BK
Notes on Handling
(1) Static charge prevention
Be sure to take the following protective measures. TFT-LCD panels are easily damaged by static charges.
a) Use non-chargeable gloves, or simply use bare hands.
b) Use an earth-band when handling.
c) Do not touch any electrodes of a panel.
d) Wear non-chargeable clothes and conductive shoes.
e) Install conductive mats on the working floor and working table.
f) Keep panels away from any charged materials.
g) Use ionized air to discharge the panels.
(2) Protection from dust and dust
a) Operate in a clean environment.
b) When delivered, panel surface (Polarizer) is covered by a protective sheet. Peel off the protective sheet
carefully so as not to damage the panel.
c) Do not touch the polarizer surface. The surface is easily scratched. When cleaning, use a clean-room
wiper with isopropyl alcohol. Be careful not to leave a stain on the surface.
d) Use ionized air to blow dust off the polarizer.
(3) Other handling precautions
a) Do not twist or bend the flexible PC board especially at the connecting region because the board is
easily deformed.
b) Do not drop the panel.
c) Do not twist or bend the panel or panel frame.
d) Keep the panel away from heat sources.
e) Do not dampen the panel with water or other solvents.
f) Avoid storing or using the panel at a high temperature or high humidity, which may result in panel
damages.
– 23 –
LCX020BK
Package Outline
Unit: mm
18.0 ± 0.3
Thickness of the connector
12.0 ± 0.05
0.2 ± 0.03
2
0.3 ± 0.3
2.761 ± 0.1
17.6 ± 0.3
1.075 ± 0.3
19.65 ± 0.15
0.05 ± 0.3
47.75 ± 0.9
3
Incident
light
4
4
Reinforcing material 1.5 ± 1.0
19.75 ± 0.15
18.25 ± 0.15
5.0 ± 0.3
(14.227)
0.05 ± 0.3
(10.608)
9±3
6±3
Active Area
14.0 ± 0.3
Polarizing Axis
0.3 ± 0.3
1.754 ± 0.1
1
(26.0)
electrode
0.8 ± 0.1
1.9 ± 0.3
2.33 ± 0.4
19.75 ± 0.15
P 0.6 ± 0.02 × 19 = 11.4 ± 0.03
P 0.6 ± 0.02 × 18 = 10.8 ± 0.03
0.3 ± 0.07
0.6 ± 0.07
No
Description
1
F P C
2
Reinforcing board
3
Reinforcing material
4
Polarizing film
PIN 39
PIN1
weight 2g
electrode (enlarged)
– 24 –