LCX024AK
1.4cm (0.55-inch) NTSC/PAL Color LCD Panel
For the availability of this product, please contact the sales office.
Description
The LCX024AK is a 1.4cm diagonal active matrix
TFT-LCD panel addressed by polycrystalline silicon
super thin film transistors with built-in peripheral
driving circuit. This panel provides full-color
representation in NTSC/PAL mode. RGB dots are
arranged in a delta pattern featuring high picture
quality of no fixed color patterns, which is inherent in
vertical stripes and mosaic pattern arrangements.
Features
• The number of active dots: 113,578 (0.55-inch; 1.397cm in diagonal)
• Horizontal resolution: 260 TV lines
• High optical transmittance: 3.4% (typ.)
• High contrast ratio with normally white mode: 270 (typ.)
• Built-in H and V drivers (built-in input level conversion circuit, TTL drive possible)
• High quality picture representation with RGB delta arranged color filters
• Full-color representation
• NTSC/PAL compatible
• Right/left inverse display function
• 4:3 and 16:9 aspect switching function
Element Structure
• Dots
Total dots : 537 (H) × 222 (V) = 119,214
Active dots: 521 (H) × 218 (V) = 113,578
• Built-in peripheral driver using polycrystalline silicon super thin film transistors.
Applications
• Viewfinders
• Super compact liquid crystal monitors etc.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E97729C8X-PS
LCX024AK
VDD
VSS
VST
VCK
(NC)
EN
CLR
RGT
HST
HCK2
HCK1
BLK
BLUE
RED
GREEN
COM
Block Diagram
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
H Level
Conversion
Circuit
H Shift Register
V Shift Register
V Level
Conversion
Circuit
CS
LC
COM
Pad
–2–
LCX024AK
Absolute Maximum Ratings (VSS = 0V)
• H and V driver supply voltages
VDD
• H driver input pin voltage
HST, HCK1, HCK2
RGT
• V driver input pin voltage
VST, VCK
CLR, EN, BLK
• Video signal input pin voltage
GREEN, RED, BLUE
• Operating temperature
Topr
• Storage temperature
Tstg
–1.0 to +17
–1.0 to +17
V
V
–1.0 to +17
V
–1.0 to +15
–10 to +70
–30 to +85
V
°C
°C
Operating Conditions (VSS = 0V)
Supply voltage
VDD
11.4 to 14.0
V
Input pulse voltage (Vp-p of all input pins except video signal input pins)
Vin
2.6V (more than)
Pin Description
Pin
No.
Symbol
Pin
No.
Description
Symbol
Description
1
COM
Common voltage of panel
9
RGT
Drive direction pulse for H shift
register (H: normal, L: reverse)
2
GREEN
Video signal (G) to panel
10
CLR
Improvement pulse for
uniformity
3
RED
Video signal (R) to panel
11
EN
Enable pulse for gate selection
4
BLUE
Video signal (B) to panel
(12)
(NC)
Not connected
5
BLK
Top/bottom block display pulse
13
VCK
Clock pulse for V shift register
drive
6
HCK1
Clock pulse for H shift register
drive
14
VST
Start pulse for V shift register
drive
7
HCK2
Clock pulse for H shift register
drive
15
Vss
GND (H, V drivers)
8
HST
Start pulse for H shift register
drive
16
VDD
Power supply for H and V drivers
–3–
LCX024AK
Input Equivalent Circuit
To prevent static charges, protective diodes are provided for each pin except the power supply. In addition,
protective resistors are added to all pins except video signal input. All pins are connected to Vss with a high
resistance of 1MΩ (typ.). The equivalent circuit of each input pin is shown below: (The resistor value: typ.)
(1) Video signal input
From H driver
VDD
Input
1MΩ
Signal line
(2) HCK1, HCK2
VDD
250Ω
250Ω
HCK1
250Ω
250Ω
1MΩ
1MΩ
HCK2
Level conversion
circuit (2-phase
input)
(3) HST
VDD
250Ω
250Ω
Level conversion
circuit (singlephase input)
2.5kΩ
Level conversion
circuit (singlephase input)
2.5kΩ
Level conversion
circuit (singlephase input)
Input
1MΩ
(4) RGT, VST, CLR, EN, VCK
VDD
2.5kΩ
Input
1MΩ
(5) BLK
VDD
2.5kΩ
Input
28kΩ
1MΩ
(6) COM
VDD
Input
1MΩ
–4–
LC
LCX024AK
Level Conversion Circuit
The LCX024AK has a built-in level conversion circuit in the clock input unit located inside the panel. The circuit
voltage is stepped up to VDD inside the panel. This level conversion circuit meets the specifications of a 3.0V
power supply of the externally-driven IC.
(For a single-phase input unit)
An example of the I/O voltage characteristics of a
level conversion circuit is shown in the figure to the
right. The input voltage value that becomes half the
output voltage (after voltage conversion) is defined
as Vth.
The Vth value varies depending on the VDD voltage.
The Vth values under standard conditions are
indicated in the table below. (HST, VST, EN, CLR,
RGT, VCK and BLK in the case of a single-phase input)
Output voltage (inside panel)
1. I/O characteristics of level conversion circuit
VDD
Example of single-phase
I/O characteristics
VDD
2
Vth
Input voltage [V]
VDD = 12.0V
Vth voltage of circuit
Symbol
Min.
Typ.
Max.
Unit
Vth
0.35
1.50
2.60
V
(For a differential input unit)
An example of I/O voltage characteristics of a level
conversion circuit for a differential input is shown in
the figure to the right. Although the characteristics,
including those of the Vth voltage, are basically the
same as those for a single-phased input, the twophased input phase is defined. (Refer to clock
timing conditions.)
Output voltage (inside panel)
Item
VDD
Example of differential I/O
characteristics
VDD
2
Vth
Input voltage [V]
2. Current characteristics at the input pin of level conversion circuit
VDD
A slight pull-in current is generated at the input pin
of the level conversion circuit. (The equivalent
circuit is shown to the right.) The current volume
increases as the voltage at the input pin decreases,
and is maximized when the pin is grounded. (Refer
to electrical characteristics.)
0
Input pin voltage [V]
10
output
Input pin current
0
HCK1
input
HCK2
input
Max. value
Level conversion equivalent circuit
Pull-in current characteristics at the input pin
–5–
LCX024AK
Input Signals
1. Input signal voltage conditions (VSS = 0V, VDD = 11.4 to 14V)
Item
Symbol
Min.
Typ.
Max.
Unit
H driver input voltage
(HST, HCK1, HCK2, RGT)
(Low)
VHIL
–0.35
0.0
0.35
V
(High)
VHIH
2.6
5.0
5.5
V
V driver input voltage
(VST, VCK1, VCK2, CLR, EN)
(Low)
VVIL
–0.35
0.0
0.35
V
(High)
VVIH
2.6
5.0
5.5
V
Video signal center voltage
VVC
5.8
6.0
6.2
V
Common voltage of panel
VCOM
Symbol
Item
VVC – 0.45 VVC – 0.3 VVC – 0.15
Min.
Video signal input range
Vsig
VSS + 1.3
Video signal input white level
VsigL
0.5
Typ.
Max.
Unit
VDD – 1.8
V
V
Note) Video signal shall be symmetrical to VVC.
Supplement) Video signal input range is set within the range shown below for VDD and VSS.
Also, video signal white level is defined for VVC as shown below.
VDD
VDD – 1.8
VsigL
White level
VVC
VsigL
VSS + 1.3
VSS
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
–6–
V
Video signal input range
Max. VDD – 1.8 [V]
Min. VSS + 1.3 [V]
LCX024AK
2. Clock timing conditions (Ta = 25°C, Input voltage = 3.0V, VDD = 12.0V)
Item
HST
HCK
CLR
VST
VCK
EN
BLK∗3
Symbol
Min.
Typ.
Max.
Hst rise time
trHst
30
Hst fall time
tfHst
30
Hst data set-up time
tdHst
–170
135
170
Hst data hold time
Hckn∗2 rise time
thHst
–455
–135
–50
trHckn
30
Hckn∗2 fall time
tfHckn
30
Hck1 fall to Hck2 rise time
to1Hck
–15
0
15
Hck1 rise to Hck2 fall time
to2Hck
–15
0
15
Clr rise time
trClr
100
Clr fall time
tfClr
100
Clr pulse width
twClr
3400
3500
3600
Clr fall to Hst rise time
toHst
1100
1200
1300
Vst rise time
trVst
100
Vst fall time
tfVst
100
Vst data set-up time
tdVst
–50
32
50
Vst data hold time
thVst
–50
–32
–20
Vck rise time
trVck
100
Vck fall time
tfVck
100
En rise time
trEn
100
En fall time
tfEn
100
Vck fall to En fall time
tdVck2
–100
0
100
Vck rise to En rise time
tdVck1
–100
0
100
BLK rise time
trBlk
100
BLK fall time
tfBlk
100
BLK pulse width
twBlk
BLK fall to CLR fall time
toClr
1.0
600
∗2 Hckn means Hck1, Hck2. (fHckn = 1.84MHz, fVckn = 7.865kHz)
∗3 BLK pulse is used only for 16:9 mode. For 4:3 mode, connect to VSS.
–7–
700
Unit
ns
µs
ns
ms
800
ns
LCX024AK
<Horizontal Shift Register Driving Waveform>
Item
Hst rise time
Symbol
Waveform
90%
trHst
HST
Hst fall time
HST
Conditions
90%
10%
tfHst
10%
trHst
tfHst
∗4
Hst data set-up time
tdHst
50%
50%
HCKn∗2
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
HST
HCK1
50%
Hst data hold time
50%
thHst
tdHst
Hckn∗2 rise time
Hckn∗2 fall time
Hck1 fall to Hck2 rise
time
trHckn
∗2
10%
trHckn
∗4
50%
tfHckn
50%
HCK1
50%
Hck1 rise to Hck2 fall
time
to2Hck
Clr rise time
trClr
tdHst = 135ns
thHst = –135ns
50%
HCK2
to2Hck
to1Hck
90%
90%
CLR
10%
Clr fall time
tfClr
Clr pulse width
twClr
Clr fall to Hst rise time
toHst
HCKn∗2
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
tdHst = 135ns
thHst = –135ns
90%
10%
tfHckn
to1Hck
thHst
90%
HCKn
HCK
HCKn∗2
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
10%
trClr
tfClr
HCKn∗2
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
CLR
HST
CLR
50%
50%
twClr
–8–
50%
toHst
HCKn∗2
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
LCX024AK
<Vertical Shift Register Driving Waveform>
Item
Symbol
Vst rise time
Waveform
90%
trVst
VST
Vst fall time
VST
Conditions
90%
10%
tfVst
VCK
duty cycle 50%
10%
trVst
tfVst
∗4
Vst data set-up time
50%
tdVst
50%
VST
50%
50%
VCK
duty cycle 50%
Vst data hold time
VCK
thVst
tdVst
Vck rise time
10%
VCK
VCK
tfVck
En rise time
trEn
90%
90%
trVck
Vck fall time
thVst
VCK
duty cycle 50%
tdVst = 32µs
thVst = –32µs
10%
trVck
90%
tfVck
10%
10%
90%
VCK
duty cycle 50%
to1Vck = 0ns
to2Vck = 0ns
EN
En fall time
tfEn
tfEn
EN
trEn
∗4
Vck rise to En rise time
50%
VCK
tdVck
50%
50%
Vck rise to En fall time
50%
EN
tdVck
tdVck
BLK rise time
tdVck
90%
trBlk
90%
10%
BLK fall time
tfBlk
BLK pulse width
twBlk
BLK fall to CLR fall
time
toClr
BLK
∗4 Definitions:
VCK
duty cycle 50%
to1Vck = 0ns
to2Vck = 0ns
10%
trBlk
∗4
50%
tfBlk
twBlk
50%
BLK
50%
CLR
The right-pointing arrow (
The left-pointing arrow (
The black dot at an arrow (
) means +.
) means –.
) indicates the start of measurement.
–9–
LCX024AK
Electrical Characteristics
1. Horizontal drivers
(Ta = 25°C, VDD = 12.0V, Input voltage = 3.0V)
Item
Input pin capacitance
Input pin current
Symbol
Min.
Typ.
Max.
Unit
Condition
HCKn
CHckn
5
10
pF
HST
CHst
5
10
pF
HCK1
IHck1
–500
–250
µA
HCK1 = GND
HCK2
IHck2
–500
–250
µA
HCK2 = GND
HST
IHst
–300
–100
µA
HST = GND
RGT
IRgt
–100
–25
µA
RGT = GND
Video signal input pin capacitance
Csig
35
45
pF
Typ.
Max.
Unit
2. Vertical drivers
Item
Input pin capacitance
Symbol
Min.
VCK
CVck
5
10
pF
VST
CVst
5
10
pF
VST
EN
CLR
VCK
BLK
IVst
IEn
IClr
IVck
IBlk
–100
–25
µA
3. Total power consumption of the panel
Item
Total power consumption of
the panel (NTSC)
Symbol
Min.
PWR
Typ.
Max.
Unit
30
50
mW
Max.
Unit
4. VCOM input resistance
Item
Symbol
Min.
Typ.
VCOM – Vss input resistance
Rcom
0.5
1
– 10 –
MΩ
Condition
VST, EN, CLR, VCK,
BLK = GND
LCX024AK
Electro-optical Characteristics
(Ta = 25°C, NTSC mode)
Symbol
Item
Contrast
ratio
VDD = 12.0V
Vsig = 6.0 ± 4.0V
VDD = 13.5V
Vsig = 6.0 ± 4.5V
60°C
CR4.060
25°C
CR4.025
60°C
CR4.560
25°C
CR4.525
R
G
B
V90
V-T
characteristics
V50
V10
Half tone color reproduction
range
ON time
Response time
OFF time
Flicker
Image retention time
1
T
Optical transmittance
Chromaticity
Measurement
method
2
Min
Typ.
Max.
70
200
—
70
200
—
80
270
—
80
270
—
2.6
3.4
—
X
Rx
0.560
0.630
0.670
Y
Ry
0.300
0.345
0.390
X
Gx
0.275
0.310
0.347
Y
Gy
0.541
0.595
0.650
X
Bx
0.120
0.148
0.187
Y
By
0.040
0.088
0.122
3
25°C
V90-25
1.1
1.6
2.2
60°C
V90-60
1.0
1.5
2.1
25°C
V50-25
1.5
2.0
2.5
1.4
1.8
2.4
4
60°C
V50-60
25°C
V10-25
2.2
2.5
3.2
60°C
V10-60
2.1
2.4
3.1
R vs. G
V50RG
—
–0.10
–0.25
B vs. G
V50BG
—
0.10
0.45
0°C
ton0
—
30
100
25°C
ton25
—
8
40
—
65
150
—
20
60
5
6
Unit
—
%
CIE
standards
V
V
ms
0°C
toff0
25°C
toff25
60°C
F
7
—
—
–40
dB
YT60
8
—
—
20
s
60 min.
– 11 –
LCX024AK
<Electro-optical Characteristics Measurement>
Basic measurement conditions
(1) Driving voltage
VDD = 13.5V
VVC = 6.0V, VCOM = 5.7V
(2) Measurement temperature
25°C unless otherwise specified.
(3) Measurement point
One point in the center of screen unless otherwise specified.
(4) Measurement systems
Two types of measurement system are used as shown below.
(5) RGB input signal voltage (Vsig)
Vsig = 6.0 ± VAC [V] (VAC: signal amplitude)
∗ Measurement system I
Back Light
3.5mm
Measurement
Equipment
Luminance
Meter
Back light: color temperature 6500K, +0.004uV (25°C)
∗ Back light spectrum (reference) is listed on another page.
LCD panel
∗ Measurement system II
Optical fiber
Light receptor lens
Drive Circuit
Light Detector
Measurement
Equipment
LCD panel
Light Source
1. Contrast Ratio
Contrast Ratio (CR4.0) is given by the following formula (1).
CR4.0 =
L4.0 (White)
...(1)
L4.0 (Black)
L4.0 (White): Surface luminance of the TFT-LCD panel at VDD = 12.0V, VVC = 6.0V, VCOM = 5.7V and the
RGB signal amplitude VAC = 0.5V.
L4.0 (Black): Surface luminance of the panel at VAC = 4.0V.
Contrast Ratio (CR4.5) is given by the following formula (2).
CR4.5 =
L4.5 (White)
...(2)
L4.5 (Black)
L4.5 (White): Surface luminance of the TFT-LCD panel at the RGB signal amplitude VAC = 0.5V.
L4.5 (Black): Surface luminance of the panel at VAC = 4.5V.
The above luminosities are measured by System I.
– 12 –
LCX024AK
2. Optical Transmittance
Optical Transmittance (T) is given by the following formula (2).
T=
L (White)
× 100 [%] ...(2)
Luminance of Back Light
L (White) is the same expression as defined in the "Contrast Ratio" section.
3. Chromaticity
Chromaticity of the panels are measured by System I. Raster modes of each color are defined by the
representations at the input signal amplitude conditions shown in the table below. System I uses
Chromaticity of x and y on the CIE standards here.
Raster
Signal amplitudes (VAC) supplied to each input
R input
G input
B input
R
0.5
4.5
4.5
G
4.5
0.5
4.5
B
4.5
4.5
0.5
4. V-T Characteristics
V-T characteristics, the relationship between signal
amplitude and the transmittance of the panels, are
measured by System II. V90, V50 and V10 correspond to
the each voltage which defines 90%, 50% and 10% of
transmittance respectively. (Transmittance at VAC =
0.5V is 100%.)
Transmittance [%]
(Unit : V)
90
50
10
V90
VAC – Signal amplitude [V]
100
Transmittance [%]
5. Half Tone Color Reproduction Range
Half tone color reproduction range of the LCD panels is
characterized by the differences between the V-T
characteristics of R, G and B. The differences of these
V-T characteristics are measured by System II. System
II defines signal voltages of each R, G, B raster modes
which correspond to 50% of transmittance, V50R, V50G
and V50B respectively. V50RG and V50BG, the voltage
differences between V50R and V50G, V50B and V50G, are
simply given by the following formulas (3) and (4)
respectively.
V50 V10
V50RG
V50BG
50
G raster
R raster
B raster
0
V50R V50B
V50G
V50RG = V50R – V50G ...(3)
V50BG = V50B – V50G ...(4)
VAC – Signal amplitude [V]
– 13 –
LCX024AK
6. Response Time
Response time ton and toff are defined by
the formulas (5) and (6) respectively.
Input signal voltage (waveform applied to the measured pixels)
4.5V
ton = t1 – tON ...(5)
toff = t2 – tOFF ...(6)
t1: time which gives 10% transmittance of
the panel.
t2: time which gives 90% transmittance of
the panel.
0.5V
6.0V
0V
Optical transmittance output waveform
100%
90%
The relationships between t1, t2, tON and
tOFF are shown in the right figure.
10%
0%
tON
t1
ton
tOFF
t2
toff
7. Flicker
Flicker (F) is given by the formula (7). DC and AC (NTSC: 30Hz, rms, PAL: 25Hz, rms) components of the
panel output signal for gray raster∗ mode are measured by a DC voltmeter and a spectrum analyzer in
System II.
F (dB) = 20log
AC component
...(7)
{ DC
component }
∗ R, G, B input signal condition for gray raster mode
is given by Vsig = 6.0 ± V50 (V)
where: V50 is the signal amplitude which gives 50%
of transmittance in V-T characteristics.
8. Image Retention Time
Apply the monoscope signal to the LCD panel for 60 minutes and then change this signal to the gray scale
of Vsig = 6.0 ± VAC (VAC: 3 to 4V), judging by sight at VAC that hold the maximum image retention, measure
the time till the residual image becomes indistinct.
∗ Monoscope signal conditions:
Vsig = 6.0 ± 4.5 or 6 ± 2.0 (V)
(shown in the right figure)
VCOM = 5.7V
Black level
4.5V
White level
2.0V
6.0V
2.0V
4.5V
0V
Vsig waveform
– 14 –
LCX024AK
Example of Back Light Spectrum (Reference)
0.4
0.3
0.2
0.1
0
400
500
600
Wavelength 380 – 780 [nm]
– 15 –
700
LCX024AK
Description of Operation
1. Color Coding
Color filters are coded in a delta arrangement.
The shaded area is used for the dark border around the display.
Gate SW
Gate SW
Gate SW
Gate SW
Gate SW
Gate SW
Green is not
connected
for only final
stage.
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
2
G
B
B
R
G
B
3
R
B
B
G
B
G
B
B
G
R
G
R
B
Photo-shielding
G
B
B
G
R
R
B
G
G
R
B
B
G
R
R
B
G
G
R
B
R
B
G
R
G
B
G
R
B
R
G
R
B
G
B
R
B
G
R
G
B
G
R
B
R
G
R
B
G
B
R
B
G
R
G
R
Active area
G
B
R
R
R
G
R
B
G
B
R
B
G
R
G
R
B
G
G
B
G
R
B
R
B
G
R
R
G
R
B
G
B
G
R
B
B
R
B
G
R
G
R
B
G
G
B
G
R
B
R
B
G
R
R
G
R
B
G
B
G
R
B
R
B
G
B
R
G
B
R
G
R
G
B
R
R
521
G
B
R
G
B
R
13
537
– 16 –
G
222
G
G
218
R
2
B
LCX024AK
2. LCD Panel Operations
• A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse
to every 218 gate lines sequentially in every horizontal scanning period. A vertical shift register scans the
gate lines from the top to bottom of the panel.
• The selected pulse is delivered when the enable pin turns to High level. PAL mode images are displayed by
controlling the enable and VCK pin. The enable pin should be High when not in use.
• A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuits
applies selected pulses to every 521 signal electrodes sequentially in a single horizontal scanning period.
• Scanning direction of horizontal shift register can be switched with RGT pin. Scanning direction is left to right
for RGT pin at High level; and right to left for RGT pin at Low level. (These scanning directions are from a
front view.) Normally, set to High level.
• Vertical and horizontal drivers address one pixel and then turn on Thin Film Transistors (TFTs; two TFTs) to
apply a video signal to the dot. The same procedures lead to the entire 218 × 521 dots to display a picture in
a single vertical scanning period.
• Pixel dots are arranged in a delta pattern, where sets of RGB pixels are positioned with 1.5-dot shifted
against adjacent horizontal line. 1.5-dot shift of a horizontal driver output pulse against horizontal
synchronized signal is required to apply a video signal to each dot properly. 1H reversed displaying mode is
required to apply video signal to the panel.
• The CLR pin is provided to eliminate the shading effect caused by the coupling of selected pulses. While
maintaining the CLR at High level, the VDD potential of gate output inverter drops to approximately 8.5V. This
pin shall be grounded when not in use.
• The video signal shall be input with polarity-inverted system in every horizontal cycle.
• Timing diagrams of the vertical and the horizontal right-direction scanning (RGT = High level) display cycle
are shown below:
(1) Vertical display cycle
VD
VST
Vertical display cycle 218H (13.84ms)
VCK
1
2
217
218
∗ VST is sampled at first for VCK.
(2) Horizontal display cycle (right scan)
HD
HST
175
HCK1
1
2
3
4
5
174
HCK2
Horizontal display cycle (47.3µs)
∗ HST is sampled at first for HCK1.
The horizontal display cycle consists of 521/3 = 174 clock pulses because of RGB simultaneous sampling.
∗ Refer to Description of Operation "3. RGB Simultaneous Sampling."
– 17 –
LCX024AK
3. RGB Simultaneous Sampling
Horizontal driver samples R, G and B signal simultaneously, which requires the phase matching between R,
G and B signals to prevent horizontal resolution from deteriorating. Thus phase matching between each
signal is required using an external signal delaying circuit before applying video signal to the LCD panel.
Two methods are applied for the delaying procedure: Sample and hold and Delay circuit. These two block
diagrams are as follows.
The LCX024AK has the right/left inverse function. The following phase relationship diagram indicates the
phase setting for the right scan (RGT = High level). For the left scan (RGT = Low level), the phase setting
shall be inverted between B and G signals.
B
S/H
S/H
CKB
CKG
R
G
S/H
S/H
CKR
CKG
S/H
AC Amp
4
BLUE
AC Amp
3
RED
AC Amp
2
GREEN
LCX024AK
(1) Sample and hold (right scan)
CKG
<Phase relationship of delaying sample-and-hold pulses> (right scan)
HCKn
CKB
CKR
CKG
B
R
Delay
Delay
AC Amp
4
BLUE
Delay
AC Amp
3
RED
AC Amp
2
GREEN
G
– 18 –
LCX024AK
(2) Delay circuit (right scan)
LCX024AK
Example of Color Filter Spectrum (Reference)
100
Color Filter Spectrum
R
80
G
B
Transmittance [%]
60
40
20
0
400
500
600
Wavelength [nm]
– 19 –
700
LCX024AK
Color Display System Block Diagram (1)
An example of dual-chip display system is shown below.
+12V
+5V
+12.0 or 13.5V
RED
Composite video
GREEN
Decoder/Driver
CXA1785AR
Y/C
BLUE
Y/color difference
SYNC
VCOM
FRP
+3V
LCD panel
NTSC/PAL
LCX024AK
HST
HCK1
HCK2
VST
BLK
TG
CXD2458AR
VCK
EN
CLR
(Refer to CXD2458AR data sheet.)
RGT
– 20 –
LCX024AK
Color Display System Block Diagram (2)
An example of single-chip display system is shown below.
+12V
+5V
+12.0 or +13.5V
RED
Composite video
GREEN
Y/C
BLUE
Y/color difference
VCOM
LCD panel
NTSC/PAL
LCX024AK
CXA2503AR
HST
HCK1
HCK2
VST
VCK
EN
CLR
(Refer to CXA2503AR data sheet.)
RGT
When the CXA2503AR is used, connect BLK (Pin 5) of the LCD panel to VSS or leave that pin open. The
LCX024AK specification conforms to the LCX005BK specification.
– 21 –
LCX024AK
Color Display System Block Diagram (3)
An example of dual-chip display system is shown below.
+12V
+5V
+12.0 or +13.5V
RED
Composite video
GREEN
Decoder/Driver
CXA1785AR
Y/C
BLUE
Y/color difference
SYNC
VCOM
FRP
+5V
LCD panel
NTSC/PAL
LCX024AK
HST
HCK1
HCK2
VST
TG
CXD2411AR
VCK
EN
CLR
(Refer to CXD2411AR data sheet.)
RGT
When the CXA1785AR and the CXD2411AR are used, connect BLK (Pin 5) of the LCD panel to VSS or leave
that pin open. The LCX024AK specification conforms to the LCX005BK specification.
– 22 –
LCX024AK
Notes on Handling
(1) Static charge prevention
Be sure to take following protective measures. TFT-LCD panels are easily damaged by static charge.
a) Use non-chargeable gloves, or simply use bare hands.
b) Use an earth-band when handling.
c) Do not touch any electrodes of a panel.
d) Wear non-chargeable clothes and conductive shoes.
e) Install conductive mat on the working floor and working table.
f) Keep panels away from any charged materials.
g) Use ionized air to discharge the panels.
(2) Protection from dust and dirt
a) Operate in clean environment.
b) When delivered, a surface of a panel (Polarizer) is covered by a protective sheet. Peel off the
protective sheet carefully not to damage the panel.
c) Do not touch the surface of a panel. The surface is easily scratched. When cleaning, use a clean-room
wiper with isopropyl alcohol. Be careful not to leave stain on the surface.
d) Use ionized air to blow off dust at a panel.
(3) Other handling precautions
a) Do not twist or bend the flexible PC board especially at the connecting region because the board is
easily deformed.
b) Do not drop a panel.
c) Do not twist or bend a panel or a panel frame.
d) Keep a panel away from heat source.
e) Do not dampen a panel with water or other solvents.
f) Avoid to store or to use a panel in a high temperature or in a high humidity, which may result in panel
damages.
– 23 –
LCX024AK
Package Outline
Unit: mm
Thickness of the connector 0.3 ± 0.05
14.0 ± 0.3
8.5 ± 0.05
1.2 ± 0.3
4
1
S-C K1
5
1.0
4-R
Active Area
34.8 ± 0.8
25.5 ± 0.8
17.8 ± 0.15
3
6
Incident
light
Active Area
7.7 ± 0.25
(11.2)
(8.3)
6
2
9.0 ± 0.25
2.7 ± 0.15
18.0 ± 0.15
1
0.5 ± 0.1
PIN 16
PIN 1
4.0 ± 0.5
+ 0.04
0.35 – 0.03
3.0 ± 0.3
× 15 = 7.5 ± 0.03
0.5 ± 0.15
P 0.5 ± 0.02
No
Description
F P C
2
Molding material
3
Outside frame
4
Reinforcing board
5 Reinforcing material
6
Polarizing film
weight 1.3g
electrode (enlarged)
– 24 –