LCX018AK
1.8cm (0.7-inch) NTSC/PAL/WID Color LCD Panel
For the availability of this product, please contact the sales office.
Description
The LCX018AK is a 1.8cm diagonal active matrix
TFT-LCD panel addressed by the polycrystalline
silicon super thin film transistors with built-in
peripheral driving circuit. This panel provides fullcolor representation in NTSC/PAL/WID mode. RGB
dots are arranged in a delta pattern featuring high
picture quality of no fixed color patterns, which is
inherent in vertical stripes and mosaic pattern
arrangements.
Features
• Number of active dots: 240,000 (0.7-inch; 1.8cm in diagonal)
• Horizontal resolution: 400 TV lines
• High optical transmittance: 4.4% (typ.)
• High contrast ratio with normally white mode: 200 (typ.)
• Built-in H and V driving circuit (built-in input level conversion circuit, TTL drive possible)
• High quality picture representation with RGB delta arranged color filters
• Full-color representation
• NTSC/PAL/WID compatible
• Up/down and/or right/left inverse display function
• Side-black function
• 16:9 and 4:3 aspect switching function
Element Structure
• Dots
16:9 display: 1068.5 (H) × 225 (V) = 240,412
4:3 display: 803.5 (H) × 225 (V) = 180,787
• Built-in peripheral driving circuit using the polycrystalline silicon super thin film transistors.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E98521-PS
Side-Black
Control Circuit
V Shift Register
(Bidirectional Scanning)
V Shift Register
(Bidirectional Scanning)
Up/Down and/or
Right/Left Inversion
4:3/16:9 Control Circuit
PSIG
HST
HCK1
HCK2
WID
RGT
VST
VCK1
VCK2
PCG
DWN
EN
HVDD
VVDD
VSS
SIG3
SIG2
SIG1
COM
LCX018AK
Block Diagram
2
9
10
11
7
8
16
15
14
18
17
13
6
19
12
5
4
3
1
Input Signal
Level Shifter
H Shift Register (Bidirectional Scanning)
COM
Pad
–2–
LCX018AK
Absolute Maximum Ratings (Vss = 0V)
• H driver supply voltage
HVDD
• V driver supply voltage
VVDD
• H driver input pin voltage
HST, HCK1, HCK2
RGT
• V driver input pin voltage
VST, VCK1, VCK2
CLR, EN
• Video signal input pin voltage GREEN, RED, BLUE
• Operating temperature
Topr
• Storage temperature
Tstg
–1.0 to +17
–1.0 to +17
–1.0 to +17
V
V
V
–1.0 to +17
V
–1.0 to +15
–10 to +70
–30 to +85
V
°C
°C
Operating Conditions (Vss = 0V)
• Supply voltage
HVDD
13.5 ± 0.5
V
VVDD
13.5 ± 0.5
V
• Input pulse voltage (Vp-p of all input pins except video signal input pins)
Vin
3.0V or more
Pin Description
Pin
No.
Description
Symbol
1
COM
Common voltage of panel
2
PSIG
Improvement signal for uniformity
3
SIG1
Video signal (Green) to panel
4
SIG2
Video signal (Red) to panel
5
SIG3
Video signal (Blue) to panel
6
HVDD
Power supply for H driver
7
WID
Aspect-ratio switching (H: 16:9, L: 4:3)
8
RGT
Drive direction pulse for H shift register (H: normal, L: reverse)
9
HST
Start pulse for H shift register drive
10
HCK1
Clock pulse for H shift register drive
11
HCK2
Clock pulse for H shift register drive
12
VSS
GND (H, V drivers)
13
EN
Enable pulse for gate selection
14
VCK2
Clock pulse for V shift register drive
15
VCK1
Clock pulse for V shift register drive
16
VST
Start pulse for V shift register drive
17
DWN
Drive direction pulse for V shift register (H: normal, L: reverse)
18
PCG
Improvement pulse for uniformity
19
VVDD
Power supply for V driver
20
SOUT
H, V shift register drive confirmation
–3–
LCX018AK
Input Equivalent Circuit
To prevent static charges, protective diodes are provided for each pin except the power supply. In addition,
protective resistors are added to all pins except video signal input. The equivalent circuit of each input pin is
shown below. (The resistor value: typ.)
(1) SIG1, SIG2, SIG3, SID
HVDD
From H driver
Input
1MΩ
Signal line
(2) HCK1, HCK2
VVDD
250Ω
250Ω
HCK1
1MΩ
250Ω
Level conversion circuit
(2-phase input)
250Ω
1MΩ
HCK2
(3) HST
HVDD
250Ω
250Ω
Input
Level conversion circuit
(single-phase input)
1MΩ
(4) RGT, WID
HVDD
2.5kΩ
2.5kΩ
Input
Level conversion circuit
(single-phase input)
1MΩ
(5) VCK1, VCK2
VVDD
250Ω
250Ω
VCK1
1MΩ
250Ω
Level conversion circuit
(2-phase input)
250Ω
1MΩ
VCK2
(6) VST, DWN, EN
VVDD
2.5kΩ
2.5kΩ
Input
Level conversion circuit
(single-phase input)
1MΩ
(7) PCG
VVDD
250Ω
250Ω
Input
Level conversion circuit
(single-phase input)
1MΩ
(8) COM
VVDD
Input
1MΩ
LC
–4–
LCX018AK
Input Signals
1.Input signal voltage conditions (Vss = 0V)
Symbol
Item
Min.
Typ.
Max.
Unit
H driver input voltage
(HST, HCK1, HCK2, RGT, WID)
(Low)
VHIL
–0.30
0.0
0.30
V
(High)
VHIH
2.7
3
5.5
V
V driver input voltage
(VST, VCK1, VCK2, DWN, PCG, EN)
(Low)
VVIL
–0.30
0.0
0.3
V
(High)
VVIH
2.7
3
5.5
V
Video signal center voltage
VVC
5.8
6.0
6.2
V
Common voltage of panel
VCOM
Item
Video signal input range∗1
VVC – 0.4 VVC – 0.25 VVC – 0.1
Symbol
(VDD = 12.0V)
Vsig
Uniformity improvement signal PSIG input voltage Vpsig
Video signal and uniformity improvement signal
input white level
Min.
Max.
Unit
VVC – 4.0
VVC + 4.0
V
VVC – 4.0
VVC + 4.0
V
VsigL
Typ.
V
V
0.5
∗1 Video input signal should be symmetrical to VVC.
Supplement) Video signal and uniformity improvement signal input range are set within the range shown
below for VDD and VSS.
Also, video signal white level is defined for VVC as shown below.
VDD
VDD – 1.8
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
VsigL White level
VVC
VsigL
VDD + 1.3
VSS
–5–
Video signal input range
Max. VDD – 1.8 [V]
Min. VSS + 1.3 [V]
LCX018AK
2. Clock timing conditions (Ta = 25°C)
Item
HST
HCK
VST
VCK
ENB
PCG
Symbol
Min.
Typ.
Max.
Hst rise time
trHst
30
Hst fall time
tfHst
30
Hst data set-up time
tdHst
35
45
55
Hst data hold time
Hckn∗2 rise time
thHst
80
90
100
trHckn
30
Hckn∗2 fall time
tfHckn
30
Hck1 fall to Hck2 rise time
to1Hck
–15
0
15
Hck1 rise to Hck2 fall time
to2Hck
–15
0
15
Vst rise time
trVst
100
Vst fall time
tfVst
100
Vst data set-up time
tdVst
–5.5
4.5
14.5
Vst data hold time
Vckn∗2 rise time
thVst
49
59
69
trVckn
100
Vckn∗2 fall time
tfVckn
100
Vck1 fall to Vck2 rise time
to1Vck
–20
0
20
Vck1 rise to Vck2 fall time
to2Vck
–20
0
20
Enb rise time
trEnb
—
—
100
Enb fall time
tfEnb
—
—
100
Vck rise/fall to Enb rise time
tdEnb
2150
2200
2250
Enb pulse width
twEnb
5950
6000
6050
Pcg rise time
trPcg
—
—
20
Pcg fall time
tfPcg
—
—
20
Pcg fall to Vck rise/fall time
toVck
–1050
–1000
–950
Pcg pulse width
twPcg
2450
2500
2550
∗2 Hckn and Vckn mean Hck1, Hck2 and Vck1, Vck2. (fHckn = 3.72MHz, fVckn = 7.81kHz)
–6–
Unit
ns
µs
ns
LCX018AK
<Horizontal Shift Register Driving Waveform>
Item
Hst rise time
Symbol
Waveform
trHst
90%
Hst
Hst fall time
Conditions
90%
10%
10%
tfHst
trHst
HST
Hst data set-up time
tdHst
50%
50%
Hck1
Hst data hold time
tfHst
50%
Hst
50%
thHst
tdHst
Hckn∗2 rise time
∗2
Hckn∗2 fall time
HCK
Hck1 fall to
Hck2 rise time
90%
10%
Hckn
tfHckn
to1Hck
10%
trHckn
∗3
50%
tfHckn
• Hckn∗2
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
tdHst = 60ns
thHst = –120ns
50%
Hck1
50%
Hck1 rise to
Hck2 fall time
• Hckn∗2
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
thHst
90%
trHckn
• Hckn∗2
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
50%
Hck2
to2Hck
to2Hck
–7–
to1Hck
• tdHst = 60ns
thHst = –120ns
LCX018AK
<Vertical Shift Register Driving Waveform>
Item
Vst rise time
Symbol
Waveform
90%
trVst
Vst
Vst fall time
Conditions
10%
tfVst
• Vckn∗2
duty cycle 50%
to1Vck = 0ns
to2Vck = 0ns
90%
10%
trVst
tfVst
∗3
VST
50%
Vst data set-up time
tdVst
Vst data hold time
thVst
Vst
50%
50%
50%
Vck1
tdVst
Vckn∗2 rise time
10%
tfVckn
trVckn
VCK
Vck1 fall to
Vck2 rise time
∗3
to1Vck
50%
tfVckn
50%
Vck1
50%
Vck1 rise to
Vck2 fall time
to2Vck
• tdVst = 32µs
thVst = –32µs
50%
Vck2
to2Vck
Enb rise time
• Vckn∗2
duty cycle 50%
to1Vck = 0ns
to2Vck = 0ns
tdVst = 32µs
thVst = –32µs
90%
10%
Vckn
Vckn∗2 fall time
thVst
90%
trVckn
90%
trEnb
to1Vck
10%
10%
90%
Enb
ENB
Enb fall time
tfEnb
Vck rise/fall to
Enb rise time
tdEnb
Enb pulse width
Pcg rise time
tfEn
trEn
Vck
50%
Enb
50%
∗4
twEnb
50%
twEnb
tdEnb
trPcg
Vck
PCG
• Vckn∗2
duty cycle 50%
to1Vck = 0ns
to2Vck = 0ns
Pcg fall time
tfPcg
Pcg fall to
Vck rise/fall time
toVck
Pcg
Pcg pulse width
twPcg
∗4
50%
50%
50%
twPcg
toVck
∗3 Definitions: The right-pointing arrow (
) means +.
The left-pointing arrow (
) means –.
The black dot at an arrow (
) indicates the start of measurement.
–8–
LCX018AK
Electrical Characteristics (Ta = 25°C, HVDD = 13.5V, VVDD = 13.5V)
1. Horizontal drivers
Item
Symbol
Typ.
Max.
Unit
CHckn
8
13
pF
Hst
CHst
8
13
pF
Hck1
IHck1
–450
–190
µA
Hck1 = GND
Hck2
IHck2
–900
–200
µA
Hck2 = GND
IRgt
–130
–25
µA
Hst, Wid, Rgt = GND
Input pin capacitance Hckn
Input pin current
Hst, Wid, Rgt
Min.
Condition
Video signal input pin
capacitance
Csig
150
200
pF
Current consumption
IH
3.5
6
mA
Typ.
Max.
Unit
CVckn
8
13
pF
Vst
CVst
8
13
pF
Vck1
IVck1
–450
–190
µA
Vck1 = GND
Vck2
IVck2
–900
–200
µA
Vck2 = GND
IVst,
IEn
–130
–25
µA
Vst, En, Dwn, Pcg = GND
mA
Vckn: Vck1, Vck2 (7.87kHz)
Hckn: Hck1, Hck2 (3.72MHz)
2. Vertical drivers
Item
Symbol
Input pin capacitance Vckn
Input pin current
Vst, En, Dwn, Pcg
Current consumption
Min.
IV
1.0
2.0
Condition
3. Total power consumption of the panel
Item
Total power consumption of the panel (NTSC)
Symbol
Min.
PWR
Typ.
Max.
Unit
60
120
mW
Max.
Unit
4. COM input resistance
Item
COM – Vss input resistance
Symbol
Min.
Typ.
Rcom
0.5
1
Symbol
Min.
Typ.
Max.
Unit
CPSIGon
—
7
10
nF
MΩ
5. Improvement signal for uniformity
Item
Improvement signal for uniformity
–9–
LCX018AK
Electro-optical Characteristics
(Ta = 25°C, NTSC mode)
Item
Symbol
Contrast ratio
25°C
CR25
60°C
CR60
Optical transmittance
G
B
V90
V-T
characteristics
1
2
T
R
Chromaticity
Measurement
method
V50
V10
Half tone color
reproduction range
ON time
Response time
OFF time
Flicker
Image retention time
Optimum Vcom voltage
Min.
Typ.
Max.
80
200
—
80
200
—
3.8
4.4
—
X
Rx
0.580
0.620
0.660
Y
Ry
0.300
0.340
0.380
X
Gx
0.250
0.290
0.330
Y
Gy
0.550
0.590
0.630
X
Bx
0.105
0.140
0.175
Y
By
0.070
0.110
0.150
3
Unit
—
%
CIE
standards
25°C
V90-25
1.1
1.5
2.2
60°C
V90-60
1.0
1.3
2.1
25°C
V50-25
1.5
2.0
2.5
60°C
V50-60
1.4
1.8
2.4
25°C
V10-25
2.2
2.7
3.2
60°C
V10-60
2.1
2.5
3.1
R vs. G
V50RG
—
–0.10
–0.25
B vs. G
V50BG
—
0.10
0.45
0°C
ton0
—
25
100
25°C
ton25
—
8
40
0°C
toff0
—
65
150
25°C
toff25
—
20
60
60°C
F
7
—
—
–40
dB
YT60
8
—
—
20
s
Vcomopt
9
5.60
5.75
5.90
V
60min.
4
5
6
– 10 –
V
V
ms
LCX018AK
<Electro-optical Characteristics Measurement>
Basic measurement conditions
(1) Driving voltage
HVDD = 13.5V, VVDD = 13.5V
VVC = 6.0V, Vcom = 5.75V
(2) Measurement temperature
25°C unless otherwise specified.
(3) Measurement point
One point in the center of screen unless otherwise specified.
(4) Measurement systems
Two types of measurement system are used as shown below.
(5) RGB input signal voltage (Vsig)
Vsig = 6 ± VAC [V]
(VAC: signal amplitude)
Back Light
∗ Measurement system I
Back
light
Luminance
Meter
3.5mm
Measurement
Equipment
Back light: color temperature 8500K, +0.004uV (25°C)
∗ Back light spectrum (reference) is listed on another page.
LCD panel
∗ Measurement system II
Optical fiber
Light receptor lens
Light Detector
Measurement
Equipment
LCD panel
Drive Circuit
Light
Source
1. Contrast Ratio
Contrast Ratio (CR) is given by the following formula (1).
CR =
L (White)
... (1)
L (Black)
L (White): Surface luminance of the TFT-LCD panel at the RGB signal amplitude VAC = 0.5V.
L (Black): Surface luminance of the panel at VAC = 4.5V
Both luminosities are measured by System I.
– 11 –
LCX018AK
2. Optical Transmittance
Optical Transmittance (T) is given by the following formula (2).
T=
L (White)
× 100 [%] ... (2)
Luminance of Back Light
L (White) is the same expression as defined in the "Contrast Ratio" section.
3. Chromaticity
Chromaticity of the panels are measured by System I. Raster modes of each color are defined by the
representations at the input signal amplitude conditions shown in the table below. System I uses
Chromaticity of x and y on the CIE standards here.
Raster
Signal amplitudes (VAC) supplied to each input
R input
G input
B input
R
0.5
4.5
4.5
G
4.5
0.5
4.5
B
4.5
4.5
0.5
5. Half Tone Color Reproduction Range
Half tone color reproduction range of the LCD panels is
characterized by the differences between the V-T
characteristics of R, G and B. The differences of these
V-T characteristics are measured by System II. System
II defines signal voltages of each R, G, B raster modes
which correspond to 50% of transmittance, V50R, V50G
and V50B respectively. V50RG and V50BG, the voltage
differences between V50R and V50G, V50B and V50G, are
simply given by the following formula (3) and (4)
respectively.
V50RG = V50R – V50G ... (3)
V50BG = V50B – V50G ... (4)
90
50
10
V90
V50 V10
VAC – Signal amplitude [V]
100
Transmittance [%]
4. V-T Characteristics
V-T characteristics, the relationship between signal
amplitude and the transmittance of the panels, are
measured by System II. V90, V50 and V10 correspond to
the each voltage which defines 90%, 50% and 10% of
transmittance respectively.
Transmittance [%]
(Unit: V)
V50RG
V50BG
50
G raster
R raster
B raster
0
V50R V50B
V50G
VAC – Signal amplitude [V]
– 12 –
LCX018AK
6. Response Time
Response time ton and toff are defined by
the formula (5) and (6) respectively.
ton = t1 – tON ... (5)
toff = t2 – tOFF ... (6)
t1: time which gives 10% transmittance of
the panel.
t2: time which gives 90% transmittance of
the panel.
The relationships between t1, t2, tON and
tOFF are shown in the right figure.
Input signal voltage (waveform applied to the measured pixels)
4.5V
0.5V
6V
0V
Light transmission
output waveform
100%
90%
10%
0%
tON
t1
ton
tOFF
t2
toff
7. Flicker
Flicker (F) is given by the formula (7). DC and AC (NTSC: 30Hz, rms, PAL: 25Hz, rms) components of the
panel output signal for gray raster∗ mode are measured by a DC voltmeter and a spectrum analyzer in
System II.
AC component
}
F [dB] = 20 log {
DC component ... (7)
∗ R, G, B input signal condition for gray raster mode is given by
Vsig = 6 ± V50 [V]
where: V50 is the signal amplitude which gives 50% of
transmittance in V-T curve.
8. Image Retention Time
Image retention time is given by the following procedures:
Apply monoscope signal to the LCD panel for 60 minutes and then change monoscope signal∗ to gray scale
signal (Vsig = 6 ± VAC (V); VAC = 3 to 4V) so as to give the maximum image retention. Hold input signal VAC.
The time of the residual image to disappear gives the image retention time.
∗ Monoscope signal conditions:
Black level
Vsig = 6 ± 4.5 or 6 ± 2.0 [V]
4.5V
White level
(shown in the right figure)
2.0V
Vcom = 5.6V
6V
2.0V
4.5V
0V
Vsig waveform
– 13 –
LCX018AK
9. Method of Measuring the Optimum Vcom
There are two methods of measuring the optimum Vcom using the photoelectric element.
9-1. Method of Measuring Flicker
In the field invert drive mode, adjust the flicker level of the half tone (Vsig = 1.5 to 2.5V) using the
photoelectric element and oscilloscope so that its 30Hz component becomes minimum. The Vcom value
at this time is taken to be the optimum Vcom.
9-2. Method of Measuring Contrast
In the normal 1H invert drive mode, adjust the optical output voltage of the half tone (Vsig = 1.5 to 2.5V) so
that it becomes minimum. The Vcom value at this time is taken to be the optimum Vcom.
Example of Back Light Spectrum (Reference)
0.6
0.4
0.2
0
380
480
580
Wave length 380 – 780 [nm]
– 14 –
680
780
2 dots
– 15 –
225 dots
(Effective 8.775mm)
2 dots
DL2
1
2
3
355
GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW
EVEN = 1069 dots
ODD = 1068 dots
(Effective 15.493mm)
EVEN = 1083 dots
ODD = 1083 dots
357
DR1
DR2
GATE SW GATE SW GATE SW GATE SW
356
EVEN = 7 dots
ODD = 7 dots
B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
2
3
4
225
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
224
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
1
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW
DL1
EVEN = 7 dots
ODD = 8 dots
LCX018AK Dot Arrangement (16:9)
1. Color Coding
The shaded area is used for the dark border around the display.
Description of Operation
LCX018AK
2 dots
– 16 –
225 dots
(Effective 8.775mm)
2 dots
DL2
1
2
45
46
311
312
313
314
GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW
356
357
DR1
DR2
EVEN = 7 dots
ODD = 7 dots
GATE SW GATE SW GATE SW GATE SW GATE SW
Side Black
EVEN = 133 dots
ODD = 132 dots
B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
2
3
4
225
R G B R G B R G B
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
224
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
1
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R
B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B
GATE SW GATE SW GATE SW GATE SW
47
4:3 Area
Side Black
44
EVEN = 803 dots
ODD = 804 dots
(Effective 11.651mm)
EVEN = 1083 dots
ODD = 1083 dots
EVEN = 133 dots
ODD = 132 dots
GATE SW GATE SW GATE SW GATE SW
DL1
EVEN = 7 dots
ODD = 8 dots
LCX018AK Dot Arrangement (4:3)
LCX018AK
LCX018AK
2. LCD Panel Operations
[Description of basic operations]
The basic operations of the LCD panel are shown below based on the wide-display mode.
• A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse
to every 225 gate lines sequentially in every single horizontal scanning period.
• A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuit,
applies selected pulses to every 1068.5 signal electrodes sequentially in a single horizontal scanning period.
• Vertical and horizontal shift registers address one pixel, and then dot Thin Film Transistors (TFTs; two TFTs
for one dot) turn on to apply a video signal to the dot. The same procedures lead to the entire 480 × 1068.5
dots to display a picture in a single vertical scanning period.
• The LCD pixel dots are arranged in a delta pattern, where the dots connected to the identical signal line are
positioned with 1.5-dot offset against those of the adjacent horizontal line. Horizontal Start Pulse (HST) is
generated with 1.5-bit offset between the horizontal lines to regulate the above offset. HCK and sample-hold
(S/H) pulses follow the same 1.5-bit offset scheme.
• The video signal must be input with polarity-inverted system in every horizontal cycle.
• Timing diagrams of the vertical and the horizontal display cycle are shown below.
(1) Vertical display cycle (down-direction scanning)
VD
VST
1
VCK1
2
3
223 224 225
VCK2
Vertical display cycle
(2) Horizontal display cycle (16:9)
BLK
HST
HCK1
1
2
3
HCK2
355 356 357
Horizontal display
cycle
(3) Horizontal display cycle (4:3)
BLK
HST
HCK1
HCK2
1
2
3
267 268 269
Horizontal display cycle
– 17 –
LCX018AK
[Description of operating mode]
The LCD panel has the following functions to easily apply to various uses, as well as various broadcasting
systems.
• Right/left inverse mode
• Up/down inverse mode
• 4:3 display mode with side-black display
These modes are controlled by three signals (RGT, DWN, and WID). The setting mode is shown below:
WID RGT
Mode
DWN
Mode
H
H
16:9 right scan
H
Down scan
H
L
16:9 left scan
L
Up scan
L
H
4:3 right scan
L
L
4:3 left scan
The direction of the right/left and/or up/down mean when Pin 1 marking is located at right side with the pin
block upside.
• The analog signal (PSIG) to display side-black shall be input by 1H inversion synchronized with the signal.
3. 3-dot Simultaneous Sampling (RGB Simultaneous Sampling)
SIG2
S/H
S/H
CK2
CK3
SIG1
S/H
S/H
CK1
CK3
S/H
SIG3
AC Amp
4
SIG2
AC Amp
3
SIG1
AC Amp
5
SIG3
CK3
<Phase relationship of delaying sample-and-hold pulses> (right scan)
HCKn
CK2
CK1
CK3
– 18 –
LCX018AK
Horizontal driver samples SIG1, SIG2 and SIG3 signal simultaneously, which requires the phase matching
between SIG1, SIG2, and SIG3 signals to prevent horizontal resolution from deteriorating. Thus phase
matching between each signal is required using an external signal delaying circuit before applying video
signal to the LCD panel.
The block diagram of the delaying procedure using sample-and-hold method is as follows.
The LCX018 has the right/left inverse function. The following phase relationship diagram indicates the phase
setting for the right scan (RGT = High level). For the left scan (RGT = Low level), the phase setting shall be
inverted between SIG2 and SIG3 signals.
LCX018AK
Example of Color Filter Spectrum (Reference)
100
Color Filter Spectrum
R
80
G
B
Transmittance [%]
60
40
20
0
400
500
600
Wavelength [nm]
– 19 –
700
LCX018AK
Color Display System Block Diagram
+12.0V
+4.5V
+3.0V
+13.5V
PSIG
Composite video
Buff.
Y/C
RED
Y/color difference
GREEN
BLUE
COM
HST
HCK1
HCK2
CXA2543R
VST
Serial data
VCK1
VCK2
ENB
PCG
DWN
WID
RGT
(Refer to CXA2543R data sheet.)
Control circuit
– 20 –
LCD panel
NT/PAL/WID
LCX018AK
LCX018AK
Notes on Handling
(1) Static charge prevention
Be sure to take following protective measures. TFT-LCD panels are easily damaged by static charge.
a) Use non-chargeable gloves, or simply use bare hands.
b) Use an earth-band when handling.
c) Do not touch any electrodes of a panel.
d) Wear non-chargeable clothes and conductive shoes.
e) Install conductive mat on the working floor and working table.
f) Keep panels away from any charged materials.
g) Use ionized air to discharge the panels.
(2) Protection from dust and dirt
a) Operate in clean environment.
b) When delivered, a surface of a panel (Polarizer) is covered by a protective sheet. Peel off the protective
sheet carefully not to damage the panel.
c) Do not touch the surface of a panel. The surface is easily scratched. When cleaning, use a clean-room
wiper with isopropyl alcohol. Be careful not to leave stain on the surface.
d) Use ionized air to blow off dust at a panel.
(3) Other handling precautions
a) Do not twist or bend the flexible PC board especially at the connecting region because the board is easily
deformed.
b) Do not drop a panel.
c) Do not twist or bend a panel or a panel frame.
d) Keep a panel away from heat source.
e) Do not dampen a panel with water or other solvents.
f) Avoid to store or to use a panel in high temperature or in high humidity, which results in panel damages.
– 21 –
LCX018AK
Package Outline
Unit: mm
2.9 ± 0.15
Thickness of the connector 0.3 ± 0.05
1.3 ± 0.3
10.5 ± 0.05
4
(40.2)
1
59.2 ± 0.8
1.0
19.0 ± 0.15
4-R
Incident light
Polarizing Axis
Active Area
3
5
2
6
Output light
Polarizing Axis
Incident
light
7.6 ± 0.25
(8.8)
6
No
(15.5)
11.0 ± 0.25
1
Description
F P C
+ 0.04
0.35 – 0.03
PIN1
0.5 ± 0.1
PIN 20
3.0 ± 0.3
P 0.5 ± 0.02 × 19 = 9.5 ± 0.03
0.5 ± 0.15
22.0 ± 0.15
2
Molding material
3
Outside frame
4
Reinforcing board
5 Reinforcing material
6
Polarizing film
weight 2g
electrode (enlarged)
The rotation angle of the active area relative to H and V is ± 1°.
– 22 –