SCAS261A − JANUARY 1993 − REVISED JULY 1995 D EPIC (Enhanced-Performance Implanted D D D D D D DGG OR DL PACKAGE (TOP VIEW) CMOS) Submicron Process Member of the Texas Instruments Widebus Family UBT (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages OEAB LEAB A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 OEBA LEBA description The SN74ALVC16501 18-bit universal bus transceiver is designed for low-voltage (3.3-V) VCC operation; it is tested at 2.5-V, 2.7-V, and 3.3-V VCC. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A-bus data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is high, the outputs are active. When OEAB is low, the outputs are in the high-impedance state. 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 GND CLKAB B1 GND B2 B3 VCC B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VCC B16 B17 GND B18 CLKBA GND Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are complementary (OEAB is active high and OEBA is active low). The SN74ALVC16501 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG) packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The SN74ALVC16501 is characterized for operation from − 40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC, UBT, and Widebus are trademarks of Texas Instruments Incorporated. Copyright 1995, Texas Instruments Incorporated !"# $ %&'# "$ (&)*%"# +"#', +&%#$ %! # $('%%"#$ (' #-' #'!$ '."$ $#&!'#$ $#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+' #'$#1 "** (""!'#'$, • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 1 SCAS261A − JANUARY 1993 − REVISED JULY 1995 FUNCTION TABLE† INPUTS OEAB LEAB CLKAB A OUTPUT B Z L X X X H H X L L H H X H H H L ↑ L L H L ↑ H H L H X H B0‡ X B0§ † A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, and CLKBA. ‡ Output level before the indicated steady-state input conditions were established, provided that CLKAB is high before LEAB goes low § Output level before the indicated steady-state input conditions were established H L L logic symbol† OEAB CLKAB LEAB 1 55 2 27 OEBA CLKBA LEBA A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 30 28 3 EN1 2C3 C3 G2 EN4 5C6 C6 G5 3D 1 1 4 1 6D 5 52 6 51 8 49 9 48 10 47 12 45 13 44 14 43 15 42 16 41 17 40 19 38 20 37 21 36 23 34 24 33 26 31 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 54 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 SCAS261A − JANUARY 1993 − REVISED JULY 1995 logic diagram (positive logic) OEAB CLKAB LEAB LEBA CLKBA OEBA A1 1 55 2 28 30 27 3 1D C1 CLK 54 B1 1D C1 CLK To 17 Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Input voltage range, VI (I/O ports) (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 100 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 3): DGG package . . . . . . . . . . . . . . . . . . 1 W DL package . . . . . . . . . . . . . . . . . . 1.4 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 3 SCAS261A − JANUARY 1993 − REVISED JULY 1995 recommended operating conditions (see Note 4) VCC Supply voltage VIH High-level input voltage VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VIL Low-level input voltage VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VI VO Input voltage IOH IOL ∆t /∆v MAX 2.3 3.6 Output voltage Low-level output current 0.7 0.8 −12 VCC = 3 V VCC = 2.3 V −24 VCC = 2.7 V VCC = 3 V 12 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • VCC VCC VCC = 2.3 V VCC = 2.7 V Input transition rise or fall rate V V 2 0 High-level output current UNIT 1.7 0 TA Operating free-air temperature NOTE 4: Unused inputs must be held high or low to prevent them from floating. 4 MIN −12 V V V mA 12 mA 24 0 10 ns / V −40 85 °C SCAS261A − JANUARY 1993 − REVISED JULY 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER IOH = − 100 µA IOH = − 6 mA VOH VOL VIH = 1.7 V VIH = 1.7 V MIN to MAX 2.3 V VCC −0.2 2 2.3 V 1.7 IOH = − 12 mA VIH = 2 V VIH = 2 V 2.7 V 2.2 3V 2.4 IOH = − 24 mA IOL = 100 µA VIH = 2 V 3V 2 MIN to MAX 0.2 IOL = 6 mA VIL = 0.7 V VIL = 0.7 V 2.3 V 0.4 2.3 V 0.7 VIL = 0.8 V VIL = 0.8 V 2.7 V 0.4 3V 0.55 IOL = 12 mA IOL = 24 mA VI = VCC or GND II Ihold 2.3 V VI = 0.8 V VI = 2 V 3V V µA 45 −45 µA 75 VI = VCC or GND, VCC = 3 V to 3.6 V, Other inputs at VCC or GND nICC UNIT V 3.6 V VI = 0.7 V VI = 1.7 V VI = 0 to 3.6 V VO = VCC or GND IOZ§ ICC TA = − 40°C to 85°C MIN TYP‡ MAX VCC† TEST CONDITIONS IO = 0 One input at VCC − 0.6 V, −75 3.6 V ± 500 3.6 V ± 10 µA 3.6 V 40 µA 750 µA Ci Control inputs VI = VCC or GND 3.3 V Cio A or B ports VO = VCC or GND 3.3 V † For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions. ‡ All typical values are at VCC = 3.3 V. § For I/O ports, the parameter IOZ includes the input leakage current. 4 pF 8 pF timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC = 2.5 V ± 0.2 V fclock Clock frequency tw Pulse duration tsu Setup time th Hold time MIN MAX 0 150 VCC = 2.7 V MIN MAX 0 150 VCC = 3.3 V ± 0.3 V MIN MAX 0 150 LE high 3.3 3.3 3.3 CLK high or low 3.3 3.3 3.3 Data before CLK↑ 2.2 2.1 1.7 Data before LE↓, CLK high 1.9 1.6 1.5 Data before LE↓, CLK low 1.3 1.1 1 Data after CLK↑ 0.6 0.6 0.7 Data after LE↓, CLK high or low 1.4 1.7 1.4 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • UNIT MHz ns ns ns 5 SCAS261A − JANUARY 1993 − REVISED JULY 1995 switching characteristics over recommended operating free-air temperature range, (unless otherwise noted) (see Figures 1 and 2) PARAMETER FROM (INPUT) TO (OUTPUT) fmax VCC = 2.5 V ± 0.2 V MIN MAX 150 VCC = 2.7 V MIN MAX 150 VCC = 3.3 V ± 0.3 V MIN UNIT MAX 150 ns A or B B or A 1.2 5.4 4.5 1 3.9 LE A or B 1.6 6.3 5.3 1.3 4.6 CLK A or B 1.7 6.7 5.6 1.4 4.9 ten tdis OEAB B 1.1 6.3 5.3 1 4.6 ns OEAB B 2.2 6.4 5.7 1.4 5 ns ten tdis OEBA A 1.4 6.8 6 1.1 5 ns OEBA A 2 5.5 4.6 1.3 4.2 ns tpd ns operating characteristics, TA = 25°C PARAMETER Cpd 6 Power dissipation capacitance TEST CONDITIONS Outputs enabled CL = 50 pF, Outputs disabled • f = 10 MHz POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V TYP TYP 44 54 6 6 UNIT pF SCAS261A − JANUARY 1993 − REVISED JULY 1995 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V " 0.2 V 4.6 V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 4.6 V GND tw LOAD CIRCUIT 2.3 V Input 2.3 V Timing Input VOLTAGE WAVEFORMS PULSE DURATION th 2.3 V Data Input 1.2 V 1.2 V 0V tPHL Output Waveform 2 S1 at GND (see Note B) VOH 1.2 V 1.2 V VOL 1.2 V 0V tPLZ 2.3 V Output Waveform 1 S1 at 4.6 V (see Note B) 1.2 V tPLH 1.2 V tPZL 2.3 V 1.2 V 2.3 V Output Control (low-level enabling) 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output 1.2 V 0V 0V tsu Input 1.2 V 1.2 V 1.2 V tPZH VOL + 0.3 V VOL tPHZ 1.2 V VOH − 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR v 10 MHz, ZO = 50 Ω, tr v 2.5 ns, tf v 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 7 SCAS261A − JANUARY 1993 − REVISED JULY 1995 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V " 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V Input 2.7 V Timing Input VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V tPHL Output Waveform 2 S1 at GND (see Note B) VOH 1.5 V 1.5 V VOL 1.5 V 0V tPLZ 3V Output Waveform 1 S1 at 6 V (see Note B) 1.5 V tPLH 1.5 V tPZL 2.7 V 1.5 V 2.7 V Output Control (low-level enabling) 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output 1.5 V 0V 0V tsu Input 1.5 V 1.5 V 1.5 V tPZH VOL + 0.3 V VOL tPHZ 1.5 V VOH − 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR v 10 MHz, ZO = 50 Ω, tr v 2.5 ns, tf v 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms 8 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • PACKAGE OPTION ADDENDUM www.ti.com 24-Jun-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74ALVC16501DL OBSOLETE SSOP DL 56 TBD Call TI Call TI SN74ALVC16501DLR OBSOLETE SSOP DL 56 TBD Call TI Call TI Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.620 (15,75) 0.720 (18,29) DIM 4040048 / E 12/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. 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