STMICROELECTRONICS TDA9111

TDA9111
LOW-COST I2C CONTROLLED DEFLECTION PROCESSOR
FOR MULTISYNC MONITOR
FEATURES
General
SYNC PROCESSOR (separate or composite)
12V SUPPLY VOLTAGE
■ 8V REFERENCE VOLTAGE
■ HOR. LOCK/UNLOCK OUTPUT
■ HOR. & VERT. LOCK/UNLOCK INDICATION
2
■ READ/WRITE I C INTERFACE
■ HORIZONTAL AND VERTICAL MOIRE
■ B+ REGULATOR
- Internal PWM generator for B+ current mode
step-up converter
- Switchable to step-down converter
- I2C adjustable B+ reference voltage
- Output pulses synchronized on horizontal
frequency
- Internal maximum current limitation.
Horizontal
■
■
Self-adaptative
Dual PLL concept
■ 150kHz maximum frequency
■ X-Ray protection input
2
■ I C controls: Horizontal duty-cycle, H-position,
horizontal size amplitude
Vertical
DESCRIPTION
The TDA9111 is a monolithic integrated circuit assembled in a 32-pin shrink dual-in-line plastic
package. This IC controls all the functions related
to horizontal and vertical deflection in multimode
or multi-frequency computer display monitors.
The internal sync processor, combined with the
powerful geometry correction block, makes the
TDA9111 suitable for very high performance monitors, using few external components.
The horizontal jitter level is very low. It is particularly well-suited to high-end 15” and 17” monitors.
Combined with the ST7275 Microcontroller family,
TDA9206 (Video preamplifier) and STV942x (OnScreen Display controller), the TDA9111 allows
fully-I2C bus-controlled computer display monitors
to be built with a reduced number of external components.
■
■
Vertical ramp generator
■ 50 to 185Hz AGC loop
■ Geometry tracking with VPOS & VAMP
2
■ I C controls:
VAMP, VPOS, S-CORR, C-CORR
■ DC breathing compensation
I2C Geometry corrections
SHRINK32 (Plastic Package)
ORDER CODE: TDA9111
PIN CONNECTIONS
■
■
■
■
Vertical parabola generator (Pin Cushion - E/W,
Keystone, Corner Correction)
Horizontal dynamic phase (Side Pin Balance &
Parallelogram)
Horizontal and vertical dynamic focus
(Horizontal Focus Amplitude, Horizontal Focus
Symmetry, Vertical Focus Amplitude)
H/HVIN
VSYNCIN
HMOIRE/HLOCK
PLL2C
C0
R0
PLL1F
HPOSITION
HFOCUSCAP
FOCUS-OUT
HGND
HFLY
HREF
COMP
REGIN
ISENSE
1
2
3
32
31
30
4
5
6
7
29
28
27
26
8
25
9
10
11
12
24
23
22
21
13
14
15
16
20
19
18
17
5V
SDA
SCL
VCC
BOUT
GND
HOUT
XRAY
EWOUT
VOUT
VCAP
VREF
VAGCCAP
VGND
VBREATH
B + GND
Version 4.2
June 2000
1/43
1
TABLE OF CONTENTS
PIN CONNECTIONS
QUICK REFERENCE DATA
BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
SUPPLY AND REFERENCE VOLTAGES
I2C READ/WRITE
SYNC PROCESSOR
HORIZONTAL SECTION
VERTICAL SECTION
DYNAMIC FOCUS SECTION
GEOMETRY CONTROL SECTION
MOIRE CANCELLATION SECTION
B+ SECTION
TYPICAL OUTPUT WAVEFORMS
I2C BUS ADDRESS TABLE
OPERATING DESCRIPTION
1
......................................................................3
......................................................................4
......................................................................5
......................................................................6
......................................................................6
......................................................................6
......................................................................7
......................................................................7
......................................................................8
......................................................................10
......................................................................11
......................................................................12
......................................................................13
......................................................................14
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......................................................................20
......................................................................23
GENERAL CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.1 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.2 I2C Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.3 Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.4 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.5 Sync Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.6 Sync Identification Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.7 IC status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.8 Sync Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.9 Sync Processor Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2
HORIZONTAL PART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.1 Internal Input Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.2 PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.3 PLL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.4 Output Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.5 X-RAY Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.6 Horizontal and Vertical Dynamic Focus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.7 Horizontal Moiré Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3
VERTICAL PART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.1 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.2 I2C Control Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.3 Vertical Moiré . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.4 Basic Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.5 Geometric Corrections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.6 E/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.7 Dynamic Horizontal Phase Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4
DC/DC CONVERTER PART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.1 Step-up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.2 Step-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.3 Step-up and Step-down Mode Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . .2. . . 33
INTERNAL SCHEMATICS
......................................................................35
PACKAGE MECHANICAL DATA
......................................................................42
2/43
TDA9111
PIN CONNECTIONS
Pin
Name
Function
1
H/HVIN
TTL compatible Horizontal sync Input (separate or composite)
2
VSYNCIN
TTL compatible Vertical sync Input (for separated H&V)
3
HMOIRE/
HLOCK
Horizontal Moiré Output (to be connected to PLL2C through a resistor divider), HLock
Output
4
PLL2C
Second PLL Loop Filter
5
C0
Horizontal Oscillator Capacitor
6
R0
Horizontal Oscillator Resistor
7
PLL1F
First PLL Loop Filter
8
HPOSITIO N
Horizontal Position Filter (capacitor to be connected to HGND)
9
HFOCUSCAP
Horizontal Dynamic Focus Oscillator Capacitor
10
FOCUS OUT
Mixed Horizontal and Vertical Dynamic Focus Output
11
HGND
Horizontal Section Ground
12
HFLY
Horizontal Flyback Input (positive polarity)
13
HREF
Horizontal Section Reference Voltage (to be filtered)
14
COMP
B+ Error Amplifier Output for frequency compensation and gain setting
15
REGIN
Feedback Input of B+ control loop
16
ISENSE
Sensing of external B+ switching transistor current, or switch for step-down converter
17
B+GND
Ground (related to B+ reference)
18
VBREATH
V Breathing Input Control (compensation of vertical amplitude against EHV variation)
19
VGND
Vertical Section Ground
20
VAGCCAP
Memory Capacitor for Automatic Gain Control in Vertical Ramp Generator
21
VREF
Vertical Section Reference Voltage (to be filtered)
22
VCAP
Vertical Sawtooth Generator Capacitor
23
VOUT
Vertical Ramp Output (with frequency-independent amplitude and S or C Corrections
if any). It is mixed with vertical position voltage and vertical moiré.
24
EWOUT
Pin Cushion (E/W) Correction Parabola Output
25
XRAY
X-RAY protection input (with internal latch function)
26
HOUT
Horizontal Drive Output (open collector)
27
GND
General Ground
28
BOUT
B+ PWM Regulator Output
29
VCC
Supply Voltage(12V typ) (referenced to Pin 27)
30
SCL
I2C Clock Input
31
SDA
I2C Data Input
32
5V
5V Supply Voltage
3/43
TDA9111
QUICK REFERENCE DATA
Parameter
Value
Any polarity on H Sync & V Sync inputs
YES
TTL or composite Syncs
YES
Sync on Green
NO
Horizontal Frequency
15 to 150
Horizontal Autosync Range (for given R0 and C0. Can be easily increased by application)
1 to 4.5 f0
Control of free-running frequency
Unit
kHz
NO
Frequency Generator for Burn-in
NO
Control of H-Position through I 2C
YES
Control for H-Duty Cycle through I2C
30 to 65
PLL1 Inhibition Possibility
NO
Output for Horizontal Lock/Unlock
YES
Dual Polarity H-Drive Outputs
NO
%
Vertical Frequency
35 to 200
Hz
Vertical Autosync Range (for 150nF on Pin 22 and 470nF on Pin 20)
50 to 185
Hz
Vertical S-Correction (adapted to normal or super flat tube), controlled through I2C
YES
Vertical C-Correction, controlled through I2C
YES
Control of Vertical Amplitude through I2 C
YES
2
Control of Vertical Position through I C
YES
Input for Vertical Amplitude compensation versus EHV
YES
E/W Correction Output (also known as Pin Cushion Output)
YES
Horizontal Size Adjustment through I2C control of E/W Output DC level
YES
Control of E/W (Pincushion) Adjustment through I2 C
YES
Control of Keystone (Trapezoïd) Adjustment through
I 2C
YES
Control of Corner Adjustment through I2C
YES
Fully integrated Dynamic Horizontal Phase Control
Control of Side Pin Balance through I2C
YES
Control of Parallelogram through I2C
YES
YES
H/V composite Dynamic Focus Output
YES
2
Control of Horizontal Dynamic Focus Amplitude through I C
YES
Control of Horizontal Dynamic Focus Symmetry through I2C
YES
Control of Vertical Dynamic Focus Amplitude through I2C
YES
Tracking of Geometric Corrections and of Vertical focus with Vertical Amplitude and Position
YES
Control of Horizontal and Vertical Moiré cancellations through I2C
YES
Optimisation of HMoiré frequency through I2C
YES
B+ Regulation, adjustable through I2C
YES
Stand-by function, disabling H and V scanning and B+
YES
X-Ray protection, disabling H scanning and B+
YES
Blanking Outputs
NO
2
Fast I C Read/Write
I2C indication of the presence of Syncs (biased from 5V alone)
400
YES
I2C indication of the polarity and Type of Syncs
YES
I2C indication of Lock/Unlock, for both Horizontal and Vertical sections
YES
4/43
kHz
POSITION
7
8
6
Phase/Frequency
Comparator
H-Phase(7bits)
H/HVIN 1
VSYNCIN 2
Sync Input
Select
(1bit)
VSYNC
Sync
Processor
R0 C0
HFLY
5
PLL2C
12
VCO
4
Phase
Comparator
Lock/Unlock
Identification
HOUT
26
Phase
Shifter
11 HGND
19 VGND
17 GND
29 VCC
25 XRAY
Hout
Buffer
H-Duty
(7bits)
Safety
Processor
SPin bal
7bits
28 B+OUT
16 ISENSE
14 COMP
x2
B+
Controller
HFLY
x
15 REGIN
+
HMOIRE 3
/HLOCK
HorizontalMoire
Generator
7 bits+ON/OFF
+Frequency
Parallelogram
7bits
5V
7 bits
7 bits
VAMP
7bits
I2C Interface
S and C
Correction
5V 32
HREF 13
Href
VREF 21
Vref
Internal
reference
(7bits)
VDFAMP
7bits
Corner
7bits
Geometry
Tracking
SDA 31
SCL 30
GND 27
Vertical
Oscillator
Ramp Generator
x4
E/Wpcc
7bits
Keyst.
7 bits
VSYNC
VCAP VAGCCAP
10 FOCUS
Amp,
2
Symmetryx
2x7bits
x2
x
9 HFOCUSCAP
24 EWOUT
HSize
DC 7 bits
18 23
VBREATHVOUT
TDA9111
5/43
TDA9111
20
x2
VerticalMoire
Cancel
7bits+ON/OFF
VPOS
7bits
22
BLOCK DIAGRAM
PLL1F
TDA9111
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
13.5
V
VCC
Supply Voltage (Pin 29)
VDD
Supply Voltage (Pin 32)
5.7
V
Max Voltage on
4.0
5.5
6.4
8.0
V CC
V DD
5
V
V
V
V
V
V
V
2
300
kV
V
-40, +150
°C
VIN
VESD
Pin 4
Pin 9
Pin 5
Pins 6, 7, 8, 14, 15, 16, 20, 22
Pins 3, 10, 18, 23, 24, 25, 26, 28
Pins 1, 2
Pins 30, 31
ESD susceptibility
through 1.5kΩ
Human Body Model, 100pF Discharge
EIAJ Norm, 200pF Discharge through 0Ω
Tstg
Storage Temperature
Tj
Junction Temperature
+150
°C
Operating Temperature
0, +70
°C
Value
Unit
65
°C/W
Toper
THERMAL DATA
Symbol
Rth(j-a)
Parameter
Max. Junction-Ambient Thermal Resistance
SUPPLY AND REFERENCE VOLTAGES
Electrical Characteristics (VCC = 12V, Tamb = 25°C
Symbol
6/43
Min.
Typ.
Max.
Units
VCC
Supply Voltage
Parameter
Pin 29
Test Conditions
10.8
12
13.2
V
VDD
Supply Voltage
Pin 32
4.5
5
5.5
ICC
Supply Current
Pin 29
IDD
50
V
mA
Supply Current
Pin 32
VREF-H
Horizontal Reference Voltage
Pin 13, I = -2mA
7.6
8.2
5
8.8
mA
V
VREF-V
Vertical Reference Voltage
Pin 21, I = -2mA
7.6
8.2
8.8
V
IREF-H
Max. Sourced Current on VREF-H
Pin 13
5
mA
IREF-V
Max. Sourced Current on VREF-V
Pin 21
5
mA
TDA9111
I2C READ/WRITE
Electrical Characteristics (VDD = 5V, Tamb = 25°C)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
400
kHz
I2C PROCESSOR (1)
Fscl
Maximum Clock Frequency
Pin 30
Tlow
Low period of the SCL Clock
Pin 30
1.3
Thigh
High period of the SCL Clock
Pin 30
0.6
Vinth
SDA and SCL Input Threshold
Pins 30, 31
VACK
Acknowledged Output Voltage on SDA
input with 3mA
Pin 31
0.4
V
I2C leak
Leakage current into SDA and SCL with
no logic supply
VDD = 0
Pins 30, 31 = 5 V
20
µA
Max.
Units
5
V
Note: 1
µs
µs
2.2
V
See also I2 C Sub Address Table.
SYNC PROCESSOR
Operating Conditions (VDD = 5V, VCC = 12V, Tamb = 25°C)
Symbol
Parameter
Test Conditions
Min.
HSVR
Voltage on H/HVIN Input
Pin 1
0
MinD
Minimum Horizontal Input Pulses Duration
Pin 1
0.7
Mduty
Maximum Horizontal Input Signal Duty
Cycle
Pin 1
VSVR
Voltage on VSYNCIN
Pin 2
0
VSW
Minimum Vertical Sync Pulse Width
Pin 2
5
Typ.
µs
25
5
%
V
µs
VSmD
Maximum Vertical Sync Input Duty Cycle Pin 2
15
%
VextM
Maximum Vertical Sync Width on TTL H/
Pin 1
Vcomposite
750
µs
Max.
Units
0.8
V
V
Electrical Characteristics (VDD = 5V, VCC = 12V, Tamb = 25°C)
Symbol
VINTH
Parameter
Test Conditions
Horizontal and Vertical Input Logic Level High Level
(Pins 1, 2)
Low Level
RIN
Horizontal and Vertical Pull-Up Resistor
Pins 1, 2
VoutT
Extracted Vsync Integration Time (% of
TH) on H/VComposite (2)
C0 = 820pF
Note: 2
Min.
Typ.
2.2
26
250
kΩ
35
%
T H is the horizontal period.
7/43
TDA9111
HORIZONTAL SECTION
Operating Conditions
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
VCO
I0max
F(max.)
Max Current from Pin 6
Pin 6
Maximum Oscillator Frequency
1.5
mA
150
kHz
OUTPUT SECTION
I12m
Maximum Input Peak Current
Pin 12
5
mA
HOI
Horizontal Drive Output Maximum Current
Pin 26, Sunk current
30
mA
Max.
Units
Electrical Characteristics (VCC = 12V, Tamb = 25°C)
Symbol
Parameter
Test Conditions
Min.
Typ.
1st PLL SECTION
HpoIT
Delay Time for detecting polarity
change (3)
Pin 1
Vvco
VCO Control Voltage (Pin 7)
VREF-H = 8.2V
fH = f0
fH=fH (Max.)
Vcog
VCO Gain (Pin 7)
R 0 = 6.49kΩ,
C 0 = 820pF
Hph
Horizontal Phase Adjustment (4)
% of Horizontal
Period
Horizontal Phase Setting Value (Pin 8)(4)
Minimum Value
Typical Value
Maximum Value
Sub-Address 01
Byte
x1111111
Byte
x1000000
Byte
x0000000
PLL1 Filter Charge Current
PLL1 is Unlocked
PLL1 is Locked
Vbmi
Vbtyp
Vbmax
IPII1U
IPII1L
fo
dfo/dT
CR
HUnlock
8/43
Free Running Frequency
Free Running Frequency Thermal Drift
R 0 = 6.49kΩ, C 0 = 820pF
(5)
0.75
1.4
6.4
Tbd
Tbd
Not including external
componant drift
PLL1 Capture Range
fH(Min.)
fH(Max.) (6)
DC level pin 3 when PLL1 is
unlocked
Sub-address 02
1xxx xxxx
0000 0000
0111 1111 (7)
ms
15.9
V
V
Tbd
kHz/V
±10
%
2.9
3.5
4.2
V
V
V
±140
±1
µA
mA
22.8
Tbd
kHz
-150
ppm/C
fo+0.5
4.5fo
kHz
kHz
0.3
2.75
V
V
V
6
3
TDA9111
Symbol
Parameter
Test Conditions
Min.
Typ.
0.65
Max.
Units
2nd PLL SECTION AND HORIZONTAL OUTPUT SECTION
FBth
0.75
V
Horizontal Jitter (8)
At 31.4kHz
70
ppm
HDmin
HDmax
Horizontal Drive Output Duty-Cycle (Pin
26) (9)
Sub-Address 00
Byte x1111111
Byte x0000000 (10)
30
65
%
%
XRAYth
X-RAY Protection Input Threshold Voltage,
Pin 25, (see fig. 14)
Internal Clamping Levels on 2nd PLL
Loop Filter (Pin 4)
Low Level
High Level
Hjit
Vphi2
VSCinh
Flyback Input Threshold Voltage (Pin 12)
Inhibition threshold (The condition VCC <
VSCinh will stop H-Out, V-Out, B-Out and Pin 29
reset X-RAY)
7.6
8.2
8.8
V
1.6
4.2
V
V
7.5
V
0.4
V
HDvd
Horizontal Drive Output (low level)
Pin 26, IOUT = 30mA
Note: 3 This delay is necessary to avoid a wrong detection of polarity change in the case of a composite sync.
4 See Figure 10 for explanation of reference phase.
5 These parameters are not tested on each unit. They are measured during our internal qualification.
6 A larger range may be obtained by application.
7 When at 0xxx xxxx, (HMoiré/HLock not selected), Pin 3 is a DAC with 0.3...2.75V range. When at 1xxx xxxx
(HMoiré/HLock selected) and PLL1 is locked, Pin 3 provides the waveform for HMoiré. See also Moiré
section.
Hjit = 106x(Standard deviation/Horizontal period).
Duty Cycle is the ratio between the output transistor OFF time and the period. The scanning transistor is
controlled OFF when the output transistor is OFF.
10 Initial Condition for Safe Start Up.
8
9
9/43
TDA9111
VERTICAL SECTION
Operating Conditions
Symbol
Parameter
RLOAD
Minimum Load for less than 1% Vertical
Amplitude Drift
Test Conditions
Pin 20
Min.
Typ.
Max.
65
Units
MΩ
Electrical Characteristics (VCC = 12V, Tamb = 25°C)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
VRB
Voltage at Ramp Bottom Point
Pin 22
2.1
V
VRT
Voltage at Ramp Top Point (with Sync)
Pin 22
5.1
V
Pin 22
VRT0.1
V
VRTF
Voltage at Ramp Top Point (without
Sync)
VSTD
Vertical Sawtooth Discharge Time
Pin 22, C22 = 150nF
70
µs
VFRF
Vertical Free Running Frequency (12)
Pin 22, C22 = 150nF
100
Hz
ASFR
AUTO-SYNC Frequency (13)
C 22 = 150nF ±5%
RAFD
Ramp Amplitude Drift Versus Frequency C 22 = 150nF
50Hz< f < 185Hz
at Maximum Vertical Amplitude (11)
200
ppm/
Hz
Ramp Linearity on Pin 22 (12)
0.5
%
Rlin
VPOS
2.5V < V27 < 4.5V
Sub Address 06
Vertical Position Adjustment Voltage (Pin Byte 00000000
23 - VOUT mean value)
Byte 01000000
Byte 01111111
Sub Address 05
Byte 10000000
Byte 11000000
Byte 11111111
VOR
Vertical Output Voltage
(peak-to-peak on Pin 23)
VOI
Vertical Output Maximum Current
(Pin 23)
dVS
Max Vertical S-Correction Amplitude (TV Sub Address 07
Byte 11111111
is the vertical period)
∆V/VPP at TV/4
(0xxxxxxx inhibits S-CORR
∆V/VPP at 3TV/4
11111111 gives max S-CORR)
Ccorr
BRRANG
BRADj
50
Vertical C-Corr Amplitude
(0xxxxxxx inhibits C-CORR)
Sub Address 08
∆V/VPP at TV/2
Byte 10000000
Byte 11000000
Byte 11111111
DC Breathing Control Range (14)
V 18
Vertical Output Variation versus DC
Breathing Control (Pin 23)
V 18 > VREF-V
1V<V 18< VREF-V
185
Hz
Tbd
Tbd
3.2
3.6
4.0
V
V
V
Tbd
Tbd
2.15
3.0
3.9
V
V
V
±5
mA
-3.5
+3.5
%
%
-3
0
+3
%
%
%
1
12
0
-2.5
V
%/V
%/V
Note: 11 These parameters are not tested on each unit. They are measured during our internal qualification procedure.
Note: 12 Set Register 07 at Byte 0xxxxxxx (S correction inhibited) and Register 08 at Byte 0xxxxxxx (C correction
inhibited), to obtain a vertical sawtooth with linear shape.
Note: 13 This is the frequency range for which the vertical oscillator will automatically synchronize, using a single
capacitor value on Pin22 and Pin 20, and with a constant ramp amplitude.
Note: 14 When not used, the DC breathing control pin must be connected to 12V.
10/43
TDA9111
DYNAMIC FOCUS SECTION
Electrical Characteristics (VCC = 12V, Tamb = 25°C)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
HORIZONTAL DYNAMIC FOCUS FUNCTION (seeFigure 15 on page 29)
HDFst
Horizontal Dynamic Focus Sawtooth
Minimum Level
Maximum Level
Pin 9, capacitor on HFOCUSCAP and
C0 = 820pF, TH = 20µs
HDFdis
Horizontal Dynamic Focus Sawtooth DisTriggered by HDFstart
charge Width
2.2
4.9
V
V
400
ns
1
µs
2.1
V
200
ppm/C
1
1.5
3.5
VPP
VPP
VPP
16
16
%
%
AMPVDF
Sub-Address 0F
Vertical Dynamic Focus Parabola (added
Min Byte x0000000
to horizontal) Amplitude with VAMP and
Typ Byte x1000000
VPOS Typical
Max Byte x1111111
0
0.5
1
VPP
VPP
VPP
VDFAMP
Parabola Amplitude Function of VAMP
(tracking between VAMP and VDF) with
VPOS Typ. (seeFigure 1 on page 15 and
(15))
Sub-Address 05
Byte
x0000000
Byte
x1000000
Byte
x1111111
0.6
1
1.5
VPP
VPP
VPP
Sub-Address 06
VHDFKeyt
Parabola Asymmetry Function of VPOS
Control (tracking between VPOS and
VDF) with VAMP Max.
B/A Ratio
A/B Ratio
HDFstart
Internal Phase Advance versus HFLY
middle
(Independent of frequency)
HDFDC
Bottom DC Output Level
TDFHD
DC Output Voltage Thermal Drift (11)
Horizontal Dynamic Focus
Amplitude
HDFamp
HDFKeyst
Max Byte
Typ Byte
Max Byte
Horizontal Dynamic FocusSymmetry
(For time reference, see Figure 15 )
Advance for Byte
Delay for Byte
RLOAD = 10kΩ,
Pin 10
Sub-Address 03,
Pin 10, fH = 50kHz,
Symmetric Wave Form
x1111111
x1000000
x0000000
Subaddress 04
x1111111 (decimal 127)
x0000000 (decimal 0)
VERTICAL DYNAMIC FOCUS FUNCTION (see Figu re 1)
Byte
Byte
x0000000
x1111111
0.52
0.52
Note: 15 S and C correction are inhibited to obtain a linear vertical sawtooth.
11/43
TDA9111
GEOMETRY CONTROL SECTION
Electrical Characteristics (VCC = 12V, Tamb = 25°C)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
SYMMETRIC CONTROL THROUGH E/W OUTPUT (see Figure 2 on page 15 and Figu re 4 on page 15)
VEWM
Maximum E/W Output Voltage
Pin 24
VEWm
Minimum E/W Output Voltage
Pin 24
EW DC
For control of Horizontal size. DC Output Pin 24, see Figure 2
Voltage with E/W, corner and Keystone Subaddress 11
inhibited
Byte x0000000
Byte x1000000
Byte x1111111
See (16)
6.5
1.8
V
V
2
3.25
4.2
V
V
V
TDEW DC
DC Output Voltage Thermal Drift
100
ppm/C
EWpara
Parabola Amplitude with Max. VAMP,
Subaddress 0A
Typ. VPOS, Keystone and Corner inhibit- Byte 11111111
ed
Byte 11000000
Byte 10000000
1.4
0.7
0
VPP
VPP
VPP
EWtrack
Parabola Amplitude Function of VAMP
Control (tracking between VAMP and E/
W) with Typ. VPOS, Typ. E/W Amplitude,
corner and Keystone inhibited (17)
0.2
0.4
0.7
VPP
VPP
VPP
0.4
0.4
VPP
VPP
VPP
VPP
VPP
Subaddress 05
Byte 10000000
Byte 11000000
Byte 11111111
KeyAdj
Keystone Adjustment Capability with
Subaddress 09
Typ. VPOS, E/W inhibited, Corner inhibitByte 10000000
(17)
and
ed and Max. Vert. Amplitude (see
Byte 11111111
Figure 4)
EW Corner
Subaddress 10
Corner Adjustment Capability with Typ.
Byte 11111111
VPOS, E/W inhibited, Keystone inhibited
Byte 11000000
and Max. Vertical Amplitude
Byte 10000000
+1.25
0
−1.25
Intrinsic Keystone Function of VPOS
Control (tracking between VPOS and E/
W) with Max. E/W Amplitude and Max.
Vertical Amplitude, Corner inhibited
B/A Ratio
A/B Ratio
0.52
0.52
KeyTrack
Subaddress 06
Byte 00000000
Byte 01111111
ASYMMETRIC CONTROL THROUGH INTERNAL DYNAMIC HORIZONTAL PHASE MODULATION (see Figu re 3)
Subaddress 0D
Byte 11111111
Byte 10000000
+2.8
-2.8
%TH
%TH
Subaddress 05
Byte 10000000
Byte 11000000
Byte 11111111
1
1.8
2.8
%TH
%TH
%TH
ParAdj
Parallelogram Adjustment Capability with Subaddress 0E
Max. VAMP, Typ. VPOS and SPB inhibit- Byte 11111111
ed (17 & 18)
Byte 11000000
+2.8
-2.8
%TH
%TH
Partrack
Intrinsic Parallelogram Function of VPOS Subaddress 06
Control (tracking between VPOS and
DHPC) with Max. VAMP, Max. SPB and
Parallelogram inhibited (17 & 18)
Byte x0000000
B/A Ratio
Byte x1111111
A/B Ratio
0.52
0.52
SPBpara
SPBtrack
Side Pin Balance Parabola Amplitude
(Figure 3) with Max. VAMP, Typ. VPOS
and Parallelogram inhibited (17 & 18)
Side Pin Balance Parabola Amplitude
function of VAMP Control (tracking between VAMP and SPB) with Max. SPB,
Typ. VPOS and Parallelogram inhibited
(17 & 18)
12/43
TDA9111
Note: 16 These parameters are not tested on each unit. They are measured during our internal qualification procedure.
Note: 17 With Register 07 at Byte 0xxxxxxx (S correction inhibited) and Register 08 at Byte 0xxxxxxx (C correction
inhibited), the sawtooth has a linear shape.
MOIRE CANCELLATION SECTION
Electrical Characteristics (V CC = 12V, Tamb = 25°C)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
HORIZONTAL AND VERTICAL MOIRE
RMOIRE
DacOut
HMOIRE
THMOIRE
VMOIRE
Minimum Output Resistor to GND
Pin 3
DC Voltage pin 3
DAC configuration
RMOIRE = 4.7kΩ
sub-address 02
Byte 00000000
Byte 01000000
Byte 01111111
4.7
kΩ
0.3
1.1
2.75
RMOIRE = 4.7kΩ
Moiré pulse (See also Hunlock in 1st PLL Sub-address 02
section)
Byte 10000000
H Frequency: Locked
Byte 11000000
Byte 11111111
0
0.8
2.2
HMoiré pulse period pin 3
H Frequency: Locked
Sub-address II:
0xxx xxxx
1xxx xxxx
4.TH
2.TH
Vertical Moiré
(measured on VOUT: Pin 23)
Sub-address 0C
Byte 11111111
6
3
V
V
V
VPP
VPP
VPP
mV
Note: 18 TH is the horizontal period.
13/43
TDA9111
B+ SECTION
Operating Conditions
Symbol
FeedRes
Parameter
Minimum Feedback Resistor
Test Conditions
Min.
Resistor between Pins 15
and 14
5
Typ.
Max.
Units
kΩ
Electrical Characteristics (VCC = 12V, Tamb = 25°C)
Symbol
OLG
Parameter
Test Conditions
Error Amplifier Open Loop Gain
At low frequency
Unity Gain Bandwidth
See (19)
IRI
Feedback Input Bias Current
Current sourced by Pin 15
(PNP base)
EAOI
Error Amplifier Output Current
Current sourced by Pin 14
Current sunk by
Pin 14 (20)
CSG
Current Sense Input Voltage Gain
Pin 16
UGBW
MCEth
ISI
Max Current Sense Input Threshold VoltPin 16
age
Current Sense Input Bias Current
Min.
(19)
Current sunk by Pin 16
(PNP base)
Typ.
Max.
Units
85
dB
6
MHz
0.2
µA
1.4
mA
2
mA
3
1.3
V
1
µA
Tonmax
Maximum ON Time of the external power % of horizontal period,
transistor
fo = 27kHz) (21)
100
%
B+OSV
B+Output Saturation Voltage
V 28 with I28 = 10mA
0.25
V
Internal Reference Voltage
On error amp (+)
input Subaddress OB:
Byte 1000000
5
V
VREFADJ
Internal Reference Voltage Adjustment
Range
Byte 01111111
Byte 00000000
+20
-20
%
%
PWMSEL
Threshold for step-up/step-down selection (step-up configuration if V16 < PWM- Pin 16
SEL)
6
V
100
ns
IVREF
tFB+
Fall Time
Pin 28
Note: 19 These parameters are not tested on each unit. They are measured during our internal qualification procedure
which includes characterization on batches coming from corners of our process and also temperature
characterization.
Note: 20 To make soft start possible, 0.5mA are sunk when B+ is disabled.
Note: 21 The external power transistor is OFF during 400ns of the HFOCUSCAP discharge
14/43
TDA9111
Figure 1. Vertical Dynamic Focus Function
Figure 2. E/W Output
Figure 3. Dynamic Horizontal Phase Control
Figure 4. Keystone Effect on E/W Output (PCC Inhibited)
15/43
TDA9111
TYPICAL OUTPUT WAVEFORMS
Function
Sub
Address
Pin
Byte
Specification
10000000
Vertical Size
05
23
11111111
Vertical
Position
DC Control
06
00000000
VOUTDC = 3.2V
01000000
VOUTDC = 3.6V
01111111
VOUTDC = 4.0V
23
0xxxxxxx:
Inhibited
Vertical
S
Linearity
07
23
∆V
11111111
16/43
VPP
∆V
= 3.5%
V PP
Effect on Screen
TDA9111
Function
Sub
Address
Pin
Byte
Specification
Effect on Screen
0xxxxxxx :
Inhibited
Vertical
C
Linearity
08
∆V
23
10000000
VPP
DV =-3%
VPP
11111111
V PP
DV =+3%
VPP
x1111111
4.2V
Horizontal
Size
11
24
x0000000
Horizontal
Dynamic
Focus with:
03
10
X000 0000 —
X111 1111 ---
Amplitude
Horizontal
Dynamic
Focus with:
2V
04
10
X000 0000 —
X111 1111 ---
Symmetry
17/43
TDA9111
Function
Sub
Address
Pin
Byte
Specification
Effect on Screen
(E/W + Corner Inhibited)
Keystone
(Trapezoid)
Control
09
10000000
0.4V
EWDC
11111111
0.4V
EW DC
24
(Keystone + Corner Inhibited)
E/W
(Pin
Cushion)
Control
10000000
0A
EWDC
0V
24
1.4V
11111111
EWDC
(Keystone + E/W Inhibited)
1.25V
11111111
Corner
Control
EW DC
10
24
EW DC
10000000
1.25V
Parallelogram
Control
0E
Internal
(SPB Inhibited)
10000000
2.8% TH
11111111
2.8% TH
(Parallelogram Inhibited)
Side Pin
Balance
Control
18/43
10000000
2.8% TH
11111111
2.8% TH
0D
TDA9111
Function
Sub
Address
Pin
Byte
Specification
Effect on Screen
X111 1111
2.1V
TV
Vertical
Dynamic
Focus with
Horizontal
0F
10
X000 0000
0V
2.1V
TV
19/43
TDA9111
I2C BUS ADDRESS TABLE
Slave Address (8C): Write Mode
Sub Address Definition
D8
D7
D6
D5
D4
D3
D2
D1
0
0
0
0
0
0
0
0
0
Horizontal Drive Selection/Horizontal Duty Cycle
1
0
0
0
0
0
0
0
1
X-ray Reset/Horizontal Position
2
0
0
0
0
0
0
1
0
Horizontal Moiré/H Lock
3
0
0
0
0
0
0
1
1
Sync. Priority/Horizontal Focus Amplitude
4
0
0
0
0
0
1
0
0
Refresh/Horizontal Focus Symmetry
5
0
0
0
0
0
1
0
1
Vertical Ramp Amplitude
6
0
0
0
0
0
1
1
0
Vertical Position Adjustment
7
0
0
0
0
0
1
1
1
S Correction
8
0
0
0
0
1
0
0
0
C Correction
9
0
0
0
0
1
0
0
1
E/W Keystone
A
0
0
0
0
1
0
1
0
E/W Amplitude
B
0
0
0
0
1
0
1
1
B+ Reference Adjustment
C
0
0
0
0
1
0
0
0
Vertical Moiré
D
0
0
0
0
1
0
0
1
Side Pin Balance
E
0
0
0
0
1
0
1
0
Parallelogram
F
0
0
0
0
1
0
1
1
Vertical Dynamic Focus Amplitude
10
0
0
0
1
0
0
0
0
E/W Corner
11
0
0
0
1
0
0
0
1
H. Moiré Frequency/Horizontal Size Amplitude
Slave Address (8D): Read Mode: No sub address needed.
20/43
TDA9111
I2C BUS ADDRESS TABLE (continued)
D8
D7
D6
D5
D4
D3
D2
D1
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
WRITE MODE
00
HDrive
0, off
[1], on
Horizontal Duty Cycle
01
Xray
1, reset
[0]
[1]
[0]
[0]
02
HMoiré/HLock
1, on
[0], off
[0]
[0]
[0]
03
Sync
0, Comp
[1], Sep
[1]
[0]
[0]
04
Detect
Refresh
[0], off
[1]
[0]
05
Vramp
0, off
[1], on
[1]
[0]
06
Test V
1, on
[0], off
07
S Select
1, on
[0]
[1]
[0]
[0]
08
C Select
1, on
[0]
[1]
[0]
[0]
09
E/W Key
0, off
[1]
[1]
[0]
[0]
0A
E/W Sel
0, off
[1]
[1]
[0]
[0]
0B
Test H
1, on
[0], off
[1]
[0]
[0]
0C
V. Moiré
1, on
[0]
[0]
[0]
[0]
0D
SPB Sel
0, off
[1]
[1]
[0]
[0]
0E
Parallelo
0, off
[1]
[0]
[0]
[0]
[0]
Horizontal Phase Adjustment
[0]
[0]
Horizontal Moiré Amplitude
[0]
[0]
Horizontal Focus Amplitude
[0]
[0]
Horizontal Focus Symmetry
[0]
[0]
[0]
Vertical Ramp Amplitu de Adjustment
[0]
[0]
[0]
Vertical Position Adjustment
[1]
[0]
[0]
[0]
S Correction
[0]
C Correction
[0]
E/W Keystone
[0]
E/W Amplitude
[0]
B + Reference Adjustment
[0]
[0]
Vertical Moiré Amplitude
[0]
Side Pin Balance
[0]
Parallelogram
[1]
[0]
[0]
[0]
21/43
TDA9111
D8
D7
D6
D5
D4
D3
D2
D1
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
Vertical Dynamic Focus Amplitude
0F
Eq. Pulse
1, ignore TH/2
[0], accept all
[1]
[0]
[0]
10
Corner Sel
1, on
[0], off
[1]
[0]
[0]
11
H. Moiré Frequency
1 F/2
[0] F/4
[0]
E/W Corner
[0]
Horizontal Size Amplitu de
[1]
[0]
[0]
[0]
[0]
READ MODE
Hlock
0, on
[1], no
Vlock
0, on
[1], no
Xray
1, on
[0], off
Polarity Detection
Sync Detection
H/V pol
V pol
Vext det
[1], negative [1], negative [0], no det
H/V det
[0], no det
[x] initial value
Data is transferred with vertical sawtooth retrace.
We recommend setting the unspecified bits to [0] in order to ensure compatibility with future devices.
22/43
V det
[0], no det
TDA9111
OPERATING DESCRIPTION
1 GENERAL CONSIDERATIONS
1.1 Power Supply
The typical values of the power supply voltages
VCC and VDD are 12 V and 5 V respectively. Optimum operation is obtained for VCC between 10.8
and 13.2 V and VDD between 4.5 and 5.5 V.
In order to avoid erratic operation of the circuit during the transient phase of VCC switching on, or off,
the value of V CC is monitored: if VCC is less than
7.5 V typ., the outputs of the circuit are inhibited.
Similarly, before VDD reaches 4 V, all the I2 C register are reset to their default value (see I 2C Control Table).
In order to have very good power supply rejection,
the circuit is internally supplied by several voltage
references (typ. value: 8.2 V). Two of these voltage references are externally accessible, one for
the vertical and one for the horizontal part. They
can be used to bias external circuitry (if ILOAD is
less than 5 mA). It is necessary to filter the voltage
references by external capacitors connected to
ground, in order to minimize the noise and consequently the “jitter” on vertical and horizontal output
signals.
1.2 I2C Control
TDA9111 belongs to the I2C controlled device
family. Instead of being controlled by DC voltages
on dedicated control pins, each adjustment can be
done via the I2C Interface.
The I2C bus is a serial bus with a clock and a data
input. The general function and the bus protocol
are specified in the Philips-bus data sheets.
The inputs (Data and Clock) are comparators with
a 2.2 V threshold at 5 V supply. Spikes of up to 50
ns are filtered by an integrator and the maximum
clock speed is limited to 400 kHz.
The data line (SDA) can be used bidirectionally. In
read-mode the IC sends reply information
(1 byte) to the micro-processor.
The bus protocol prescribes a full-byte transmission in all cases. The first byte after the start condition is used to transmit the IC-address (hexa 8C
for write, 8D for read).
1.3 Write Mode
In write mode the second byte sent contains the
subaddress of the selected function to adjust (or
controls to affect) and the third byte the corresponding data byte. It is possible to send more
than one data byte to the IC. If after the third byte
no stop or start condition is detected, the circuit increments automatically by one the momentary
subaddress in the subaddress counter (auto-increment mode). So it is possible to transmit immediately the following data bytes without sending the
IC address or subaddress. This can be useful to
reinitialize all the controls very quickly (flash manner). This procedure can be finished by a stop condition.
The circuit has 18 adjustment capabilities: 3 for the
horizontal part, 4 for the vertical, 3 for the
E/W correction, 2 for the dynamic horizontal phase
control, 2 for the vertical and horizontal Moiré options, 3 for the horizontal and the vertical dynamic
focus and 1 for the B+ reference adjustment.
18 bits are also dedicated to several controls (ON/
OFF, Horizontal Forced Frequency, Sync Priority,
Detection Refresh and XRAY reset).
1.4 Read Mode
During the read mode the second byte transmits
the reply information.
The reply byte contains the horizontal and vertical
lock/unlock status, the XRAY activation status,
and the horizontal and vertical polarity detection. It
also contains the sync detection status which is
used by the MCU to assign the sync priority. A
stop condition always stops all the activities of the
bus decoder and switches to high impedance both
the data and clock line (SDA and SCL).
See I2C subaddress and control tables.
1.5 Sync Processor
The internal sync processor allows the TDA9111
to accept:
– separated horizontal & vertical TTL-compatible
sync signal
– composite horizontal & vertical TTL-compatible
sync signal
1.6 Sync Identification Status
The MCU can read (address read mode: 8D) the
status register via the I2C bus, and then select the
sync priority depending on this status.
Among other data this register indicates the presence of sync pulses on H/HVIN, VSYNCIN and
(when 12 V is supplied) whether a Vext has been
extracted from H/HVIN. Both horizontal and vertical sync are detected even if only 5 V is supplied.
23/43
TDA9111
In order to choose the right sync priority the MCU
may proceed as follows (see I 2C Address Table):
– refresh the status register,
– wait at least for 20ms (Max. vertical period),
– read this status register.
Sync priority choice should be :
Vextd
et
H/V
det
V
det
Sync
priority
Subaddress
03 (D8)
Comment
Sync type
No
Yes
Yes
1
Separated H&V
Yes
Yes
No
0
Composite TTL
H&V
Of course, when the choice is made, we can refresh the sync detections and verify that the extracted Vsync is present and that no sync type
change has occurred. The sync processor also
gives sync polarity information.
1.7 IC status
The IC can inform the MCU about the 1st horizontal PLL and vertical section status (locked or not)
and about the XRAY protection (activated or
not).Resetting the XRAY internal latch can be
done either by decreasing the VCC supply or directly resetting it via the I2C interface.
1.8 Sync Inputs
Both H/HVIN and VSYNCIN inputs are TTL compatible triggers with hysteresis to avoid erratic detection. Both inputs include a pull up resistor connected to VDD.
1.9 Sync Processor Output
The sync processor indicates on the D8 bit of the
status register whether 1st PLL is locked to an incoming horizontal sync. Its level goes to low when
locked. This information is also available on pin 3 if
sub-address 02 D8 is equal to 1. When PLL1 is unlocked, pin 3 output voltage becomes greater than
6V. When it is locked, the HMoiré waveform is
available on pin 3 (max voltage: 3V).
2 HORIZONTAL PART
2.1 Internal Input Conditions
A digital signal (horizontal sync pulse or TTL composite) is sent by the sync processor to the horizontal input. It may be positive or negative (see
Figure 5).
Using internal integration, both signals are recognized if Z/T < 25%. Synchronization occurs on the
leading edge of the internal sync signal.
The minimum value of Z is 0.7 µs.
Figure 6.
CSync
Integ.
d
VSyn
24/43
Another integration is able to extract the vertical
pulse from composite sync if the duty cycle is higher than 25% (typically d = 35%),
(see Figure 6).
Figure 5.
TDA9111
The last feature performed is the removal of these
equalization pulses which fall in the middle of a
line, to avoid parasitic pulses on the phase comparator (which would be disturbed by missing or extraneous pulses). This last feature is switched on/
off by sub-address 0F D8. By default [0], equalization pulses will not be removed.
2.2 PLL1
The PLL1 consists of a phase comparator, an external filter and a voltage-controlled oscillator
(VCO).The phase comparator is a “phase/frequency” type designed in CMOS technology. This kind
of phase detector avoids locking on wrong frequencies. It is followed by a “charge pump”, composed of two current sources : sunk and sourced
(typically I =1 mA when locked and I = 140 µA
when unlocked). This difference between lock/unlock allows smooth catching of the horizontal frequency by PLL1. This effect is reinforced by an internal original slow down system when PLL1 is
locked, avoiding the horizontal frequency changing too quickly. The dynamic behavior of PLL1 is
fixed by an external filter which integrates the cur-
rent of the charge pump. A “CRC” filter is generally
used (see Figure 7 on page 25).
Figure 7.
PLL1F
7
1.8kΩ
10nF
The PLL1 is internally inhibited during extracted
vertical sync (if any) to avoid taking in account
missing pulses or wrong pulses on phase comparator. Inhibition is obtained by stopping high and
low signals at the input of the charge pump block
(see Figure 8 on page 25).
Figure 8.
Lock/Unlock
Status
LOCKDET
H/HVIN 1
CHARGE
PUMP
COMP1
Low
PLL1F
R0
C0
7
6
5
PLL
INHIBITION
High
INPUT
INTERFACE
Extracted
VSync
VCO
HPOSITION
OSC
Extracted
VSync
PHASE
ADJUST
I2C
HPOS
Adj.
25/43
TDA9111
Figure 9.
I0
I0
2
6.4V
PLL1F
7
(Loop Filter)
RS
FLIP FLOP
1.6V
4 I0
6
(1.4V<V7<6.4V)
R0
5
6.4V
C0
1.6V
0 0.875THT H
The VCO uses an external RC network. It delivers
a linear sawtooth obtained by the charge and the
discharge of the capacitor, with a current proportional to the current in the resistor. The typical
thresholds of the sawtooth are 1.6 V and 6.4 V.
The control voltage of the VCO is between 1.4 V
and 6.4 V (see Figure 9). The theoretical frequency range of this VCO is in the ratio of 1 to 4.5. The
effective frequency range has to be smaller (1 to
4.2) due to clamp intervention on the filter lowest
value.
The sync frequency must always be higher than
the free running frequency. For example, when using a sync range between 25 kHz and 100 kHz,
the suggested free running frequency is 22 kHz.
PLL1 ensures the coincidence between the leading edge of the sync signal and a phase reference
REF1 obtained by comparison between the sawtooth of the VCO and an internal DC voltage Vb.
Vb is I2C adjustable between 2.9 V and 4.2 V (corresponding to ±10 %) (see Figure 10).
The TDA9111 also includes a Lock/Unlock identification block which senses in real time whether
PLL1 is locked or not on the incoming horizontal
sync signal. This information is available through
26/43
I2C, and also on pin 3 if HLock/Unlock option has
been set through Subaddress 02,D8.
Figure 10. PLL1 Timing Diagram
H O SC
Sawtooth
7/8 TH
1/8 TH
6.4V
Ref. for H Position
Vb
(2.9V<Vb<4.2V)
1.6V
REF1
HSync
Phase REF1 is obtained by comparison between
the sawtooth and a DC voltage adjustable between
2.9 V and 4.2 V.
The PLL1 ensures the exact coincidence between the
signal phase REF and HSYNC. A ±10% TH phase
adjustment is possible around the 3.5V point.
TDA9111
2.3 PLL2
PLL2 ensures a constant position of the shaped
flyback signal in comparison with the sawtooth of
the VCO, taking into account the saturation time
Ts (see Figure 11)
Figure 11. PLL2 Timing Diagram
HOsc
Sawtooth
7/8TH
1/8 TH
6.4V
4.0V
1.6V
Flyback
The maximum storage time (Ts Max.) is (0.44THTFLY/2). Typically, TFLY/TH is around 20 %, at
maximum frequency, which means that Ts max is
around 34 % of TH.
2.4 Output Section
The H-drive signal is sent to the output through a
shaping stage which also controls the H-drive duty
cycle (I2C adjustable) (see Figure 11). In order to
secure the scanning power part operation, the output is inhibited in the following cases:
– when VCC or VDD are too low
– when the XRAY protection is activated
– during the Horizontal flyback
– when the HDrive I2C bit control is off.
The output stage consists of a NPN bipolar transistor. Only the collector is accessible (see
Figure 13).
Figure 13.
Internally
shaped Flyback
HDrive
Ts
Duty Cycle
The phase comparator of PLL2 is followed by a
charge pump (typical output current: 0.5 mA).
The flyback input consists of an NPN transistor.
The input current must be limited to less than 5 mA
(see Figure 12).
Figure 12. Flyback Input Electrical Diagram
500Ω
HFLY
Q1
12
20kΩ
GND 0V
The duty cycle is adjustable through I2C from 30 %
to 65 %. For a safe start-up operation, the initial
duty cycle (after power-on reset) is 65% in order to
avoid having too long a conduction period of the
horizontal scanning transistor.
This output stage is intended for “reverse” base
control, where setting the output NPN in off-state
will control the power scanning transistor in offstate.
The maximum output current is 30mA, and the
corresponding voltage drop of the output VCEsat is
0.4V Max.
Obviously the power scanning transistor cannot be
directly driven by the integrated circuit. An interface has to be added between the circuit and the
power transistor either of bipolar or MOS type.
2.5 X-RAY Protection
The X-Ray protection is activated by application of
a high level on the X-Ray input (more than 8.2V on
Pin 25). It inhibits the H-Drive and B+ outputs.
This activation is internally delayed by 2 lines to
avoid erratic detection when short parasitics are
present .
27/43
TDA9111
This protection is latched; it may be reset either by
VCC switch-off or by I2C (see Figure 14 on
page 28).
2.6 Horizontal and Vertical Dynamic Focus
For dynamic focus adjustment, the TDA9111 delivers the sum of two signals on pin 10:
– a parabolic waveform at horizontal frequency,
– a parabolic waveform at vertical frequency.
The horizontal parabola comes from a sawtooth in
phase advance with flyback pulse middle. The
Figure 14. Safety Functions Block Diagram
28/43
phase advance versus horizontal flyback middle is
kept constant versus frequency (about 1µs).
Symmetry and amplitude are I2C adjustable (see
Figure 15 on page 29). The vertical parabola is
tracked with VPOS and VAMP. Its amplitude can
be adjusted. It is also affected by S and C corrections. This positive signal once amplified is to be
sent to the CRT focusing grids.
Because the DC/DC converter is triggered by the
HFocus sawtooth, it is recommended to connect a
capacitor to pin 9, even if HFocus is not needed.
TDA9111
Figure 15. Phase of HFocus Parabola
Flyback pulse
1 µs
0.4 µs
H Focus sawtooth
0.6 µs
0.6 µs
127
64
H Focus parabola
I2C Code
(decimal)
45
0
0.475TH
0.16TH
2.7 Horizontal Moiré Output
The Horizontal Moiré output is intended to correct
a beat between the horizontal video pixel period
and the CRT pixel width.
The Moiré signal is a combination of the horizontal
and vertical frequency signals.
To achieve a Moiré cancellation, the Moiré output
has to be connected so as to modulate the horizontal position. We recommend introducing this
“Horizontal Controlled Jitter” on the ground side of
PLL2 capacitor where this “controlled jitter” will directly affect the horizontal position.
The amplitude of the signal is I2C adjustable. The
H-Moiré frequency can be chosen via the I2C.
64
45
0
127
0.16TH
When sub-address 11 D8=0, Fh is divided by 4.
This is recommended for separate scanning and
EHV. When D8=1, Fh is divided by 2, which gives
a better aspect in the case of common scanning
and EHV. The H-Moiré output is combined with the
PLL1 horizontal unlock output.
If HMoiré/HLock is selected:
– when PLL1 is unlocked, pin 3 output voltage
goes above 6V.
– when PLL1 is locked, the HMoiré signal (up to
2.2V peak) is present on pin 3.
If HMoiré/HLock is not selected, pin 3 can be used
as a 0....2.5V DAC.
29/43
TDA9111
3 VERTICAL PART
3.1 Function
When the synchronization pulse is not present, an
internal current source sets the free running frequency. For an external capacitor C OSC = 150nF,
the typical free running frequency is 100Hz.
The typical free running frequency can be calculated by:
1
fo(Hz) = 1.5 . 10-5 . C
OSC
A negative or positive TTL level pulse applied on
Pin 2 (VSYNC) as well as a TTL composite sync
on Pin 1 can synchronize the ramp in the range
[fmin, fmax] (See Figure 16 on page 31). This frequency range depends on the external capacitor
connected on Pin 22. A 150nF (± 5%) capacitor is
recommended for 50Hz to 185Hz applications.
If a synchronization pulse is applied, the internal
oscillator is synchronized immediately but with
wrong amplitude. An internal correction then adjusts it in less than half a second. The top value of
the ramp (Pin 22) is sampled on the AGC capacitor (Pin 20) at each clock pulse and a transconductance amplifier modifies the charge current of
the capacitor so as to adjust the amplitude to the
right value.
The Read Status register provides the vertical
Lock-Unlock and the vertical sync polarity information.
We recommend to use an AGC capacitor with low
leakage current. A value lower than 100nA is mandatory.
30/43
A good stability of the internal closed loop is
reached with a 470nF ± 5% capacitor value on Pin
20 (VAGC).
3.2 I2C Control Adjustments
S and C correction shapes can then be added to
this ramp. These frequency-independent S and C
corrections are generated internally. Their amplitudes are adjustable by their respective I2C registers. They can also be inhibited by their select bits.
Finally, the amplitude of this S and C corrected
ramp can be adjusted by the vertical ramp amplitude control register.
The adjusted ramp is available on Pin 23 (VOUT) to
drive an external power stage.
The gain of this stage can be adjusted (± 25%) depending on its register value.
The mean value of this ramp is driven by its own
I2C register (vertical position). Its value is
VPOS = 7/16 . VREF-V ± 400mV.
Usually VOUT is sent through a resistive divider to
the inverting input of the booster. Since VPOS derives from VREF-V, the bias voltage sent to the noninverting input of the booster should also derive
from VREF-V to optimize the accuracy (see Application Diagram).
3.3 Vertical Moiré
By using the vertical Moiré, VPOS can be modulated from frame to frame. This function is intended
to cancel the fringes which appear when the line to
line interval is very close to the CRT vertical pitch.
The amplitude of the modulation is controlled by
register VMOIRE on sub-address 0C and can be
switched-off via the control bit D8.
TDA9111
Figure 16. AGC Loop Block Diagram
3.4 Basic Equations
In first approximation, the amplitude of the ramp
on Pin 23 (VOUT) is:
VOUT - VPOS = (VOSC - VDCMID) . (1 + 0.3 (VAMP ))
where:
VDCMID = 7/16 VREF (middle value of the ramp
on Pin 22, typically 3.6V)
VOSC = V22 (ramp with fixed amplitude)
VAMP = -1 for minimum vertical amplitude register value and +1 for maximum
VPOS is calculated by:
VPOS = VDCMID + 0.4 VP
where VP = -1 for minimum vertical position register value and +1 for maximum.
The current available on Pin 22 is:
3 .
IOSC =
VREF x COSC x f
8
where COSC = capacitor connected on Pin 22 and
f = synchronization frequency.
3.5 Geometric Corrections
The principle is represented in Figure 17 on
page 32.
Starting from the vertical ramp, a parabola-shaped
current is generated for E/W correction (also
known as Pin Cushion correction), dynamic horizontal phase control correction, and vertical dynamic focus correction.
The parabola generator is made by an analog multiplier, the output current of which is equal to:
DI = k .(VOUT - VDCMID)2
where VOUT is the vertical output ramp (typically
between 2 and 5V) and VDCMID is 3.6V
(for VREF-V = 8.2V). The VOUT sawtooth is typically centered on 3.6V. By changing the vertical position, the sawtooth shifts by ± 0.4V.
To provide good screen geometry for any end user
adjustment, the TDA9111 has the “geometry
tracking” feature which automatically adapts the
parabola shape, depending on the vertical position
and size.
31/43
TDA9111
Due to the large output stage voltage range (E/W
Pin Cushion, Keystone, E/W Corner), the combination of the tracking function, maximum
vertical amplitude, maximum or minimum vertical
position and maximum gain on the DAC control
may lead to output stage saturation. This must be
avoided by limiting the output voltage with appropriate I2C register values.
For the E/W part and the dynamic horizontal
phase control part, a sawtooth-shaped differential
current in the following form is generated:
∆I’ = k’ . (VOUT - VDCMID)
Then ∆I and ∆I’ are added and converted into voltage for the E/W part.
Each of the three E/W components or the two dynamic horizontal phase control components may
be inhibited by their own I2C select bit.
The E/W parabola is available on Pin 24 via an
emitter follower output stage which has to be biased by an external resistor (10kΩ to ground).
Since stable in temperature, the device can be DC
coupled with external circuitry (mandatory to obtain H Size control).
The vertical dynamic focus is combined with the
horizontal focus on Pin 10.
The dynamic horizontal phase control drives internally the H-position, moving the HFLY position on
the horizontal sawtooth in the range of ± 2.8 %TH
both for side pin balance and parallelogram.
Figure 17. Geometric Corrections Principle
3.6 E/W
EWOUT = EWDC + K1 (VOUT - VDCMID) +
K2 (VOUT - VDCMID)2+ K3 (VOUT - VDCMID)4
32/43
K1 is adjustable by the keystone I2C register.
K2 is adjustable by the E/W amplitude I2C register.
K3 is adjustable by the E/W corner I2C register.
TDA9111
3.7 Dynamic Horizontal Phase Control
IOUT= K4 (VOUT - VDCMID) + K5 (VOUT - VDCMID)2
K4 is adjustable by the parallelogram I2C register.
K5 is adjustable by the side pin balance I2C register.
4 DC/DC CONVERTER PART
This unit controls the switch-mode DC/DC converter. It converts a DC constant voltage into the
B+ voltage (roughly proportional to the horizontal
frequency) necessary for the horizontal scanning.
This DC/DC converter can be configured either in
step-up or step-down mode. In both cases it operates very similarly to the well known UC3842.
4.1 Step-up Mode
Operating Description
– The power MOS is switched ON during the flyback (at the beginning of the positive slope of the
horizontal focus sawtooth).
– The power MOS is switched OFF when its current reaches a predetermined value. For this purpose, a sense resistor is inserted in its source.
The voltage on this resistor is sent to Pin16
(ISENSE).
– The feedback (coming either from the EHV or
from the flyback) is divided to a voltage close to
5.0V and compared to the internal 5.0V reference (IVREF). The difference is amplified by an
error amplifier, the output of which controls the
power MOS switch-off current.
Main Features
– Switching synchronized on the horizontal frequency,
– B+ voltage always higher than the DC source,
– Current limited on a pulse-by-pulse basis.
The DC/DC converter is disabled:
– when VCC or VDD are too low,
– when X-Ray protection is latched,
– directly through I2C bus.
When disabled, BOUT is driven to GND by a
0.5mA current source. This feature allows to implement externally a soft start circuit.
4.2 Step-down Mode
In step-down mode, the ISENSE information is not
used any more and therefore not sent to the
Pin16. This mode is selected by connecting this
Pin16 to a DC voltage higher than 6V (for example
VREF-V).
Operating Description
– The power MOS is switched ON as for the stepup mode.
– The feedback to the error amplifier is done as for
the step-up mode.
– The power MOS is switched OFF when the HFOCUSCAP voltage gets higher than the error amplifier output voltage.
Main Features
– Switching synchronized on the horizontal frequency,
– B+ voltage always lower than the DC source,
– No current limitation.
4.3 Step-up and Step-down Mode Comparison
In step-down mode the control signal is inverted
compared with the step-up mode.This, for the following reason:
– In step-up mode, the switch is a N-channel MOS
referenced to ground and made conductive by a
high level on its gate.
– In step-down, a high-side switch is necessary. It
can be either a P- or a N-channel MOS.
• For a P-channel MOS, the gate is controlled
directly from Pin 28 through a capacitor (this
allows to spare a Transformer). In this case,
a negative-going pulse is needed to make
the MOS conductive. Therefore it is
necessary to invert the control signal.
• For a N-channel MOS, a transformer is
needed to control the gate. The polarity of
the transformer can be easily adapted to the
negative-going control pulse.
33/43
TDA9111
Figure 18. DC/DC Converter (represented: Step-Up configuration)
I 2C
DAC
7bits
± I adjust
-
+
85 dB
- A
1/3
1.3V
BOUT
C1
down
+
-
down
C2
22kΩ
14
1MΩ
EHV
Feedback
VB+
34/43
ISENSE
COMP
15
up
B+ Inhibit.
+
C4
Command step-up/down
-
TDA9111
16
L
Q
up
6V
8V
S
R
+
C3
-
1.3V
REGIN
12V
+
8.2V
5V ±20%
HDF Discharge
400ns
Horizontal Dynamic
Focus Sawtooth
28
TDA9111
INTERNAL SCHEMATICS
Figure 22.
Figure 19.
12V
5V
HREF
20 kΩ
13
Pins 1-2
H/HVIN
VSYNCIN
CO 5
200Ω
Figure 23.
Figure 20.
HREF
13
12V
12V
R0 6
HMOIRE/HLOCK 3
Figure 21.
Figure 24.
12V
HREF
13
PLL1F 7
PLL2
4
35/43
TDA9111
Figure 28.
Figure 25.
HREF
13
HREF
12V
12V
8
HPOSITION
HFLY 12
Figure 26.
Figure 29.
12V
HREF
13
HFOCUS 9
CAP
COMP 14
Figure 30.
Figure 27.
12V
12V
12V
REGIN 15
HFOCUS 10
36/43
TDA9111
Figure 31.
Figure 34.
12V
12V
VCAP 22
ISENSE 16
Figure 32.
Figure 35.
12V
12V
BREATH
18
VOUT 23
Figure 33.
Figure 36.
12V
12V
EWOUT
24
VAGCCAP 20
37/43
TDA9111
Figure 37.
12V
XRAY
25
Figure 38.
V12
HOUT-BOUT
Pins 26-28
Figure 39.
Pins 30-31
SDA-SCL
38/43
TDA9111
Figure 40. Demonstration Board
J14
J16 J15
1
+12V
TP17
J12
+5V 32
C30
100µF
H FOCUS-EWOUT
9
24
C AP
C34
820 pF 5%
FOCUS
10
VOUT 23
OUT
L
47µH
R24
10kΩ
VCAP 22
12 HFLY
VREF 21
150nF
C16 (*)
J19
C 27
4 7µF
1
2
C33 HREF
100nF
3
4
JP1
CON4
C46
1nF
R5 0
1MΩ
14 COMP
R 89
33kΩ
R51
1kΩ
ISENSE
R4 5 33kΩ
R58
10Ω
1
C37
33pF
TILT
J13
C42
1µF
C43 +5V R30
47µF
10kΩ
E/W POWER STAGE
TP22
R31
27k (**) R38
R1 9
2.2Ω
J1
27 0kΩ
3W
R15
1k Ω
R17
43kΩ
(**)
Q1
Q2
BC557 BC 557
R33
4.7kΩ
C1 1220 pF
R18
10kΩ
(**)
E/W
Q3
TIP122
R52
3.9kΩ
C3
47µF
C4
100n F
C2
470nF 100nF
R2
5.6k Ω
C14
470µF
D1
1 n4004
C10
100µF
35V
C9
100n F
TP6
+12V
-12V
TP4 TP3
TP7
R1
1 2kΩ
IC1
TDA8172
C41
470pF
B+GND 17
C1
R3
220nF 1.5Ω
C10
-1 2V 470µF
C8
100nF R5
5.6Ω
J2
J3
J6
VGND19
C47
100pF
GND
2
+5V
R43
10kΩ
R9
470Ω
D10
1N4 148
C51
22µF
3
R49
22kΩ
C3 6
1µF
R37
27kΩ
R34
1kΩ
R 40
3 6kΩ
16 I SENSE
4
+12V
15 R EGIN BREATH 18
REGIN
5
D2
1N4 148
R7 10kΩ
C15
13 HREF VAGCCA P 20
C38
33p F
+12V
C12
11 HGND
PWM0
DYN
FOCUS
6
C45
10µF
IC3-STV9422
C49
100nF
8 H
XRAY 25
C17 470 nF POSITION
8MH z
R56
560kΩ
C48
10µF
HOUT
TP14
R25
1kΩ
PWM7
C31 4.7µF
FBLK
HOUT
R8
10 kΩ
PWM1
HOUT 26
PWM6
R53
1kΩ
C13 10n F
7 PLL1F
TEST
+12V
R36 1.8 kΩ
7
X1
R23
(***)
R35
+12V 10kΩ
8
V DD
GND 27
12 11 10 9
VSYNC
6 R0
+12V
B
B+OUT 28
PXCK
5 C0
C5
100µF
HSYNC
C28
820pF 5%
G
VCC 29
C6
100nF
C7 22n F
R
R78
10Ω
CKOUT
4 PLL2C
13 14 15 16 17 18 19 20 21 22 23 2 4
GND
SCL 30
SDA
RST
3 H Lock out
SCL
SDA XTALOUT
SDA 31
PWM2
2 VSYNCIN
C40
22pF
XTALIN
8
C25
33pF
J9
R41
100Ω
C32
100n F
SCL
7
PC2
47kΩ
HFL Y
R2 9
R42
4.7kΩ 100Ω
PWM3
QA
GND
6
C 22
33pF
C39
22pF
R39
4.7kΩ
PWM5
ICC1
MC1 4528
QB
QB
IA
IA
5
R 90
1 0k
(∗∗)
+12V R10
10kΩ
J8
L1
22µH
PWM4
9
QA
4
IB
IB
TA2
3
CDB
TA1
TB2 CDA
TB1
VCC
2
3 4
+5V
+5V
TP10
16 15 14 13 12 11 10
CC 4
47 pF
TP16
-12V
1
TP1
1 H/HVIN
PC1
47kΩ
CC3
47pF
CC1
100nF
J11
TP13
CC2
10µF
IC4
TDA9111
2
1
R1 1
VYOKE 2
220Ω
0.5 W
3
J18
R4
1Ω
0.5 W
VER TICA L D EFLECTION STAGE
Q4
BC557
J17
B+OUT
+12V
TP8
EHT
COMP
R73
R 75 1MΩ
1 0kΩ
R76
47kΩ
D9
1 N4148
R74
10kΩ
P1
10kΩ
R77
15kΩ
C60
100nF
D8
1N41 48
Q5
BC54 7
HOUT
L3
22µH
+12V
C50
10µF
(*) o ptional
(**) see tabl e
9109A
91 11
R78
Short ed
Mou nted
R90
Remove d
Mou nted
R31
Mount ed
Removed
R17
270kΩ
43kΩ
R18
39kΩ
10kΩ
(***)
For R23=6.49kΩ f 0=22.8 kHz typ
For R23=5.23kΩ f 0=28.3 kHz typ
39/43
TDA9111
Figure 41.
40/43
TDA9111
Figure 42.
41/43
TDA9111
PACKAGE MECHANICAL DATA
32 PINS - PLASTIC SHRINK
E
A
A1
A2
E1
L
C
B
e
B1
Stand-off
eA
eB
D
32
17
1
16
Dimensions
Millimeters
Typ.
Max.
3.759
5.080
Min.
Typ.
Max.
0.140
0.148
0.200
A
3.556
A1
0.508
A2
3.048
3.556
4.572
0.120
0.140
0.180
B
0.356
0.457
0.584
0.014
0.018
0.023
B1
0.762
1.016
1.397
0.030
0.040
0.055
C
.203
0.254
0.356
0.008
0.010
0.014
D
27.43
27.94
28.45
1.080
1.100
1.120
E
9.906
10.41
11.05
0.390
0.410
0.435
E1
7.620
8.890
9.398
0.300
0.350
0.370
0.020
e
1.778
eA
10.16
eB
L
42/43
Inches
Min.
0.070
0.400
12.70
2.540
3.048
3.810
0.500
0.100
0.120
0.150
TDA9111
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no
responsibility for the consequences of use of such information nor for any infringement of patents or other
rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of STMicroelectronics. Specifications mentioned in this public ation are subject to change
witho ut notice. This publication supersedes and replaces all information previously supplied.
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