HV510 240V, 12-Channel Serial to Parallel Converter with High Voltage Push-Pull Outputs Ordering Information Package Options Device Recommended Operating VPP Max 24 Lead SOW Die HV510 240V HV510WG HV510X Features General Description ❏ HVCMOS® technology The HV510 is a low voltage serial to high voltage parallel converter with 12 high voltage push-pull outputs. This device has been designed to drive small capacitive loads such as piezo electric transducers. It can also be used in any application requiring multiple high voltage outputs, low current sourcing and sinking capabilities. ❏ Operating output voltage of 240V ❏ Low power level shifting from 5V to 240V ❏ Shift register speed 8MHz @ VDD = 5V The device consists of a 12-bit shift register, 12 latches, and control logic to perform the polarity select and blanking of the outputs. A DIR pin controls the direction of data shift through the device. With DIR grounded, DIOA is Data In and DIOB is Data Out; data is shifted from HVOUT12 to HVOUT1. When DIR is at logic high, DIOB is Data In and DIOA is Data Out: data is then shifted from HVOUT1 to HVOUT12. Data is shifted through the shift register on the low to high transition of the clock. Data output buffers are provided for cascading devices. Operation of the shift register is not affected by the LE, BL, or the POL inputs. Transfer of data from the shift register to the latch occurs when the LE is high. The data in the latch is stored during LE transition from high to low. ❏ 12 latched data outputs ❏ Output polarity and blanking ❏ CMOS compatible inputs ❏ Forward and reverse shifting options Absolute Maximum Ratings1 Supply voltage, VDD -0.5V to +6V Supply voltage, VPP VDD to 260V Logic input levels Ground -0.5V to VDD +0.5V current3 High voltage supply 0.3A current2 Continuous total power dissipation3 Operating temperature range Storage temperature range 0.25A 750mW -40°C to +85°C -65°C to +150°C Notes: 1. All voltages are referenced to GND. 2. Connection to all power and ground pads is required. Duty cycle is limited by the total power dissipated in the package. 3. For operation above 25°C ambient derate linearly to 85°C at 12mW/°C. 12/13/01 Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the 1 refer to the most current databook or to the Legal/Disclaimer page on the Supertex website. Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, HV510 Electrical Characteristics (for V DD = 5V, VPP = 240V, TA = 250C) DC Characteristics Symbol Parameter Min Typ VDD supply current IDD Max 4 Units mA Conditions fCLK = 8MHz, fDATA = 4MHz LE = LOW IDDQ Quiescent VDD supply current 200 µA All VIN = 0V or VDD IPP High voltage supply current 0.25 mA VPP = 240V All outputs high 0.25 mA VPP = 240V All outputs low IIH High-level logic input current 10 µA VIH = VDD IIL Low-level logic input current -10 µA VIL = 0V VOH High-level output 220 V VPP = 240V, IHVOUT = -0.5mA 175 V VPP = 200V, lHVOUT = -0.5mA VDD -1V V IDOUT = -100µA HVOUT Data out VOL VOC IOH Low-level output HVOUT 25 V VDD = 5V, IHVOUT = 1mA Data out 1.0 V IDOUT = 100µA VPP +1.5 V IOL = 1mA -1.5 V IOL = -1mA 1.0 mA VPP = 240V 0.8 mA VPP = 200V HVOUT clamp voltage Output Source Current AC Characteristics1 (For VDD = 5V, VPP = 200V, TA = 25°C) Symbol fCLK Parameter Min Typ Clock frequency Max Units 8 MHz tW Clock width high and low 62 ns tSU Data setup time before clock rises 35 ns tH Data hold time after clock rises 30 ns tWLE Width of latch enable pulse 80 ns tDLE LE delay time after rising edge of clock 35 ns tSLE LE setup time before rising edge of clock 40 tON, tOFF Conditions ns Time from latch enable to HVOUT 6.0 µs CL = 20pF tDHL Delay time clock to data out high to low 125 ns CL = 20pF tDLH Delay time clock to data out low to high 125 ns CL = 20pF tr, tf All logic inputs 5 ns Note: 1. Shift register speed can be as low as DC as long as Data Set-up and Hold Time meet the spec. Recommended Operating Conditions Symbol Parameter Min Typ Max Units 5.0 5.5 V VDD Logic supply voltage 4.5 VPP High voltage supply 60 240 V VIH High-level input voltage VDD -0.9 VDD V VIL Low-level input voltage 0 0.9 V TA Operating free-air temperature -40 +85 °C Notes: Power-up sequence should be the following: 1. Connect ground. 2. Apply VDD. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. 4. 5. Apply VPP. The VPP should not drop below VDD or float during operation. Power-down sequence should be the reverse of the above. 2 HV510 Input and Output Equivalent Circuits VDD VDD VPP Data Out Input HVOUT GND GND HVGND Logic Data Output Logic Inputs High Voltage Outputs Switching Waveforms VIH Data In (DIOA/DIOB) 50% Data Valid 50% VIL tSU tH VIH CLK 50% 50% 50% tWL 50% VIL tWH VOH 50% VOL tDLH Data Out (D IOA/D IOB) VOH 50% VOL tDHL LE VIH 50% 50% VOL tDLE tWLE tSLE 90% 10% HV OUT w/ S/R LOW VOH VOL tOFF HV OUT w/ S/R HIGH 10% tON 3 90% VOH VOL HV510 Functional Block Diagram POL VPP BL LE DIOA L/T HVOUT1 CLK L/T HVOUT2 L/T • • • 8 Additional Outputs • • • HVOUT11 L/T HVOUT12 DIR 12-bit Static Shift Register 12 Latches L/T = Level Translator DIOB Function Table Inputs Function Data CLK LE Outputs BL POL DIR Shift Reg HV Outputs 1 2…12 1 2…12 Data Out * All on X X X L L X * *…* H H…H * All off X X X L H X * *…* L L…L * Invert mode X X L H L X * *…* * *…* * Load S/R H or L ↑ L H H X H or L *…* * *…* * Store data in latches X X ↓ H H X * *…* * *…* * X X ↓ H L X * *…* * *…* * Transparent latch mode L ↑ H H H X L *…* L *…* * H ↑ H H H X H *…* H *…* * DIOA ↑ X X X L Qn→ Qn-1 — DIOB DIOB ↑ X X X H Qn→ Qn+1 — DIOA I/O relation Notes: H = high level, L = low level, X = irrelevant, ↑ = low-to-high transition, ↓ = high-to-low transition. * = dependent on previous stage’s state before the last CLK or last LE high. 4 HV510 Package Outline Pin Configurations HV510 24 Pin SOW Package Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Function VPP DIOA BL POL VDD DIR LGND HVGND CLK LE DIOB VPP HVOUT12/1 HVOUT11/2 HVOUT10/3 HVOUT9/4 HVOUT8/5 HVOUT7/6 HVOUT6/7 HVOUT5/8 HVOUT4/9 HVOUT3/10 HVOUT2/11 HVOUT1/12 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 top view 24-pin SOW Note: Pin designation for DIR = H/L Example: for DIR = H, Pin 13 is HVOUT12 for DIR = L, Pin 13 is HVOUT1 5