Supertex inc. HV5530 32-Channel Serial to Parallel Converter With Open Drain Outputs Features ►► Processed with HVCMOS® technology ►► Sink current minimum 100mA ►► Shift register speed 8.0MHz ►► Polarity and Blanking inputs ►► CMOS compatible inputs ►► Forward and reverse shifting options ►► Diode to VPP allows efficient power recovery General Description The HV5530 is a low-voltage serial to high-voltage parallel converter with open drain outputs. This device has been designed for use as a driver for AC-electroluminescent displays. It can also be used in any application requiring multiple output high voltage current sinking capabilities such as driving inkjet and electrostatic print heads, plasma panels, vacuum fluorescent, or large matrix LCD displays. This device consists of a 32-bit shift register, 32 latches, and control logic to perform the polarity select and blanking of the outputs. Data is shifted through the shift register on the high to low transition of the clock. The HV5530 shifts in the counter clockwise direction when viewed from the top of the package. A data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register. Operation of the shift register is not affected by the LE (latch enable), BL (blanking), or the POL (polarity) inputs. Transfer of data from the shift register to the latch occurs when the LE (latch enable) input is high. The data in the latch is stored when LE is low. Functional Block Diagram POL BL LE HVOUT1 DATA IN Latch HVOUT2 CLK Latch 32-Bit Shift Register (Outputs 3 to 30 not shown) HVOUT31 Latch HVOUT32 DATA OUT Doc.# DSFP-HV5530 C072313 Latch Supertex inc. www.supertex.com HV5530 Pin Configuration Ordering Information Part Number Package Packing HV5530PG-G 44-Lead PQFP 96/Tray HV5530PG-G M919 44-Lead PQFP 500/Reel HV5530PJ-G 44-Lead PLCC 27/Tube HV5530PJ-G M903 44-Lead PLCC 500/Reel 44 -G denotes a lead (Pb)-free / RoHS compliant package 1 44-Lead PQFP Absolute Maximum Ratings (top view) Parameter Value Supply voltage, VDD 1 -0.5V to +15V Output voltage, VPP1 -0.5V to +315V Logic input levels Ground current2 40 1.5A 1200mW 3 Operating temperature range 44-Lead PLCC (top view) -40 C to +85 C O Storage temperature range O -65OC to +150OC Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Notes: 1. All voltages are referenced to VSS 2. Duty cycle is limited by the total power dissipated in the package 3. For operation above 25°C ambient derate linearly to maximum operating temperature at 20mW/°C. Recommended Operating Conditions Product Marking Top Marking YYWW HV5530PG LLLLLLLLL Bottom Marking CCCCCCCC AAA Parameter Min Max Units VDD Logic voltage supply 10.8 13.2 V -0.3 +300 V YYWW AAA HVOUT High voltage output *May be part of top marking 44-Lead PQFP Top Marking HV5530PJ VIH Input high voltage VDD -2.0 VDD V LLLLLLLLLL VIL Input low voltage 0 2.0 V Bottom Marking fCLK Clock frequency - 8.0 MHz TA Operating free-air temperature -40 +85 C YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = “Green” Packaging Package may or may not include the following marks: Si or Sym CCCCCCCCCCC YY = Year Sealed WW = Week Sealed L = Lot Number A = Assembler ID C = Country of Origin* = “Green” Packaging *May be part of top marking O Package may or may not include the following marks: Si or 44-Lead PLCC Power-Up Sequence Power-up sequence should be the following: 1. Connect ground 2. Apply VDD 3. Set all inputs to a known state Typical Thermal Resistance Power-down sequence should be the reverse of the above. Doc.# DSFP-HV5530 C072313 1 44 -0.5V to VDD +0.5V 1 Continuous total power dissipation 6 2 Package θja 44-Lead PQFP 51OC/W 44-Lead PLCC 37OC/W Supertex inc. www.supertex.com HV5530 Electrical Characteristics (over recommended operating conditions unless otherwise noted) DC Characteristics Sym Parameter Min Max Units Conditions IDD VDD supply current - 15 mA fCLK = 8.0MHz, FDATA = 4.0MHz IDDQ VDD supply current (quiescent) - 100 µA VIN = 0V Off state output current - 10 µA All outputs high, all SWS parallel IIH High-level logic input current - 1.0 µA VIH = VDD IIL Low-level logic input current - -1.0 µA VIL = 0V VDD -1.0V - V IDOUT = -100µA HVOUT - 15 V IHVOUT = +100mA DATA OUT - 1.0 V IDOUT = +100µA - -1.5 V IOL = -100mA Min Max Units Conditions - 8.0 MHz --- IO(OFF) VOH High-level output data out VOL Low-level output voltage VOC HVOUT clamp voltage AC Characteristics Sym (VDD = 12V, TC = 25OC) Parameter fCLK Clock frequency tW Clock width, high or low 62 - ns --- tSU Data set-up time before CLK falls 25 - ns --- tH Data hold time after CLK falls 10 - ns --- tON Turn-on time, HVOUT from enable - 500 ns RL = 2.0KΩ to VPP max. tDHL Delay time clock to data high to low - 100 ns CL = 15pF tDLH Delay time clock to data low to high - 100 ns CL = 15pF tDLE Delay time clock to LE low to high 50 - ns --- tWLE Width of LE pulse 50 - ns --- tSLE LE setup time before clock falls 50 - ns --- Input and Output Equivalent Circuits VDD VDD HVOUT DATA OUT DATA IN HVIN VSS VSS VSS Logic Inputs Doc.# DSFP-HV5530 C072313 Logic Data Output 3 High Voltage Outputs Supertex inc. www.supertex.com HV5530 Switching Waveforms VIH DATA IN 50% Data Valid 50% tSU CLK VIL tH VIH 50% 50% 50% tWH 50% tWL VOH 50% DATA OUT VOL tDLH VOH 50% VOL tDHL VIH 50% 50% LE tWLE tDLE VIL VIL tSLE VOH HVOUT w/ S/R HIGH 10% VOL tON Functional Table Inputs Function Outputs 2...32 1 2...32 L * *...* On On...On * L H * *...* Off Off...Off * L H L * *...* * *...* * ↓ L H H H or L *...* * *...* * X H or L ↑ H H * *...* * *...* * X H or L ↑ H L * *...* * *...* * L ↓ H H H L *...* Off *...* * H ↓ H H H H *...* On *...* * LE BL POL All on X X X L All off X X X Invert mode X X Load S/R H or L Transparent latch mode HV Outputs 1 CLK Load latches Shift Reg Data Out * Data Notes: H = high level, L = low level, X = irrelevant, ↓ = high-to-low transition, ↑ = low-to-high transistion. * dependent on previous stage’s state before the last CLK ↓ or last LE high. Doc.# DSFP-HV5530 C072313 4 Supertex inc. www.supertex.com HV5530 44-Lead PQFP Pin Description Pin # Function 1 HVOUT11 2 HVOUT12 3 HVOUT13 4 HVOUT14 5 HVOUT15 6 HVOUT16 7 HVOUT17 8 HVOUT18 9 HVOUT19 10 HVOUT20 11 HVOUT21 12 HVOUT22 13 HVOUT23 14 HVOUT24 15 HVOUT25 16 HVOUT26 17 HVOUT27 18 HVOUT28 19 HVOUT29 20 HVOUT30 21 HVOUT31 Description High voltage outputs. 22 HVOUT32 23 DATA OUTPUT 24 N/C 25 N/C 26 N/C 27 POL Inverts the polarity of the HVOUT pins 28 CLK Clock pin, shift registers shifts data on falling edge of input clock. 29 VSS Reference voltage, usually ground. 30 VDD Logic supply voltage. 31 LE 32 DATA INPUT 33 BL Blanking pin sets all HVout pins low or high depending upon state of polarity. See function table. 34 N/C No connect. 35 HVOUT1 36 HVOUT2 37 HVOUT3 38 HVOUT4 39 HVOUT5 40 HVOUT6 41 HVOUT7 42 HVOUT8 43 HVOUT9 44 HVOUT10 Doc.# DSFP-HV5530 C072313 Data output pin. No connect. Latch enable pin, data is shifted from shift register to latches on logic input high. Data input pin. High voltage outputs. 5 Supertex inc. www.supertex.com HV5530 44-Lead PLCC Pin Description Pin # Function 1 HVOUT16 2 HVOUT17 3 HVOUT18 4 HVOUT19 5 HVOUT20 6 HVOUT21 7 HVOUT22 8 HVOUT23 9 HVOUT24 10 HVOUT25 11 HVOUT26 12 HVOUT27 13 HVOUT28 14 HVOUT29 15 HVOUT30 16 HVOUT31 17 HVOUT32 18 DATA OUTPUT 19 N/C 20 N/C 21 N/C Description High voltage outputs. Data output pin. No connect. 22 POL Inverts the polarity of the HVOUT pins 23 CLK Clock pin, shift registers shifts data on falling edge of input clock. 24 VSS Reference voltage, usually ground. 25 VDD Logic supply voltage. 26 LE 27 DATA INPUT 28 BL Blanking pin sets all HVout pins low or high depending upon state of polarity. See function table. 29 N/C No connect. 30 HVOUT1 31 HVOUT2 32 HVOUT3 33 HVOUT4 34 HVOUT5 35 HVOUT6 36 HVOUT7 37 HVOUT8 38 HVOUT9 39 HVOUT10 40 HVOUT11 41 HVOUT12 42 HVOUT13 43 HVOUT14 44 HVOUT15 Doc.# DSFP-HV5530 C072313 Latch enable pin, data is shifted from shift register to latches on logic input high. Data input pin. High voltage outputs. 6 Supertex inc. www.supertex.com HV5530 44-Lead PQFP Package Outline (PG) 10.00x10.00mm body, 2.35mm height (max), 0.80mm pitch D D1 E1 E Note 1 (Index Area D1/4 x E1/4) 44 1 e b θ1 Top View View B A A2 Seating Plane A1 L L1 Side View L2 Gauge Plane θ Seating Plane View B Note: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. Symbol MIN Dimension NOM (mm) MAX A A1 A2 b D D1 E E1 1.95* 0.00 1.95 0.30 13.65* 9.80* 13.65* 9.80* - - 2.00 - 13.90 10.00 13.90 10.00 2.35 0.25 2.10 0.45 14.15* 10.20* 14.15* 10.20* e 0.80 BSC L 0.73 0.88 1.03 L1 L2 1.95 REF 0.25 BSC θ 0O 3.5O 7O JEDEC Registration MO-112, Variation AA-2, Issue B, Sep.1995. * This dimension is not specified in the JEDEC drawing. Drawings not to scale. Supertex Doc. #: DSPD-44PQFPPG, Version C041309. Doc.# DSFP-HV5530 C072313 7 Supertex inc. www.supertex.com HV5530 44-Lead PLCC Package Outline (PJ) .653x.653in body, .180in height (max), .050in pitch D D1 .048/.042 x 45O 1 6 44 .150max .056/.042 x 45O 40 Note 1 (Index Area) .075max E E1 Note 2 e .020max (3 Places) Top View Vertical Side View View B b1 A A1 Base .020min Plane A2 Seating Plane b Horizontal Side View R View B Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. Actual shape of this feature may vary. Symbol Dimension (inches) A A1 A2 b b1 D D1 E E1 MIN .165 .090 .062 .013 .026 .685 .650 .685 .650 NOM .172 .105 - - - .690 .653 .690 .653 MAX .180 .120 .083 .021 .036 .695 .656 .695 .656 † e .050 BSC R .025 .035 .045 JEDEC Registration MS-018, Variation AC, Issue A, June, 1993. † This dimension differs from the JEDEC drawing. Drawings not to scale. Supertex Doc. #: DSPD-44PLCCPJ, Version F031111. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to: http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. ©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-HV5530 C072313 8 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com