DATA SHEET D LND-SP64HV 32MHZ, 64 CHANNEL SERIAL TO PARALLEL CONVERTER WITH PUSH-PULL OUTPUTS Features ® HVCMOS Technology 5.0V CMOS Logic Output voltage up to +90V Low power level shifting 32MHz equivalent data rate Latched data outputs Forward and reverse shifting options (DIR pin) Diode to VPP allows efficient power recovery Outputs may be hot switched Hi-Rel processing available General Description The LND-SP64HV is a low voltage serial to high voltage parallel converter with push-pull outputs. The device has been designed for use as a driver for EL displays. It can also be used in any application requiring multiple output high voltage current sourcing and sinking capability such as driving plasma panels, vacuum fluorescent displays, or large matrix LCD displays. The device has 4 parallel 16-bit registers, permitting data rates 4x the speed of one (they are clocked together). There are also 64 latches and control logic to perform the polarity select and blanking of the outputs. HVOUT1 is connected to the first stage of the first shift register through the polarity and blanking logic. Data is shifted through the shift registers on the logic low to high transition of the clock. The DIR pin causes CCW shifting when connected to GND, and CW shifting when connected to VDD. A data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register (HVOUT64). Operation of the shift register is not affected by the (latch enable), (blanking), or the (polarity) inputs. Transfer of data from the shift registers to the latches occurs when the input is high. The data in the latches is stored when the is low. Functional Block Diagram Linear Dimensions, Inc. 445 East Ohio Street, Chicago IL 60611 USA tel 312.404.9283 fax 312.321.1830 www.lineardimensions.com LND-SP64HV Ordering Information Device LND-SP64HV Pin Configuration Package Options 80-Lead PQFP 20.00x14.00mm body 3.40mm height (max) 0.80mm pitch LND-SP64HV-PG-G -G indicates package is ROHS compliant (‘Green’) Absolute Maximum Ratings Parameter Supply voltage, VDD Output voltage, VPP Logic input levels Ground current1 Continuous total power dissipation2 Operating temperature range Storage temperature range Lead temperature3 Value -0.5V to +5.5V -0.5V to +90V -0.3V to VDD+0.3V 1.5A 1200mW -40°C to +85°C -65°C to 150°C 260°C 80-Lead PQFP (PG) (top view) Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. . Notes: 1. Limited by the total power dissipated in the package 2. For operation above 25°C ambient derate linearly to maximum 3. operating temperature at 20mW/°C. 1.6mm(1/16inch) from case for 10 seconds Recommended Operating conditions Sym VDD VPP VIH VIL fCLK TA Parameter Logic supply voltage Output voltage High-level input voltage Low-level input voltage Clock frequency per register Operating free-air temperature Min 4.5 8.0 VDD-0.5V 0 -40 Max 5.5 90 0.5 8.0 +85 Units V V V V MHz °C Notes: Power-up sequence should be the following: 1. Apply ground. 2. Apply VDD. 3. Set all inputs (DIN, CLK, Enable, etc.) to a known state. 4. Apply VPP. 5. The VPP should not drop below VDD or float during operation. Power-down sequence should be the reverse of the above Linear Dimensions, Inc. 445 East Ohio Street, Chicago IL 60611 USA tel 312.404.9283 fax 312.321.1830 www.lineardimensions.com LND-SP64HV DC Electrical Characteristics Sym Parameter IDD VDD supply current IPP High voltage supply current IDDQ VOH Quiescent VDD supply current High level output HVOUT Data out Low level output HVOUT Data out High-level logic input current Low-level logic input current VOL IIH IIL VOC Min Max Units 15 100 100 100 7.0 0.5 1.0 -1.0 mA µA µA µA V V V V µA µA 1.0 V 75 VDD 0.5 High voltage clamp diode Conditions Outputs high Outputs low All AC Electrical Characteristics (TA =85 C max, Logic signals and Data inputs have tr, tf Symbol fCLK tWL, tWH tSU tH tON, tOFF tDHL tDLH tDLE* tWLE tSLE Parameter Min Clock frequency Clock width high or low Data set-up time before clock rises Data hold time after clock rises Time from latch enable to HVOUT Delay time clock to data high to low Delay time clock to data low to high Delay time clock to low to high pulse widthOutput Turn-off Delay set-up time before clock rises 5ns[10% and 90% points]). Max Units Conditions 8.0 MHz ns ns ns ns ns ns ns ns ns Per register ------- 62 10 15 200 70 70 25 25 0 ------- * tDLE is not required but is recommended to produce stable HV outputs and thus minimize power dissipation and current spikes (allows internal SR output to stabilize) Input and Output Equivalent Circuits VDD VDD VDD Data out Input GND GND Logic Inputs HVOUT GND Logic Data Output High Voltage Outputs Linear Dimensions, Inc. 445 East Ohio Street, Chicago IL 60611 USA tel 312.404.9283 fax 312.321.1830 www.lineardimensions.com