TI TLK6201EARGTT

TLK6201EA
www.ti.com
SLLS738 – AUGUST 2006
6.25-Gbps Cable and PC Board Equalizer
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Multirate Operation up to 6.25 Gbps
Compensates for up to 13-dB Loss on the
Receive Side and up to 12-dB Loss on the
Transmit Side at 3.125 GHz
Suitable to Receive and Transmit 6.25-Gbps
Data Over up to 60 Inches (1.5 Meters) of FR4
PC Boards
Suitable to Receive and Transmit 6.25-Gbps
Data Over up to 63 Feet (19.2 Meters) of
24-AWG Cable
Ultralow Power Consumption
Input Offset Cancellation
High Input Dynamic Range
Output Disable/Squelch Function
Loss of Signal Detection
Output Swing Select
Output De-Emphasis Select
Output Polarity Select
CML Data Outputs
Single 3.3-V Supply
Surface-Mount, Small-Footprint,
3-mm × 3-mm, 16-Pin QFN Package
DESCRIPTION
The TLK6201EA is a versatile, high-speed, limiting
equalizer for applications in digital high-speed links
with data rates up to 6.25 Gbps.
This device provides a high-frequency boost of 13
dB on the received data at 3.125 GHz, as well as
sufficient gain to ensure a fully differential output
swing for input signals as low as 100 mVp-p (at the
input of a lossy interconnect line).
Four de-emphasis levels can be selected on the
transmit side to provide up to 12 dB of additional
high-frequency loss compensation.
The high input-signal dynamic range ensures
low-jitter output signals even when overdriven with
input signal swings as high as 2000 mVp-p.
The TLK6201EA implements fixed loss-of-signal
detection, which can be used to implement a squelch
function by connecting the LOS output to the
adjacent DIS input.
The TLK6201EA is available in a small-footprint,
3-mm × 3-mm, 16-pin QFN package. It requires a
single 3.3-V supply.
This power-efficient equalizer is characterized for
operation from –40°C to 85°C.
APPLICATIONS
•
•
High-Speed Links in Communication and
Data Systems
Backplane, Daughtercard, and Cable
Interconnects for PCI Express, InfiniBand,
SAS, CEI, XAUI, Fibre Channel, and Ethernet
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
TLK6201EA
www.ti.com
SLLS738 – AUGUST 2006
BLOCK DIAGRAM
A simplified block diagram of the TLK6201EA is shown in Figure 1. This compact, low-power, 6.25-Gbps
equalizer consists of a high-speed data path with offset cancellation circuitry, a loss-of-signal detection block,
and a band-gap voltage reference and bias current generation block. The equalizer requires a single 3.3-V
±10% supply voltage. All circuit parts are described in detail as follows.
COC0
COC1
VCC
DE0
Offset
Cancellation
GND
DE1
POL
DIN+
+
+
+
+
DIN–
–
–
–
–
Gain Stage
Gain Stage
Gain Stage
Fixed Equalizer
Stage
DOUT+
Output
Buffer
Stage
DOUT–
DIS
SWG
Band-Gap Voltage
Reference and
Bias Current
Generation
Loss of
Signal Detection
LOS
B0052-04
Figure 1. Simplified Block Diagram of the TLK6201EA
HIGH-SPEED DATA PATH
The high-speed data signal with frequency-dependent loss is applied to the data path by means of the input
signal pins DIN+/DIN–. The data path consists of the fixed equalizer input stage, three gain stages which
provide the required gain to ensure a limited-output signal, and an output buffer stage. The equalized and
amplified data output signal is available at the output pins DOUT+/DOUT–, which provide 2 × 50-Ω
back-termination to VCC. The output stage also includes a data polarity-switching function, which is controlled
by the POL input, and a disable function, controlled by the signal applied to the DIS input pin.
The output swing can be increased 50% by applying a high-level signal to the SWG pin.
Up to 12 dB of output signal de-emphasis can be selected using the pins DE0 and DE1.
An offset cancellation compensates the inevitable internal offset voltages and thus ensures proper operation
even for very small input data signals.
The low-frequency cutoff is as low as 3.5 kHz with the built-in filter capacitor. For applications which require
even lower cutoff frequencies, an additional external filter capacitor can be connected to the COC0/COC1 pins.
LOSS-OF-SIGNAL DETECTION
The output signal of the second gain stage is monitored by the loss-of-signal detection circuitry. In this block, the
input signal is compared to a fixed threshold. If the low frequency components of the input signal fall below this
threshold, a loss of signal is indicated at the LOS pin.
A squelch function can be easily implemented by connecting the LOS output to the adjacent DIS input. This
measure avoids chattering of the output when no input signal is present.
BAND-GAP VOLTAGE AND BIAS GENERATION
The TLK6201EA equalizer is supplied by a single 3.3-V ±10% supply voltage connected to the VCC pins. This
voltage is referred to ground (GND).
2
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An on-chip band-gap voltage circuit generates a supply-voltage-independent reference from which all internally
required voltages and bias currents are derived.
DEVICE INFORMATION
The TLK6201EA is available in a small-footprint, 3-mm × 3-mm, 16-pin QFN package, with a lead pitch of
0.5 mm. The pinout is shown in Figure 2.
GND
1
DIN+
2
COC0
COC1
LOS
DIS
RGT PACKAGE
(TOP VIEW)
16
15
14
13
12
VCC
11
DOUT+
EP
GND
4
9
VCC
5
6
7
8
POL
DOUT–
DE0
10
DE1
3
SWG
DIN–
P0019-04
Figure 2. Pinout of TLK6201EA
TERMINAL FUNCTIONS
TERMINAL
TYPE
DESCRIPTION
16
Analog
Offset cancellation filter capacitor terminal 2. Connect an additional filter capacitor between
this pin and COC1 (pin 15). To disable the offset cancellation loop, connect COC1 and
COC0 (pins 15 and 16).
COC1
15
Analog
Offset cancellation filter capacitor terminal 1. Connect an additional filter capacitor between
this pin and COC0 (pin 16). To disable the offset cancellation loop, connect COC1 and
COC0 (pins 15 and 16).
DE0
7
CMOS in
Selects 4 dB of output signal de-emphasis when set to high level. Internally pulled up.
DE1
6
CMOS in
Selects 8 dB of output signal de-emphasis when set to high level. Internally pulled up.
DIN+
2
Analog in
Noninverted data input. On-chip load terminated to ground. Connect a 100-Ω differential
transmission line to terminals DIN+ and DIN–.
DIN–
3
Analog in
Inverted data input. On-chip load terminated to ground. Connect a 100-Ω differential
transmission line to terminals DIN+ and DIN–.
DIS
13
CMOS in
Disables CML output stage when set to high level. Internally pulled down.
DOUT+
11
CML out
Noninverted data output. On-chip 50-Ω back-terminated to VCC.
DOUT–
10
CML out
Inverted data output. On-chip 50-Ω back-terminated to VCC.
NAME
NO.
COC0
GND
1, 4, EP
Supply
LOS
14
CMOS out
Circuit ground. Exposed die pad (EP) must be grounded.
POL
8
CMOS in
Output data signal polarity select (internally pulled up): Setting to high level or leaving pin
open selects normal polarity. Low level selects inverted polarity.
SWG
5
CMOS in
Output swing control. The output swing is increased by 50% when set to high level.
Internally pulled down.
VCC
9, 12
Supply
High level indicates that the input signal amplitude is below the fixed threshold level.
3.3-V, ±10% supply voltage
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TLK6201EA
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SLLS738 – AUGUST 2006
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
(2)
VCC
Supply voltage
VDIN+, VDIN–
Voltage at DIN+, DIN– (2)
(2)
VALUE (1)
UNIT
–0.3 to 4
V
0.5 to 4
V
–0.3 to 4
V
±1
V
VDIS, VPOL, VDE1,
VDE0, VSWG,VCOC1,
VCOC0
Voltage at DIS, POL, DE1, DE0, SWG, COC1, COC0
VCOC,DIFF
Differential input voltage between COC1 and COC0
VDIN,DIFF
Differential input voltage between DIN+ and DIN–
±2.5
V
IDIN+, IDIN–, IDOUT+,
IDOUT–
Continuous current at inputs and outputs
±25
mA
ESD
ESD ratings at all pins, human body model (HBM)
TJ,max
Maximum junction temperature
Tstg
TA
(1)
(2)
3
kV
125
°C
Storage temperature range
–65 to 85
°C
Characterized free-air operating temperature range
–40 to 85
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage
TA
Free-air operating temperature
VIH
High-level input voltage, CMOS
VIL
Low-level input voltage, CMOS
MIN
NOM
MAX
3
3.3
3.6
V
85
°C
–40
2
UNIT
V
0.8
V
UNIT
DC ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
VCC
ICC
ROUT
4
TEST CONDITIONS
MIN
TYP
MAX
3
3.3
3.6
DIS = SWG = low (includes CML
output current)
45
54
DIS = low, SWG = high (includes
CML output current)
55
67
Output resistance, data
Single-ended to VCC
50
LOS high voltage
Isource = 1 mA
LOS low voltage
Isink = 1 mA
Supply voltage
Supply current
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V
mA
Ω
2.5
V
0.5
V
TLK6201EA
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SLLS738 – AUGUST 2006
AC ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
Typical operating condition is at VCC = 3.3 V and TA = 25°C.
PARAMETER
Low frequency –3-dB bandwidth
TYP
MAX
COC = open
TEST CONDITIONS
3.5
10
COC = 100 nF
0.8
Maximum data rate
MIN
6.25
UNIT
kHz
Gbps
10-12,
BER <
K28.5 pattern at 6.25
Gbps over a 36-inch, 7-mil-wide stripline
on standard FR4, including two
through-hole SMA connectors. Voltage
measured at the input of the
interconnect line.
VIN,MIN
Data input sensitivity (1)
VIN,MAX
Data input overload
Voltage at the input of an interconnect
line
High-frequency boost
f = 3.125 GHz (fixed input equalizer)
12
14
17
VOD
Differential data output voltage
swing
DIS = low, SWG = low
600
800
1000
DIS = low, SWG = high
900
1200
1500
VRIP
Differential output ripple
VCM,OUT
Data output, common-mode
voltage
DE
Output de-emphasis (see
Figure 3)
DIS = low, SWG = low, dc-coupled 50 Ω
to VCC, single-ended terminations
DIS = low, SWG = high, dc-coupled 50
Ω to VCC, single-ended terminations
Deterministic jitter
50
2000
DIS = high, 50% transitions of K28.5
pattern at 6.25 Gbps, no interconnect
line, VIN = 2000 mVp-p
mVP-P
mVP-P
0.25
VCC –
0.2
VCC – 0.15
VCC – 0.375
VCC –
0.3
VCC – 0.225
0
DE0 = high, DE1 = low
–4
DE0 = low, DE1 = high
–8
DE0 = high, DE1 = high
–12
dB
mVP-P
10 mVRMS
VCC – 0.25
DE0 = low, DE1 = low
K28.5 pattern at 6.25 Gbps, no
interconnect line, VIN = 400 mVp-p,
DE0 = low, DE1 = low, SWG = low
DJ
40
V
dB
8
K28.5 pattern at 6.25 Gbps over a
36-inch, 7-mil-wide stripline on standard
FR4 including two through-hole SMA
connectors, VIN = 400 mVp-p (voltage at
the input of the interconnect line),
DE0 = low, DE1 = low, SWG = low
12
1
psP-P
RJ
Random jitter
K28.5 pattern at 6.25 Gbps over a
36-inch, 7-mil-wide stripline on standard
FR4 including two through-hole SMA
connectors, VIN = 400 mVp-p (voltage at
the input of the interconnect line),
DE0 = low, DE1 = low, SWG = low
tr
Output rise time
20% to 80%, no interconnect line,
DE0 = low, DE1 = low
35
55
ps
tf
Output fall time
20% to 80%, no interconnect line,
DE0 = low, DE1 = low
35
55
ps
S11
Input return loss
10 Hz < f < 3.1 GHz
–15
dB
S22
Output return loss
10 Hz < f < 3.1 GHz
–12
dB
(1)
psRMS
The given differential input signal swing is valid for the low-frequency components of the input signal. The high-frequency components
may be attenuated by up to 13 dB at 3.125 GHz.
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TLK6201EA
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AC ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
Typical operating condition is at VCC = 3.3 V and TA = 25°C.
PARAMETER
VAS
VDAS
LOS assert threshold voltage
LOS de-assert threshold voltage
K28.5 pattern at 6.25 Gbps over a
36-inch, 7-mil-wide stripline on standard
FR4 including two through-hole SMA
connectors. Voltage measured at the
input of the interconnect line. (2)
LOS hysteresis
20 log(VDAS/VAS)
tAS/DAS
LOS assert/de-assert time
tDIS
Disable response time
Latency
(2)
TEST CONDITIONS
K28.5 pattern at 6.25 Gbps over a
36-inch, 7-mil-wide stripline on standard
FR4 including two through-hole SMA
connectors. Voltage measured at the
input of the interconnect line. (2)
MIN
TYP
40
75
130
(2)
2.5
UNIT
mVP-P
250
4.5
2
From DIN+/DIN– to DOUT+/DOUT–
MAX
mVP-P
dB
100
µs
20
ns
150
ps
This specification is for 0°C to 85°C. Depending on the interconnect line length and performance, the bit pattern, and the data rate, the
assert and de-assert threshold voltage levels vary. For more information, see the Typical Characteristics section.
A
VL, p–p
0
t
VH, p–p
t
é æ VL, p-p öù
÷ú
DE = 20 × êlogç
ç
V
êë è H, p-p ÷øúû
–A
T0157-01
Figure 3. Output Signal De-Emphasis
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APPLICATION INFORMATION
Figure 4 shows the TLK6201EA connected with an ac-coupled interface to the data signal source via a stripline
transmission line on FR4 material. The output load is ac-coupled as well.
The ac-coupling capacitors C1 through C4 in the input and output data signal lines are the only required external
components. In addition, if a very low cutoff frequency is required, as an option, an external filter capacitor COC
may be used.
LOS
DIS
Optional Connection
for Squelch Function
DIS
LOS
COC1
COC0
COC
Optional
GND
Input Transmission Line
C1
DIN+
DIN+
C2
DIN–
VCC
TLK6201EA
16-Pin QFN
DIN–
DOUT+
DOUT–
C4
DOUT+
DOUT–
POL
DE0
DE1
VCC
SWG
GND
VCC
C3
SWG
POL
DE1
DE0
S0072-04
Figure 4. Basic Application Circuit with AC-Coupled I/Os
0
Differential Stripline Attenuation − dB
−5
12-Inch Stripline
−10
−15
−20
−25
24-Inch Stripline
−30
−35
36-Inch Stripline
−40
−45
48−Inch Stripline
−50
−55
−60
0
1
2
3
4
5
6
f − Frequency − GHz
G001
Figure 5. Attenuation Characteristics of Stripline Interconnect Lines
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TLK6201EA
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TYPICAL CHARACTERISTICS
Typical operating condition is at VCC = 3.3 V, TA = 25°C, VIN = 400 mVp-p, DE0 = low, DE1 = low, SWG = low, and no
interconnect line at the output (unless otherwise noted).
DIFFERENTIAL EQUALIZER INPUT SIGNAL (TOP) AND OUTPUT SIGNAL (BOTTOM) AT
6.25 GBPS USING A K28.5 PATTERN
36-Inch y 7-Mil Stripline
Output Voltage
200 mV/Div
Output Voltage
200 mV/Div
Input Voltage
100 mV/Div
Input Voltage
100 mV/Div
36-Inch y 7-Mil Stripline
Time − 750 ps/Div
48-Inch y 10-Mil Stripline
48-Inch y 10-Mil Stripline
Output Voltage
200 mV/Div
Output Voltage
200 mV/Div
Input Voltage
100 mV/Div
Input Voltage
100 mV/Div
Time − 48 ps/Div
Time − 48 ps/Div
Time − 750 ps/Div
36-Inch y 7-Mil Stripline at the Input
24−Inch y 7-Mil Stripline at the Output
Output Volage
100 mV/Div
Output Voltage
100 mV/Div
Input Voltage
100 mV/Div
Input Voltage
100 mV/Div
36-Inch y 7-Mil Stripline at the Input
24-Inch y 7-Mil Stripline at the Output
DE0 = High, DE1 = High
Time − 48 ps/Div
DE0 = High, DE1 = High
Time − 750 ps/Div
G002
Figure 6. Equalizer Input and Output Signals With Different Interconnect Lines at 6.25 Gbps
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TYPICAL CHARACTERISTICS (continued)
Typical operating condition is at VCC = 3.3 V, TA = 25°C, VIN = 400 mVp-p, DE0 = low, DE1 = low, SWG = low, and no
interconnect line at the output (unless otherwise noted).
DIFFERENTIAL EQUALIZER INPUT SIGNAL (TOP) AND OUTPUT SIGNAL (BOTTOM) AT
4.25 GBPS USING A K28.5 PATTERN
36-Inch y 7-Mil Stripline
Output Voltage
200 mV/Div
Output Voltage
200 mV/Div
Input Voltage
100 mV/Div
Input Voltage
100 mV/Div
36-Inch y 7-Mil Stripline
Time − 70 ps/Div
Time − 1 ns/Div
48-Inch y 7-Mil Stripline
Output Voltage
200 mV/Div
Output Voltage
200 mV/Div
Input Voltage
100 mV/Div
Input Voltage
100 mV/Div
48-Inch y 7-Mil Stripline
Time − 70 ps/Div
Time − 1 ns/Div
G003
Figure 7. Equalizer Input and Output Signals With Different Interconnect Lines at 4.25 Gbps
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TYPICAL CHARACTERISTICS (continued)
Typical operating condition is at VCC = 3.3 V, TA = 25°C, VIN = 400 mVp-p, DE0 = low, DE1 = low, SWG = low, and no
interconnect line at the output (unless otherwise noted).
DIFFERENTIAL EQUALIZER INPUT SIGNAL (TOP) AND OUTPUT SIGNAL (BOTTOM) AT
2.125 GBPS USING A K28.5 PATTERN
36-Inch y 7-Mil Stripline
Output Voltage
200 mV/Div
Output Voltage
200 mV/Div
Input Voltage
100 mV/Div
Input Voltage
100 mV/Div
36-Inch y 7-Mil Stripline
Time − 2 ns/Div
48-Inch y 7-Mil Stripline
48-Inch y 7-Mil Stripline
Output Voltage
200 mV/Div
Output Voltage
200 mV/Div
Input Voltage
100 mV/Div
Input Voltage
100 mV/Div
Time − 150 ps/Div
Time − 150 ps/Div
Time − 2 ns/Div
Figure 8. Equalizer Input and Output Signals With Different Interconnect Lines at 2.125 Gbps
10
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TYPICAL CHARACTERISTICS (continued)
Typical operating condition is at VCC = 3.3 V, TA = 25°C, DE0 = low, DE1 = low, SWG = low, and no interconnect line at the
output (unless otherwise noted).
RANDOM JITTER
vs
INPUT VOLTAGE
DETERMINISTIC JITTER
vs
STRIPLINE LENGTH
80
2.5
6.25 Gbps
K28.5 Pattern
6.25 Gbps
K28.5 Pattern
70
60
Deterministic Jitter − psP−P
1.5
1.0
36-Inch Stripline
50
40
30
20
0.5
10
No line
0.0
0.0
0
0.5
1.0
1.5
2.0
VID − Differential Input Voltage − VP−P
0
5
10
15
20
25
30
35
40
45
50
Stripline Length − Inches
G005
G006
Figure 9.
Figure 10.
DETERMINISTIC JITTER
vs
INPUT VOLTAGE
18
16
Deterministic Jitter − psP−P
Random Jitter − psRMS
2.0
14
12
No Line
10
8
36-Inch Stripline
6
4
2
0
0.0
6.25 Gbps
K28.5 Pattern
0.5
1.0
1.5
VID − Differential Input Voltage − VP−P
2.0
G007
Figure 11.
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TYPICAL CHARACTERISTICS (continued)
Typical operating condition is at VCC = 3.3 V, TA = 25°C, DE0 = low, DE1 = low, SWG = low, and no interconnect line at the
output (unless otherwise noted).
DIFFERENTIAL OUTPUT RETURN LOSS
vs
FREQUENCY
0
0
−5
−5
Differential S22 − dB
Differential S11 − dB
DIFFERENTIAL INPUT RETURN LOSS
vs
FREQUENCY
−10
−15
−20
−25
−10
−15
−20
−25
−30
−30
0
2
4
6
8
10
12
0
2
4
f − Frequency − GHz
6
8
10
G008
G009
Figure 12.
Figure 13.
LOS ASSERT THRESHOLD VOLTAGE
vs
DATA RATE
LOS DE-ASSERT THRESHOLD VOLTAGE
vs
DATA RATE
180
K28.5 Pattern
90
K28.5 Pattern
LOS De-assert Threshold Voltage − mVP−P
LOS Assert Threshold Voltage − mVP−P
100
36-Inch
Stripline
80
48-Inch
Stripline
70
24-Inch Stripline
60
50
40
30
20
12-Inch
Stripline
10
1
2
3
160
36-Inch
Stripline
140
120
48-Inch
Stripline
100
80
60
40
20
24-Inch
Stripline
No Line
0
4
5
6
0
1.0
7
Data Rate − Gbps
1.5
12-Inch
Stripline
2.0
2.5
No Line
3.0
3.5
4.0
4.5
Data Rate − Gbps
G010
Figure 14.
12
12
f − Frequency − GHz
G011
Figure 15.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TLK6201EARGTR
ACTIVE
QFN
RGT
16
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TLK6201EARGTRG4
ACTIVE
QFN
RGT
16
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TLK6201EARGTT
ACTIVE
QFN
RGT
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TLK6201EARGTTG4
ACTIVE
QFN
RGT
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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