SN65LVCP40 www.ti.com SLLS623D – SEPTEMBER 2004 – REVISED FEBRUARY 2006 DC TO 4-GBPS DUAL 1:2 MULTIPLEXER/REPEATER/EQUALIZER • FEATURES • • • • • • • Receiver Equalization and Selectable Driver Preemphasis to Counteract High-Frequency Transmission Line Losses Integration of Two-Serial Port Selectable Loopback Typical Power Consumption 650 mW 30-ps Deterministic Jitter On-Chip 100-Ω Receiver and Driver Differential Termination Resistors Eliminate External Components and Reflection from Stubs 3.3-V Nominal Power Supply • 48-Terminal QFN (Quad Flatpack) 7 mm × 7 mm × 1 mm, 0.5-mm Terminal Pitch Temperature Range: -40°C to 85°C APPLICATIONS • • • • • Bidirectional Link Replicator Signal Conditioner XAUI 802.3ae Protocol Backplane Redundancy Host Adapter (Applications With Internal and External Connection to SERDES) Signaling Rates DC to 4 Gbps Including XAUI, GbE, FC, HDTV DESCRIPTION The SN65LVCP40 is a signal conditioner and data multiplexer optimized for backplanes. Input equalization and programmable output preemphasis support data rates up to 4 Gbps. Common applications are redundancy switching, signal buffering, or performance improvements on legacy backplane hardware. The SN65LVCP40 combines a pair of 1:2 buffers with a pair of 2:1 multiplexers (mux). Selectable switch-side loopback supports system testing. System interconnects and serial backplane applications of up to 4 Gbps are supported. Each of the two independent channels consists of a transmitter with a fan-out of two, and a receiver with a 2:1 input multiplexer. The drivers provide four selectable levels of preemphasis to compensate for transmission line losses. The receivers incorporates receive equalization and compensates for input transmission line loss. This minimizes deterministic jitter in the link. The equalization is optimized to compensate for a FR-4 backplane trace with 5-dB, high-frequency loss between 375 MHz and 1.875 GHz. This corresponds to a 24-inch long FR-4 trace with 6-mil trace width. This device operates from a single 3.3-V supply. The device has integrated 100-Ω line termination and provides self-biasing. The input tolerates most differential signaling levels such as LVDS, LVPECL or CML. The output impedance matches 100-Ω line impedance. The inputs and outputs may be ac coupled for best interconnectivity with other devices such as SERDES I/O or additional XAUI multiplexer buffer. With ac coupling, jitter is the lowest. FUNCTIONAL DIAGRAM Input Equalization Opens up Data Eye EQ Input Data After Long Backplane Trace Programmable Preemphasis out Output Data Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2006, Texas Instruments Incorporated SN65LVCP40 www.ti.com SLLS623D – SEPTEMBER 2004 – REVISED FEBRUARY 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) The SN65LVCP40 is packaged in a 7 mm × 7 mm × 1 mm QFN (quad flatpack no-lead) lead-free package, and is characterized for operation from -40°C to 85°C. AVAILABLE OPTIONS (1) TA DESCRIPTION -40°C to 85°C Serial multiplexer PACKAGED DEVICE (1) RGZ (48 pin) SN65LVCP40 The package is available taped and reeled. Add an R suffix to device types (e.g., SN65LVCP40RGZR). ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT VCC Supply voltage range (2) –0.5 V to 6 V Control inputs, all outputs Voltage range ESD TJ (1) (2) (3) (4) Receiver inputs Human Body Model (3) Charged-Device –0.5 V to (VCC + 0.5 V) –0.5 V to 4 V All pins Model (4) 4 kV All pins 500 V See Package Thermal Characteristics Table Maximum junction temperature Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. Tested in accordance with JEDEC Standard 22, Test Method A114-A. Tested in accordance with JEDEC Standard 22, Test Method C101. PACKAGE THERMAL CHARACTERISTICS PACKAGE THERMAL CHARACTERISTICS (1) NOM UNIT θJA (junction-to-ambient) 33 °C/W θJB (junction-to-board) 20 °C/W 23.6 °C/W 0.6 °C/W 19.4 °C/W 5.4 °C/W θJC (junction-to-case) PSI-jt (junction-to-top pseudo) 4-layer JEDEC Board (JESD51-7) using eight GND-vias Ø-0.2 on the center pad as shown in the section: Recommended pcb footprint with boundary and environment conditions of JEDEC Board (JESD51-2) PSI-jb (junction-to-board pseudo) θJP (junction-to-pad) (1) 2 See application note SPRA953 for a detailed explanation of thermal parameters (http://www-s.ti.com/sc/psheets/spra953/spra953.pdf). Submit Documentation Feedback SN65LVCP40 www.ti.com SLLS623D – SEPTEMBER 2004 – REVISED FEBRUARY 2006 RECOMMENDED OPERATING CONDITIONS dR Operating data rate VCC Supply voltage VCC(N) Supply voltage noise amplitude TJ Junction temperature TA Operating free-air temperature (1) MIN NOM MAX UNIT 4 Gbps 3.135 3.3 3.465 10 Hz to 2 GHz V 20 mV 125 °C -40 85 °C dR(in) ≤ 1.25 Gbps 100 1750 mVpp 1.25 Gbps < dR(in) ≤ 3.125 Gbps 100 1560 mVpp dR(in) > 3.125 Gbps 100 1000 mVpp Note: for best jitter performance ac coupling is recommended. 1.5 |V | ID 1.6 VCC 2 V DIFFERENTIAL INPUTS Receiver peak-to-peak differential input voltage (2) VID VICM Receiver common-mode input voltage CONTROL INPUTS VIH High-level input voltage 2 VCC + 0.3 V VIL Low-level input voltage –0.3 0.8 V 120 Ω DIFFERENTIAL OUTPUTS RL (1) (2) Differential load resistance 80 100 Maximum free-air temperature operation is allowed as long as the device maximum junction temperature is not exceeded. Differential input voltage VID is defined as | IN+ – IN– |. ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT DIFFERENTIAL INPUTS VIT+ Positive going differential input high threshold VIT– Negative going differential input low threshold A(EQ) Equalizer gain RT(D) Termination resistance, differential VBB Open-circuit Input voltage (input self-bias voltage) R(BBDC) Biasing network dc impedance R(BBAC) Biasing network ac impedance 50 –50 From 375 MHz to 1.875 GHz mV 5 80 AC-coupled inputs mV 100 dB 120 Ω 1.6 V 30 kΩ 375 MHz 42 1.875 GHz 8.4 RL = 100 Ω±1%, PRES_1 = PRES_0=0; PREL_1 = PREL_0=0; 4 Gbps alternating 1010-pattern; Figure 1 650 mVpp –650 mVpp Ω DIFFERENTIAL OUTPUTS VOH High-level output voltage VOL Low-level output voltage VODB(PP) Output differential voltage without preemphasis (2) VOCM Output common mode voltage ∆VOC(SS) Change in steady-state common-mode output voltage between logic states (1) (2) 1000 1300 1500 1.65 See Figure 6 1 mVpp V mV All typical values are at TA = 25°C and VCC = 3.3 V supply unless otherwise noted. They are for reference purposes and are not production tested. Differential output voltage V(ODB) is defined as | OUT+ – OUT– |. Submit Documentation Feedback 3 SN65LVCP40 www.ti.com SLLS623D – SEPTEMBER 2004 – REVISED FEBRUARY 2006 ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER Output preemphasis voltage ratio, V(PE) V ODB(PP) TEST CONDITIONS RL = 100 Ω ±1%; x = L or S; See Figure 1 VODPE(PP) MIN TYP (1) PREx_1:PREx_0 = 00 0 PREx_1:PREx_0 = 01 3 PREx_1:PREx_0 = 10 6 PREx_1:PREx_0 = 11 9 MAX UNIT dB t(PRE) Preemphasis duration measurement Output preemphasis is set to 9 dB during test PREx_x = 1; Measured with a 100-MHz clock signal; RL = 100 Ω, ±1%, See Figure 2 175 ps ro Output resistance Differential on-chip termination between OUT+ and OUT– 100 Ω CONTROL INPUTS IIH High-level Input current VIN = VCC IIL Low-level Input currentn VIN = GND R(PU) Pullup resistance 5 90 125 35 µA µA kΩ POWER CONSUMPTION PD ICC Device power dissipation All outputs terminated 100 Ω Device current consumption All outputs terminated 100 Ω 650 880 mW 254 mA TYP (1) MAX UNIT 3 6 ns 0.5 1 ns 0.5 1 ns PRBS 27-1 pattern at 4 Gbps SWITCHING CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MULTIPLEXER t(SM) Multiplexer switch time Multiplexer or loopback control to valid output DIFFERENTIAL OUTPUTS tPLH Low-to-high propagation delay tPHL High-to-low propagation delay tr Rise time tf Fall time tsk(p) Pulse skew, | tPHL– tPLH | (2) skew (3) tsk(o) Output tsk(pp) Part-to-part skew (4) RJ (1) (2) (3) (4) 4 Device random jitter, rms Propagation delay input to output See Figure 4 20% to 80% of VO(DB); Test Pattern: 100-MHz clock signal; See Figure 3 and Figure 7 All outputs terminated with 100 Ω See Figure 7for test circuit. BERT setting 10–15 Alternating 10-pattern. 80 ps 80 25 0.8 ps 20 ps 200 ps 500 ps 2 ps-rms All typical values are at 25°C and with 3.3 V supply unless otherwise noted. tsk(p) is the magnitude of the time difference between the tPLH and tPHL of any output of a single device. tsk(o) is the magnitude of the time difference between the tPLH and tPHL of any two outputs of a single device. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. Submit Documentation Feedback SN65LVCP40 www.ti.com SLLS623D – SEPTEMBER 2004 – REVISED FEBRUARY 2006 SWITCHING CHARACTERISTICS (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS 0 dB preemphasis Intrinsic deterministic device (PREx_x = 0); jitter (5) (6), peak-to-peak See Figure 7 for the test circuit. DJ (5) (6) (7) MIN PRBS 27-1 pattern TYP (1) 4 Gbps 30 1.25 Gbps Over 20-inch FR4 trace 0 dB preemphasis Absolute deterministic (PREx_x = 0); output jitter (7), peak-to-peak See Figure 7 for the test circuit. PRBS 27-1 pattern MAX UNIT ps 7 4 Gbps Over FR4 trace 2-inch to 20 inches long ps 20 Intrinsic deterministic device jitter is a measurement of the deterministic jitter contribution from the device. It is derived by the equation (DJ(OUT)– DJ(IN) ), where DJ(OUT) is the total peak-to-peak deterministic jitter measured at the output of the device in pspp. DJ(IN) is the peak-to-peak deterministic jitter of the pattern generator driving the device. The SN65LVCP40 built-in passive input equalizer compensates for ISI. For a 20-inch FR4 transmission line with 8-mil trace width, the LVCP40 typically reduces jitter by 60 ps from the device input to the device output. Absolute deterministic output jitter reflects the deterministic jitter measured at the SN65LVCP40 output. The value is a real measured value with a Bit error tester as described in Figure 7. The absolute DJ reflects the sum of all deterministic jitter components accumulated over the link: DJ(absolute) = DJ(Signal generator) + DJ(transmission line) + DJ(intrinsic(LVCP40)). PREL_1 1 VCC 2 SOB_0N 3 SOB_0P 4 GND LB0B LB0A SOA_0P SOA_0N VCC SIB_0P SIB_0N GND SIA_0P SIA_0N VCC MUX_S0 48 47 46 45 44 43 42 41 40 39 38 37 PIN ASSIGNMENTS PRES_0 35 VCC 34 LO_0N 33 LO_0P 5 32 GND LI_0P 6 31 LI_1N LI_0N 7 30 LI_1P VCC 8 29 VCC LO_1P 9 28 SOB_1P LO_1N 10 27 SOB_1N GND 11 26 REXT PREL_0 12 25 PRES_1 +− − + +− 36 +− +− − + + +− − +− + +− − +− 17 18 19 20 21 22 23 24 GND SIB_1N SIB_1P VCC SOA_1N SOA_1P LB1A LB1B 15 SIA_1N 16 14 VCC SIA_1P 13 MUX_S1 +− +− − + +− +− − + Submit Documentation Feedback 5 SN65LVCP40 www.ti.com SLLS623D – SEPTEMBER 2004 – REVISED FEBRUARY 2006 Table 1. Signal Descriptions SIGNAL PIN(S) TYPE SIGNAL TYPE DESCRIPTION LINE SIDE HIGH-SPEED I/O LI_0P LI_0N 6 7 I (w/ 50-Ω termination PECL/CML to VBB) compatible Differential input, port_0 line side LI_1P LI_1N 30 31 I (w/ 50-Ω termination PECL/CML to VBB) compatible Differential input, port_1 line side LO_0P LO_0N 33 34 O VML (1) Differential output, port_0 line side LO_1P LO_1N 9 10 O VML (1) Differential output, port_1 line side SWITCH SIDE HIGH-SPEED I/O SIA_0P SIA_0N 40 39 I (w/ 50-Ω termination CML/PECL to VBB) compatible Differential input, mux_0 switch_A_side SIB_0P SIB_0N 43 42 I (w/ 50-Ω termination CML/PECL to VBB) compatible Differential input, mux_0 switch_B_side SIA_1P SIA_1N 16 15 I (w/ 50-Ω termination CML/PECL to VBB) compatible Differential input, mux_1 switch_A_side SIB_1P SIB_1N 19 18 I (w/ 50-Ω termination CML/PECL to VBB) compatible Differential input, mux_1 switch_B_side SOA_0P SOA_0N 46 45 O VML (1) Differential output, mux_0 switch_A_side SOB_0P SOB_0N 4 3 O VML (1) Differential output, mux_0 switch_B_side SOA_1P SOA_1N 22 21 O VML (1) Differential output, mux_1 switch_A_side SOB_1P SOB_1N 28 27 O VML (1) Differential output, mux_1 switch_B_side CONTROL SIGNALS PREL_0 PREL_1 12 1 I (w/ 35-kΩ pullup) LVTTL Output preemphasis control, line side port_0 and port_1. Has internal pull-up. See Preemphasis Controls PREL_0, PREL_1, PRES_0 and PRES for function definition. PRES_0 PRES_1 36 25 I (w/ 35-kΩ pullup) LVTTL Output preemphasis control, switch side port_0 and port_1. See Preemphasis Controls PREL_0, PREL_1, PRES_0 and PRES for function definition. LB0A LB0B 47 48 I (w/ 35-kΩ pullup) LVTTL Loopback control for mux_0 switch side. See Loopback Controls LB0A, LB0B, LB1A and LB1B for function definition.n LB1A LB1B 23 24 I (w/ 35-kΩ pullup) LVTTL Loopback control for mux_1 switch side. See Loopback Controls LB0A, LB0B, LB1A and LB1B for function definition.n MUX_S0 MUX_S1 37 13 I (w/ 35-kΩ pullup) LVTTL Port A and B multiplex control of mux_0 and mux_1. See Multiplex Controls MUX_S0 and MUX_S1 for function definition. REXT 26 N/A No connect. This pin is unused and can be left open or tied to GND with any resistor. POWER SUPPLY VCC 2, 8, 14, 20, 29, 35, 38, 44 GND 5, 11, 17, PWR 32, 41 GND Center Pad (1) 6 PWR PWR Power supply 3.3 V ±5% Power supply return The ground center pad is the metal contact at the bottom of the 48-pin package. It must be connected to the GND plane. At least 4 vias are recommended to minimize inductance and provide a solid ground. See the package drawing for the via placement. VML stands for Voltage Mode logic; VML provides a differential output impedance of 100-Ω. VML offers the benefits of CML and consumes less power. Submit Documentation Feedback SN65LVCP40 www.ti.com SLLS623D – SEPTEMBER 2004 – REVISED FEBRUARY 2006 FUNCTIONAL BLOCK DIAGRAM VBB RT EQ LO_0P + +− − +− LO_0N SIA_0P RT SIA_0N RT EQ SIB_0P RT SIB_0N MUX_S0 VBB RT LI_0P RT +− + +− − SOA_0P +− + +− − SOB_0P SOA_0N EQ LI_0N SOB_0N LB0A LB0B PREL_0 Line Side Outputs Preemphasis Control PREL_1 VBB RT EQ RT SIA_1P SIA_1N LO_1P + +− − +− LO_1N RT EQ RT SIB_1P SIB_1N MUX_S1 VBB RT LI_1P RT +− + +− − SOA_1P +− + +− − SOB_1P SOA_1N EQ LI_1N SOB_1N LB1A LB1B PRES_0 Switch Side Outputs Preemphasis Control PRES_1 30 K 1.6 V VBB Note: VBB: Receiver input internal biasing voltage (allows ac coupling) EQ: Input Equalizer (compensates for frequency dependent transmission line loss of backplanes) RT: Internal 50−Ohm receiver termination (100−Ohm differential) Preemphasis: Output precompensation for transmission line losses Submit Documentation Feedback 7 SN65LVCP40 www.ti.com SLLS623D – SEPTEMBER 2004 – REVISED FEBRUARY 2006 FUNCTIONAL DEFINITIONS Table 2. Multiplex Controls MUX_S0 and MUX_S1 (1) MUX_Sn (1) MUX FUNCTION 0 MUX_n select input B 1 MUX_n select input A n = 0 or 1 Table 3. Loopback Controls LB0A, LB0B, LB1A and LB1B (1) LBnx (1) LOOPBACK FUNCTION 0 Enable loopback of SIx input to SOx output 1 Disable loopback of SIx input to SOx output n = 0 or 1, x = A or B Table 4. Multiplexer and Loopback Controls INPUTS / OUTPUTS SOA_0 SOB_0 SOA_1 SOB_1 LO_0 LO_1 SIA_0 LB0A = 0 x x x MUX_S0 = 1 x SIB_0 x LB0B = 0 x x MUX_S0 = 0 x SIA_1 x x LB1A = 0 x x MUX_S1 = 1 SIB_1 x x x LB1B =0 x MUX_S1 = 0 LI_0 LB0A = 1 LB0B = 1 x x x x LI_1 x x LB1A = 1 LB1B = 1 x x Table 5. Preemphasis Controls PREL_0, PREL_1, PRES_0, and PRES_1 PREx_1 (1) PREx_0 (1) OUTPUT PREEMPHASIS LEVEL IN dB DEEMPHASIZED PREEMPHASIZED TYPICAL FR4 TRACE LENGTH 0 0 0 dB 1200 1200 10 inches of FR4 trace 0 1 3 dB 850 1200 20 inches of FR4 trace 1 0 6 dB 600 1200 30 inches of FR4 trace 1 1 9 dB 425 1200 40 inches of FR4 trace (1) OUTPUT LEVEL IN mVpp x = L or S Preemphasis is the primary signal conditioning mechanism. See Figure 1 and Figure 2 for further definition. Equalization is secondary signal conditioning mechanism. The input stage provides 5-dB of fixed equalization gain from 375 MHz to 1.875 GHz (optimized for 3.75-Gbps 8B10B coded data). 8 Submit Documentation Feedback SN65LVCP40 www.ti.com SLLS623D – SEPTEMBER 2004 – REVISED FEBRUARY 2006 PARAMETER MEASUREMENT INFORMATION 1−bit 1 to N bit 3−dB Preemphasis VOCM VODB(PP) VODPE2(pp) 9−dB Preemphasis VODPE3(pp) 6−dB Preemphasis VODPE1(pp) 0−dB Preemphasis VOH VOL Figure 1. Preemphasis and Output Voltage Waveforms and Definitions 9−dB Preemphasis 1 to N bit VODPE3(pp) 1−bit VODB(PP) 80% 20% tPRE Figure 2. t(PRE) Preemphasis Duration Measurement Submit Documentation Feedback 9 SN65LVCP40 www.ti.com SLLS623D – SEPTEMBER 2004 – REVISED FEBRUARY 2006 PARAMETER MEASUREMENT INFORMATION (continued) 80% 80% VODB 20% 20% tr tf Figure 3. Driver Output Transition Time VID = 0 V IN t PHLD t PLHD VOD = 0 V OUT Figure 4. Propagation Delay Input to Output CIRCUIT DIAGRAMS VCC OUT+ 49.9 OUT− 49.9 VOCM IN+ RT(SE) = 50 1 pF Gain Stage + EQ VCC RBBDC RT(SE) = 50 Figure 6. Common-Mode Output Voltage Test Circuit IN− VBB ESD LineEndTermination Self−Biasing Network Figure 5. Equivalent Input Circuit Design 10 Submit Documentation Feedback SN65LVCP40 www.ti.com SLLS623D – SEPTEMBER 2004 – REVISED FEBRUARY 2006 JITTER TEST CIRCUIT Pattern Generator DC Block D+ Pre-amp Coax SMA 20−inch FR4 DC Block D− Coax 400 mVPP Differential SMA RX + EQ M U X <2” 50 Ω TL SMA <2” 50 Ω TL SMA DC Block Coax OUT 0 dB Coupled Transmission line DC Block Coax SN65LVCP40 Jitter Test Instrument Characterization Test Board NOTE: For the Jitter Test, the preemphasis level of the output is set to 0 dB (PREx_x=0) Figure 7. AC Test Circuit – Jitter and Output Rise Time Test Circuit The SN65LVCP40 input equalizer provides 5-dB frequency gain to compensate for frequency loss of a shorter backplane transmission line. For characterization purposes, a 24-inch FR-4 coupled transmission line is used in place of the backplane trace. The 24-inch trace provides roughly 5 dB of attenuation between 375 MHz and 1.875 GHz, representing closely the characteristics of a short backplane trace. The loss tangent of the FR4 in the test board is 0.018 with an effective ε(r) of 3.1. PREx_0 150 mV/ div 100 mV/ div Data Eye Input After 30-inch of FR4 PREx_1 TYPICAL DEVICE BEHAVIOR 0 0 1 1 0 1 0 1 0dB 3dB 6dB 9dB Data Eye Output After SN65LVCP40 80 ps/ div Figure 9. Preemphasis Signal Shape 40 ps/ div NOTE: 30 Inch Input Trace, dR = 4 Gbps; 27PRBS 1 Figure 8. Data Input and Output Pattern Submit Documentation Feedback 11 SN65LVCP40 www.ti.com SLLS623D – SEPTEMBER 2004 – REVISED FEBRUARY 2006 4-Gbps Signal Generator PRBS 27−1 LVCP40 Output with 9-dB Preemp 30−inch FR4 30-inch FR4 IN Output with 0-dB Preemp 30-inch FR4 Figure 10. Data Output Pattern 12 Submit Documentation Feedback SN65LVCP40 www.ti.com SLLS623D – SEPTEMBER 2004 – REVISED FEBRUARY 2006 TYPICAL CHARACTERISTICS DETERMINISTIC OUTPUT JITTER vs DATA RATE DETERMINISTIC OUTPUT JITTER vs DIFFERENTIAL INPUT AMPLITUDE 100 30 DJ @ T = 85°C 25 DJ @ T = 25°C 20 15 10 DJ @ T = 0°C 5 70 60 50 40 30 2 2.5 3 K 28.5 20 0 1.5 PRBS 27−1 3.5 4 50 40 Jitter @ 3.75 Gbps 30 20 Jitter @ 1.25 Gbps Jitter @ 3.125 Gbps 0 0 200 400 600 800 1000 1200 1400 16001800 0 VID − Differential Input Amplitude − mV DR − Data Rate − Gbps 200 400 600 800 1000 1200 1400 16001800 VID − Differential Input Swing − mV Figure 11. Figure 12. Figure 13. DETERMINISTIC OUTPUT JITTER vs INPUT TRACE LENGTH RANDOM OUTPUT JITTER vs DATA RATE RANDOM OUTPUT JITTER vs DIFFERENTIAL INPUT SWING RJ @ 2.5 Gbps 100 DJ @ 3.75Gpbs [ps] 200mV 80 DJ @ 3.125Gbps [ps] 200mV 60 40 20 DJ @ 3.125Gbps [ps] 600mV 0 10 20 30 40 50 60 Input Trace Length − inch 1.2 1 0.8 TA = 0°C − 1010 Pattern 0.6 TA = 85°C − 1010 Pattern TA = 25°C − 1010 Pattern 0.4 0.4 2.9 3.1 3.3 3.5 3.7 0 3.9 4 200 400 600 800 1000 1200 1400 1600 VID − Differential Input Swing − mV Figure 16. RANDOM OUTPUT JITTER vs INPUT TRACE LENGTH TOTAL OUTPUT JITTER vs POWER SUPPLY NOISE DJ/RJ OUTPUT JITTER vs COMMON-MODE INPUT VOLTAGE 1.0 0.8 0.6 RJ @ 3.75Gbps Vin=800mVpp; [ps−rms] RJ @ 3.75Gpbs Vin=200mVpp; [ps_rms] Figure 17. Jitter @ 800 mV Jitter @ 400 mV 40 30 Jitter @ 100 mV 20 Jitter Without VCC Noise 10 35 4 30 3.5 3 25 50 0 0.1 1 10 Noise Frequency - MHz Figure 18. Submit Documentation Feedback 100 2.5 20 15 DJ @ 3.75 Gbps 2 1.5 10 1.0 5 0 0.0 10 20 30 40 Input Trace Length − inch 40 DJ − Deterministic Output Jitter − ps Total Output Jitter - ps-pp 50 1.2 0 RJ @ 3.75 Gbps Figure 15. 1.4 0.2 RJ @ 3.125 Gbps 0.6 0 2.7 60 0.4 0.8 Figure 14. RJ @ 3.125Gbps Vin=200mVpp; [ps−rms] 1.6 1 DR − Data Rate − Gbps 2.0 1.8 1.2 0.2 0.2 0 2.5 70 RJ − Output Jitter − rms DJ @ 3.75Gpbs [ps] 600mV Random Output Jitter − ps-rms TA = 85°C − K28.7 Pattern 120 0 1.4 1.4 140 Deterministic Output Jitter − ps−pp Jitter @ 2.5 Gbps 60 10 CJTPAT 10 0 1 PRBS 27−1 + 100 CIDs 80 Random Output Jitter − ps-rms 35 70 90 Deterministic Output Jitter − ps 27 − 1 PRBS pattern, A 20 inch FR−4 Trace 8−mil Wide is Driving the LVCO40. The DJ is Measured on the Output of the LVCP40 Deterministic Output Jitter − ps Deterministic Output Jitter − ps 40 Random Output Jitter − ps−rms DETERMINISTIC OUTPUT JITTER vs DIFFERENTIAL INPUT AMPLITUDE RJ @ 3.75 Gbps 0.5 0 1000 1200 1400 1600 1800 2000 2200 2400 VICM − Common Mode Input Voltage − mV Figure 19. 13 SN65LVCP40 www.ti.com SLLS623D – SEPTEMBER 2004 – REVISED FEBRUARY 2006 TYPICAL CHARACTERISTICS (continued) TOTAL OUTPUT JITTER vs FREE-AIR TEMPERATURE SUPPLY CURRENT vs FREE-AIR TEMPERATURE 182 37 1.4 VDBO − Differential Output Swing − mV 38 181 TJ @ 200 mV Input Swing 0−dB Preemphasis Icc − Supply Current − mA TJ − Total Output Jitter − ps−pp DIFFERENTIAL OUTPUT SWING vs INPUT SIGNAL FREQUENCY 36 35 34 33 32 TJ @ 600 mV Input Swing 31 180 179 178 177 9−dB Preemphasis 176 175 174 30 0 10 20 30 40 50 60 70 173 80 85 20 40 60 80 TA − Free −Air Temperature − C Figure 20. 100 Figure 21. 0.8 VODB @ 25 dC 0.6 0.4 VODB @ 85 dC 0.2 0 −5 −10 −15 −20 −25 −30 −35 −40 −45 −50 10 100 1000 f − Frequency − MHz Figure 23. Submit Documentation Feedback 0 500 1 k 1.5 k 2 k 2.5 k 3 k 3.5 k 4 k Input Signal Frequency − MHz Figure 22. RECEIVER INPUT RETURN LOSS vs FREQUENCY Receiver Input Return Loss − dB VODB @ 0 dC 1 0 0 TA − Free −Air Temperature − C 14 1.2 10000 SN65LVCP40 www.ti.com SLLS623D – SEPTEMBER 2004 – REVISED FEBRUARY 2006 APPLICATION INFORMATION BANDWIDTH REQUIREMENTS Error free transmission of data over a transmission line has specific bandwidth demands. It is helpful to analyze the frequency spectrum of the transmit data first. For an 8B10B coded data stream at 3.75 Gbps of random data, the highest bit transition density occurs with a 1010 pattern (1.875 GHz). The least transition density in 8B10B allows for five consecutive ones or zeros. Hence, the lowest frequency of interest is 1.875 GHz/5 = 375 MHz. Real data signals consist of higher frequency components than sine waves due to the fast rise time. The faster the rise time, the more bandwidth becomes required. For 80-ps rise time, the highest important frequency component is at least 0.6/(π × 80 ps) = 2.4 GHz. Figure 24shows the Fourier transformation of the 375-MHz and 1.875-GHz trapezoidal signal. Signal Amplitude − dB 0 20 dB/dec 1875 MHz With 80 ps Rise Time −5 20 dB/dec 375 MHz With 80 ps Rise Time −10 40 dB/dec −15 80% 20% tr −20 −25 40 dB/dec tPeriod = 1/f 100 1000 f − Frequency − MHz 1/(pi x 100/60 tr) = 2.4 GHz 10000 Figure 24. Approximate Frequency Spectrum of the Transmit Output Signal With 80 ps Rise Time The spectrum analysis of the data signal suggests building a backplane with little frequency attenuation up to 2 GHz. Practically, this is achievable only with expensive, specialized PCB material. To support material like FR4, a compensation technique is necessary to compensate for backplane imperfections. EXPLANATION OF EQUALIZATION Backplane designs differ widely in size, layer stack-up, and connector placement. In addition, the performance is impacted by trace architecture (trace width, coupling method) and isolation from adjacent signals. Common to most commercial backplanes is the use of FR4 as board material and its related high-frequency signal attenuation. Within a backplane, the shortest to longest trace lengths differ substantially – often ranging from 8 inches up to 40 inches. Increased loss is associated with longer signal traces. In addition, the backplane connector often contributes a good amount of signal attenuation. As a result, the frequency signal attenuation for a 300-MHz signal might range from 1 dB to 4 dB while the corresponding attenuation for a 2-GHz signal might span 6 dB to 24 dB. This frequency dependent loss causes distortion jitter on the transmitted signal. Each 'LVCP40 receiver input incorporates an equalizer and compensates for such frequency loss. The SN65LVCP40 equalizer provides 5 dB of frequency gain between 375 MHz and 1.875 GHz, compensating roughly for 20 inches of FR4 material with 8-mil trace width. Distortion jitter improvement is substantial, often providing more than 30-ps jitter reduction. The 5-dB compensation is sufficient for most short backplane traces. For longer trace lengths, it is recommended to enable transmit preemphasis in addition. SETTING THE PREEMPHASIS LEVEL The receive equalization compensates for ISI. This reduces jitter and opens the data eye. In order to find the best preemphasis setting for each link, calibration of every link is recommended. Assuming each link consists of a transmitter (with adjustable pre-emphasis such as 'LVCP40) and the 'LVCP40 receiver, the following steps are necessary: 1. Set the transmitter and receiver to 0-dB preemphasis; record the data eye on the LVCP40 receiver output. 2. Increase the transmitter preemphasis until the data eye on the LVCP40 receiver output looks the cleanest. Submit Documentation Feedback 15 SN65LVCP40 www.ti.com SLLS623D – SEPTEMBER 2004 – REVISED FEBRUARY 2006 APPLICATION INFORMATION (continued) RECEIVER FAIL-SAFE RESPONSE If the input is removed from a powered receiver of the 'LVCP40, there are no internal fail-safe provisions to prevent noise from switching the output. Figure 25 shows one remedy using 1.6 kΩ resistors to pull up on one input to the SN65LVCP40 supply, and pull down the other input to its ground. Assuming the differential noise in the system is less than 25 mV, this maintains a valid output with no input. If the noise is greater than 25 mV, lower fail-safe resistance is required. VCC 1.6 kW 100 1.6 kW Figure 25. Fail-Safe Bias Resistors If the driver is another SN65LVCP40, attenuation from the driver to receiver must be less than 250 mV or 6 dB. This value comes from the minimum output of 500 mV into 100 Ω less the minimum recommended input voltage of 100 mV, 25 mV for noise, and 125 mV for the maximum fail-safe bias. The fail-safe bias also introduces additional eye-pattern jitter depending upon the input voltage transition time, but is designed to be less than 10% of the unit interval. The only other options are to have a hardware interlock that removed power to the receiver, or switched in a fail-safe bias, or rely on error detection to ignore random inputs. 16 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 8-Feb-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN65LVCP40RGZ ACTIVE QFN RGZ 48 52 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR SN65LVCP40RGZG4 ACTIVE QFN RGZ 48 52 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR SN65LVCP40RGZR ACTIVE QFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR SN65LVCP40RGZRG4 ACTIVE QFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR SN65LVCP40RGZT ACTIVE QFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR SN65LVCP40RGZTG4 ACTIVE QFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65LVCP40RGZR QFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 SN65LVCP40RGZT QFN RGZ 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LVCP40RGZR QFN RGZ 48 2500 333.2 345.9 28.6 SN65LVCP40RGZT QFN RGZ 48 250 333.2 345.9 28.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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