SN65HVD11-HT www.ti.com SLLS934D – NOVEMBER 2008 – REVISED DECEMBER 2010 3.3-V RS-485 TRANSCEIVER Check for Samples: SN65HVD11-HT FEATURES 1 • • • • • • • • APPLICATIONS • • • • • • • • • • • • • Controlled Baseline One Assembly/Test Site One Fabrication Site Available in Extreme (–55°C/210°C) Temperature Range (2) Extended Product Life Cycle Extended Product-Change Notification Product Traceability Texas Instruments' high temperature products utilize highly optimized silicon (die) solutions with design and process enhancements to maximize performance over extended temperatures. 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 • Operates With a 3.3-V Supply Bus-Pin ESD Protection Exceeds 16-kV Human-Body Model (HBM) 1/8 Unit-Load Option Available (up to 256 Nodes on Bus) Optional Driver Output Transition Times for Signaling Rates (1) of 1 Mbps, 10 Mbps, and 32 Mbps Based on ANSI TIA/EIA-485-A Bus-Pin Short Circuit Protection From –7 V to 12 V Open-Circuit, Idle-Bus, and Shorted-Bus Fail-Safe Receiver Glitch-Free Power-Up and Power-Down Protection for Hot-Plugging Applications SN75176 Footprint SUPPORTS EXTREME TEMPERATURE APPLICATIONS Down-Hole Drilling High Temperature Environments Digital Motor Controls Utility Meters Chassis-to-Chassis Interconnects Electronic Security Stations Industrial Process Control Building Automation Point-of-Sale (POS) Terminals and Networks • • • • DESCRIPTION/ORDERING INFORMATION The SN65HVD11 combines a 3-state differential line driver and differential input line receiver that operates with a single 3.3-V power supply. It is designed for balanced transmission lines and meets or exceeds ANSI TIA/EIA-485-A and ISO 8482:1993, with the exception that the thermal shutdown is removed. This differential bus transceiver is a monolithic integrated circuit designed for bidirectional data communication on multipoint bus-transmission lines. The driver and receiver have active-high and active-low enables, respectively, that can be externally connected together to function as direction control. The driver differential outputs and receiver differential inputs connect internally to form a differential input/ output (I/O) bus port that is designed to offer minimum loading to the bus when the driver is disabled or VCC = 0. D OR JD OR HKJ PACKAGE (TOP VIEW) R RE DE D (1) The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bits per second (bps). (2) 1 8 2 7 3 6 4 5 VCC B A GND Custom temperature ranges available 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2010, Texas Instruments Incorporated SN65HVD11-HT SLLS934D – NOVEMBER 2008 – REVISED DECEMBER 2010 www.ti.com BARE DIE INFORMATION DIE THICKNESS BACKSIDE FINISH BACKSIDE POTENTIAL BOND PAD METALLIZATION COMPOSITION 15 mils. Silicon with backgrind GND Cu-Ni-Pd Table 1. Bond Pad Coordinates in Microns - Rev A DESCRIPTION (1) PAD NUMBER a b c d R 1 69.30 372.15 185.30 489.15 ~RE 2 388.75 71.50 503.75 186.50 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 DNC (1) 2 3 722.40 55.40 839.40 172.40 DNC 4 891.40 55.40 1008.40 172.40 DE 5 1174.80 71.50 1289.80 186.50 DNC 6 1754.35 65.40 1869.35 180.40 DNC 7 1907.35 65.40 2022.35 180.40 D 8 2280.55 69.50 2395.55 184.50 DNC 9 2733.50 371.50 2848.50 486.50 GND 10 2691 1693.10 2808 1810.10 GND 11 2535 1693.10 2652 1810.10 DNC 12 2253.45 1685.65 2368.45 1800.65 A 13 1961.55 1693.10 2078.55 1810.10 B 14 799.55 1693.10 916.55 1810.10 DNC 15 498.35 1681.20 613.35 1796.20 VCC 16 244.80 1668.50 359.80 1783.50 VCC 17 91.80 1668.50 206.80 1783.50 DNC = Do Not Connect Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVD11-HT SN65HVD11-HT www.ti.com SLLS934D – NOVEMBER 2008 – REVISED DECEMBER 2010 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVD11-HT 3 SN65HVD11-HT SLLS934D – NOVEMBER 2008 – REVISED DECEMBER 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PACKAGE (2) SIGNALING RATE UNIT LOADS TA 10 Mbps 1/8 –55°C to 210°C SN65HVD11SJD 10 Mbps 1/8 –55°C to 210°C SN65HVD11SKGDA 10 Mbps 1/8 –55°C to 210°C SN65HVD11SHKJ SN65HVD11SHKJ 10 Mbps 1/8 –55°C to 175°C SN65HVD11HD HD11 (2) SN65HVD11SJD 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 (1) TOP-SIDE MARKING CDIP For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTIONAL BLOCK DIAGRAM 1 R 2 RE DE 3 6 4 A D 7 ABSOLUTE MAXIMUM RATINGS (1) B (2) over operating free-air temperature range (unless otherwise noted) VCC VALUE UNIT Supply voltage range –0.3 to 6 V Voltage range at A or B –9 to 14 V –0.5 to VCC + 0.5 V Input voltage range at D, DE, R, or RE IO Voltage input range, transient pulse, A and B, through 100 Ω (see Figure 12) –50 to 50 V Receiver output current range –11 to 11 mA Electrostatic discharge Human-Body Model (HBM) (3) Charged-Device Model (CDM) (4) A, B, and GND 16 All pins 4 All pins charge 1 Continuous total power dissipation (1) (2) (3) (4) 4 kV See Dissipation Ratings Table Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. Tested in accordance with JEDEC Standard 22, Test Method A114-A. Tested in accordance with JEDEC Standard 22, Test Method C101. Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVD11-HT SN65HVD11-HT www.ti.com SLLS934D – NOVEMBER 2008 – REVISED DECEMBER 2010 RECOMMENDED OPERATING CONDITIONS TA = –55°C to 125°C MIN NOM TA = 175°C MAX MIN 3 3.6 -7 (1) NOM TA = 210°C NOM MAX UNIT MAX MIN 3 3.6 3 3.6 V 12 -7 (1) 12 -7 (1) 12 V VCC Supply voltage VI or VIC Voltage at any bus terminal (separately or common mode) VIH High-level input voltage D, DE, RE 2 VCC 2 VCC 2 VCC V VIL Low-level input voltage D, DE, RE 0 0.8 0 0.8 0 0.8 V VID Differential input voltage Figure 8 -12 12 -12 12 -12 12 V Driver -60 -60 -60 Receiver -8 -8 -8 High-level output current IOL Low-level output current 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 IOH RL Differential load resistance CL Differential load capacitance TJ (2) Operating junction temperature Driver 60 60 60 Receiver 8 8 8 54 60 54 50 Signaling rate (1) (2) mA 60 54 50 10 129 60 Ω 50 pF 10 179 mA 10 214 Mbps °C The algebraic convention, in which the least-positive (most-negative) limit is designated as minimum, is used in this data sheet. See Thermal Characteristics table for information regarding this specification. Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVD11-HT 5 SN65HVD11-HT SLLS934D – NOVEMBER 2008 – REVISED DECEMBER 2010 www.ti.com DRIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER VIK Input clamp voltage |VOD| Differential output voltage TA = 175°C (1) TA = –55°C to 125°C TEST CONDITIONS MIN II = –18 mA TYP MAX –1.5 IO = 0 MIN TYP TA = 210°C (2) MAX –1.5 2 VCC MIN TYP MAX –1.5 2 VCC V 2 RL = 54 Ω, See Figure 2 1.0 1 1 Vtest = –7 V to 12 V, See Figure 3 1.0 1 1 UNIT VCC V Change in magnitude of differential output voltage Vtest = –7 V to 12 V, See Figure 2 and Figure 3 VOC(PP) Peak-to-peak common-mode output voltage See Figure 4 VOC(SS) Steady-state common-mode output voltage See Figure 4 1.4 2.5 1.4 2.5 1.4 2.5 V ΔVOC(SS) Change in steady-state common-mode output voltage See Figure 4 –0.06 0.06 –0.06 0.06 –0.06 0.06 V IOZ High-impedance output current See receiver input currents II Input current –100 0 –100 3 –100 3 0 100 0 100 0 100 IOS Short-circuit output current –7 V ≤ VO ≤ 12 V –250 250 –250 250 –250 250 C(OD) Differential output capacitance VOD = 0.4 sin (4E6pt) + 0.5 V, DE = 0 V 18 RE = VCC, D and DE = VCC, No load Receiver disabled and driver enabled 11 15.5 11.5 17.5 14 18 mA RE = VCC, D = VCC, DE = 0 V, No load Receiver disabled and driver disabled (standby) 2.5 20 20 150 175 450 mA RE = 0 V, D and DE = VCC, No load Receiver enabled and driver enabled 11 15.5 11 17.5 11 18 mA ICC (1) (2) 6 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Δ|VOD| -0.2 -0.25 0.25 400 D DE Supply current 0.2 -0.25 400 0.25 400 18 V mV 18 mA mA pF Minimum and maximum parameters are characterized for operation at TA = 175°C but may not be production tested at that temperature. Production test limits with statistical guardbands are used to ensure high temperature performance. Minimum and maximum parameters are characterized for operation at TA = 210°C but may not be production tested at that temperature. Production test limits with statistical guardbands are used to ensure high temperature performance. Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVD11-HT SN65HVD11-HT www.ti.com SLLS934D – NOVEMBER 2008 – REVISED DECEMBER 2010 DRIVER SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS TA = 175°C (1) TA = –55°C to 125°C TA = 210°C (2) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNIT tPLH Propagation delay time, low-to-high-level output 18 25 40 18 25 40 18 25 40 ns tPHL Propagation delay time, high-to-low-level output 18 25 40 18 25 40 18 25 40 ns tr Differential output signal rise time 10 21 30 10 22 30 10 22 30 ns tf Differential output signal fall time 10 21 30 10 22 30 10 22 30 ns tsk(p) Pulse skew (|tPHL – tPLH|) 2.5 2.5 2.5 ns tsk(pp) (3) Part-to-part skew (tPHL or tPLH) 11 11 11 ns tPZH Propagation delay time, high-impedance to high-level output 55 55 55 ns tPHZ Propagation delay time, high-level to high-impedance output 55 55 55 ns tPZL Propagation delay time, high-impedance to low-level output 55 55 55 ns tPLZ Propagation delay time, low-level to high-impedance output 75 75 75 ns tPZH Propagation delay time, standby to high-level output RL = 110 Ω, RE = 3 V, See Figure 6 6 6 6 ms tPZL Propagation delay time, standby to low-level output RL = 110 Ω, RE = 3 V, See Figure 7 6 6 6 ms (2) (3) 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 (1) RL = 54 Ω, CL = 50 pF, See Figure 5 RL = 110 Ω, RE = 0 V, See Figure 6 RL = 110 Ω, RE = 0 V, See Figure 7 Minimum and maximum parameters are characterized for operation at TA = 175°C but may not be production tested at that temperature. Production test limits with statistical guardbands are used to ensure high temperature performance. Minimum and maximum parameters are characterized for operation at TA = 210°C but may not be production tested at that temperature. Production test limits with statistical guardbands are used to ensure high temperature performance. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVD11-HT 7 SN65HVD11-HT SLLS934D – NOVEMBER 2008 – REVISED DECEMBER 2010 www.ti.com RECEIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TA = 175°C (1) TA = –55°C to 125°C TEST CONDITIONS MIN TYP MAX MIN TYP TA = 210°C (2) MAX MIN TYP MAX UNIT VIT+ Positive-going input threshold voltage IO = –8 mA VIT– Negative-going input threshold voltage IO = 8 mA Vhys Hysteresis voltage (VIT+ –VIT–) VIK Enable-input clamp voltage II = –18 mA –1.5 –1.5 –1.5 V VOH High-level output voltage VID = 200 mV, IOH = –8 mA, See Figure 8 2.4 2.4 2.4 V VOL Low-level output voltage VID = –200 mV, IOL = 8 mA, See Figure 8 IOZ Highimpedance state output current VO = 0 or VCC, RE = VCC –0.01 –0.2 –0.01 –0.2 –0.2 41 0.4 –1 VA or VB = 12 V VA or VB = 12 V, VCC = 0 V Other input at 0 V 1 41 0.4 –1 1 V V 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 35 –0.01 –1 mV 0.4 V 1 mA 0.075 0.11 0.1 0.15 0.1 0.15 0.085 0.13 0.12 0.16 0.12 0.16 II Bus input current IIH High-level input VIH = 2 V current, RE –30 0 –30 3 –30 3 mA IIL Low-level input current, RE VIL = 0.8 V –30 0 –30 0 –30 0 mA CID Differential input capacitance VID = 0.4 sin (4E6pt) + 0.5 V, DE at 0 V 15 RE = 0 V, D and DE = 0 V, No load Receiver enabled and driver disabled 5 8 7.5 8.5 7.5 10 mA RE = VCC, D = VCC, DE = 0 V, No load Receiver disabled and driver disabled (standby) 2.5 20 12.5 200 175 450 mA RE = 0 V, D and DE = VCC, No load Receiver enabled and driver enabled 11 15.5 11.5 17.5 14 18 mA VA or VB = –7 V VA or VB = –7 V, VCC = 0 V ICC (1) (2) 8 Supply current –0.1 –0.05 –0.3 –0.15 –0.3 –0.15 –0.1 –0.05 –0.3 –0.15 –0.3 –0.15 18 18 mA pF Minimum and maximum parameters are characterized for operation at TA = 175°C but may not be production tested at that temperature. Production test limits with statistical guardbands are used to ensure high temperature performance. Minimum and maximum parameters are characterized for operation at TA = 210°C but may not be production tested at that temperature. Production test limits with statistical guardbands are used to ensure high temperature performance. Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVD11-HT SN65HVD11-HT www.ti.com SLLS934D – NOVEMBER 2008 – REVISED DECEMBER 2010 RECEIVER SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER Propagation delay time, low-to-high-level output tPHL Propagation delay time, high-to-low-level output tsk(p) Pulse skew (|tPHL – tPLH|) tsk(pp) (3) Part-to-part skew tr Output signal rise time tf Output signal fall time tPZH (2) Output enable time to high level tPZL (2) Output enable time to low level tPHZ Output disable time from high level tPLZ Output disable time from low level tPZH (3) Propagation delay time, standby-to-high-level output tPZL (3) Propagation delay time, standby-to-low-level output (1) (2) (3) VID = –1.5 V to 1.5 V, CL = 15 pF, See Figure 9 CL = 15 pF, See Figure 9 TA = 175°C (1) TA = –55°C to 125°C TA = 210°C (2) UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX 30 55 70 30 55 70 30 55 70 ns 30 55 70 30 55 70 30 55 70 ns ns 4 4 4 15 15 15 ns 1 3 5 1 4 5 1 4 5 ns 1 3 5 1 4 5 1 4 5 ns 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 tPLH TEST CONDITIONS CL = 15 pF, DE = 3 V, See Figure 10 CL = 15 pF, DE = 0, See Figure 11 15 15 15 ns 15 15 15 ns 20 20 20 ns 15 15 15 ns 6 6 6 ms 6 6 6 ms Minimum and maximum parameters are characterized for operation at TA = 175°C but may not be production tested at that temperature. Production test limits with statistical guardbands are used to ensure high temperature performance. Minimum and maximum parameters are characterized for operation at TA = 210°C but may not be production tested at that temperature. Production test limits with statistical guardbands are used to ensure high temperature performance. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. THERMAL CHARACTERISTICS FOR JD PACKAGE over operating free-air temperature range unless otherwise noted PARAMETER qJA Junction-to-ambient thermal resistance (2) qJB Junction-to-board thermal resistance qJC Junction-to-case thermal resistance PD Device power dissipation (1) (2) (3) (1) TEST CONDITIONS MIN TYP MAX UNIT High-K board (3), No airflow JD pkg 64.9 No airflow JD pkg 83.4 High-K board without underfill JD pkg 27.9 °C/W JD pkg 6.49 °C/W HVD11 (10 Mbps) 165 mW RL= 60 Ω, CL = 50 pF, DE = VCC, RE = 0 V, Input to D a 50% duty cycle square wave at indicated signaling rate °C/W See Application Information section for an explanation of these parameters. The intent of qJA specification is solely for a thermal performance comparison of one package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a package in an application-specific environment. JED51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages THERMAL CHARACTERISTICS FOR HKJ PACKAGE over operating free-air temperature range (unless otherwise noted) PARAMETERS qJC MAX Junction-to-case thermal resistance (to bottom of case) 5.7 Junction-to-case thermal resistance (to top of case lid - as if formed dead bug) 13.7 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVD11-HT UNIT °C/W 9 SN65HVD11-HT SLLS934D – NOVEMBER 2008 – REVISED DECEMBER 2010 www.ti.com THERMAL CHARACTERISTICS FOR D PACKAGE over operating free-air temperature range (unless otherwise noted) PARAMETERS MAX UNIT 39.4 °C/W Junction-to-case thermal resistance (to bottom of case) qJC xxx 1000000 Estimated Life (Hours) 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 100000 Electromigration Fail Mode 10000 1000 110 Wirebond Fail Mode 120 130 140 150 160 170 180 190 200 210 Continuous TJ (°C) (1) See data sheet for absolute maximum and minimum recommended operating conditions. (2) Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect life). (3) The predicted operating lifetime vs. junction temperature is based on reliability modeling using electromigration as the dominant failure mechanism affecting device wearout for the specific device process and design characteristics. (4) Wirebond fail mode applicable for D package only. Figure 1. SN65HVD11SJD/SN65HVD11SKGDA/SN65HVD11SHKJ/SN65HVD11HD Operating Life Derating Chart 10 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVD11-HT SN65HVD11-HT www.ti.com SLLS934D – NOVEMBER 2008 – REVISED DECEMBER 2010 PARAMETER MEASUREMENT INFORMATION VCC DE II 375 Ω ±1% VCC IOA A DE VOD 0 or 3 V B 54 Ω ±1% 0 or 3 V D A VOD IOB 60 Ω ±1% + _ −7 V < V(test) < 12 V B VI VOB 375 Ω ±1% VOA 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Figure 2. Driver VOD Test Circuit and Voltage and Current Definitions VCC DE Input D Figure 3. Driver VOD With Common-Mode Loading Test Circuit 27 Ω ± 1% A A VA B VB VOC(PP) 27 Ω ± 1% B CL = 50 pF ±20% VOC ∆VOC(SS) VOC A. Input: PRR = 500 kHz, 50% Duty Cycle, t r <6ns, t f <6ns, Z O = 50 Ω B. CL Includes fixture and instrumentation capacitance Figure 4. Test Circuit and Definitions for Driver Common-Mode Output Voltage 3V VCC DE D Input Generator VI 50 Ω VOD tPLH CL Includes Fixture and Instrumentation Capacitance RL = 54 Ω ± 1% B 1.5 V VI CL = 50 pF ±20% A tPHL 90% VOD 1.5 V tr ≈2V 90% 0V 10% ≈ –2 V 0V 10% tf Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω Figure 5. Driver Switching Test Circuit and Voltage Waveforms A 3V D S1 VO VI 1.5 V 3V 1.5 V B DE Input Generator VI 50 Ω CL = 50 pF ±20% CL Includes Fixture and Instrumentation Capacitance RL = 110 Ω ± 1% 0.5 V 0V tPZH VOH VO 2.3 V tPHZ ≈0V Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω Figure 6. Driver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVD11-HT 11 SN65HVD11-HT SLLS934D – NOVEMBER 2008 – REVISED DECEMBER 2010 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) 3V RL = 110 Ω ± 1% A 3V VI 1.5 V VI S1 D 1.5 V VO DE Input Generator ≈3V 50 Ω 0V B tPZL tPLZ ≈3V CL = 50 pF ±20% 0.5 V CL Includes Fixture and Instrumentation Capacitance VO 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 2.3 V VOL Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω Figure 7. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms IA VA + VB 2 VID VB VIC A R VA IO B VO IB Figure 8. Receiver Voltage and Current Definitions A Input Generator R VI 50 Ω 1.5 V 0V B VO CL = 15 pF ±20% RE CL Includes Fixture and Instrumentation Capacitance Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω 3V 1.5 V VI 1.5 V 0V tPLH VO tPHL 90% 90% 1.5 V 10% tr VOH 1.5 V 10% V OL tf Figure 9. Receiver Switching Test Circuit and Voltage Waveforms 12 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVD11-HT SN65HVD11-HT www.ti.com SLLS934D – NOVEMBER 2008 – REVISED DECEMBER 2010 PARAMETER MEASUREMENT INFORMATION (continued) 3V 3V A DE 0 V or 3 V R D VO B RE Input Generator VI A 1 kΩ ± 1% S1 CL = 15 pF ±20% B CL Includes Fixture and Instrumentation Capacitance 50 Ω 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω 3V VI 1.5 V 1.5 V 0V tPZH(1) tPHZ VOH –0.5 V VOH D at 3 V S1 to B 1.5 V VO ≈0V tPZL(1) tPLZ ≈3V VO 1.5 V VOL +0.5 V D at 0 V S1 to A VOL Figure 10. Receiver Enable and Disable Time Test Circuit and Voltage Waveforms With Drivers Enabled Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVD11-HT 13 SN65HVD11-HT SLLS934D – NOVEMBER 2008 – REVISED DECEMBER 2010 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) 3V A 0 V or 1.5 V R B 1.5 V or 0 V RE Input Generator VI A 1 kΩ ± 1% VO S1 CL = 15 pF ±20% B CL Includes Fixture and Instrumentation Capacitance 50 Ω 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Generator: PRR = 100 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω 3V 1.5 V VI 0V tPZH(2) VOH A at 1.5 V B at 0 V S1 to B 1.5 V VO GND tPZL(2) 3V 1.5 V VO A at 0 V B at 1.5 V S1 to A VOL Figure 11. Receiver Enable Time From Standby (Driver Disabled) 0 V or 3 V RE A R Pulse Generator, 15 µs Duration, 1% Duty Cycle tr, tf ≤ 100 ns 100 Ω ± 1% B D + _ DE 3 V or 0 V NOTE: This test is conducted to test survivability only. Data stability at the R output is not specified. Figure 12. Test Circuit, Transient Over Voltage Test 14 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVD11-HT SN65HVD11-HT www.ti.com SLLS934D – NOVEMBER 2008 – REVISED DECEMBER 2010 PARAMETER MEASUREMENT INFORMATION (continued) FUNCTION TABLES Table 2. DRIVER (1) OUTPUTS INPUT D ENABLE DE A B H H H L H L H L Z Z Open H H L 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 L X (1) H = high level L = low level Z = high impedance X = irrelevant ? = indeterminate Table 3. RECEIVER (1) DIFFERENTIAL INPUTS VID = VA - VB ENABLE RE OUTPUT R VID ≤ −0.2 V L L −0.2 V < VID < −0.01 V L ? −0.01 V ≤ VID L H (1) X H Z Open circuit L H Short circuit L H H = high level L = low level Z = high impedance X = irrelevant ? = indeterminate Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVD11-HT 15 SN65HVD11-HT SLLS934D – NOVEMBER 2008 – REVISED DECEMBER 2010 www.ti.com EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS D and RE Inputs DE Input VCC VCC 100 kΩ 1 kΩ 1 kΩ Input Input 100 kΩ 9V 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 9V A Input B Input VCC 16 V VCC 16 V R3 R1 R1 R3 Input Input 16 V R2 16 V A and B Outputs R2 R Output VCC VCC 16 V 5Ω Output Output 9V 16 V R1/R2 = 36 kΩ R3 = 180 kΩ 16 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVD11-HT SN65HVD11-HT www.ti.com SLLS934D – NOVEMBER 2008 – REVISED DECEMBER 2010 TYPICAL CHARACTERISTICS RMS SUPPLY CURRENT vs SIGNALING RATE BUS INPUT CURRENT vs BUS INPUT VOLTAGE 70 90 RL = 54 Ω CL = 50 pF 80 VCC = 3.6 V 70 I I − Bus Input Current − µ A I CC − RMS Supply Current − mA TA = 25°C RE at VCC DE at VCC 60 VCC = 3 V 40 60 50 VCC = 0 V 40 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 50 TA = 25°C DE at 0 V VCC = 3.3 V 30 20 10 0 VCC = 3.3 V −10 −20 −30 −40 −50 30 0 5 7.5 Signaling Rate − Mbps −60 −7−6 −5 −4 −3 −2 −1 0 1 2 3 4 5 6 7 8 9 10 11 12 VI − Bus Input Voltage − V 10 Figure 13. Figure 14. HIGH-LEVEL OUTPUT CURRENT vs DRIVER HIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT CURRENT vs DRIVER LOW-LEVEL OUTPUT VOLTAGE 200 TA = 25°C DE at VCC D at VCC VCC = 3.3 V 100 50 0 −50 −100 −150 180 I OL − Low-Level Output Current − mA IOH − High-Level Output Current − mA 150 2.5 160 140 TA = 25°C DE at VCC D at 0 V VCC = 3.3 V 120 100 80 60 40 20 0 −200 −4 −2 0 2 4 VOH − Driver High-Level Output Voltage − V 6 −20 −4 −2 0 2 4 6 VOL − Driver Low-Level Output Voltage − V Figure 15. 8 Figure 16. Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVD11-HT 17 SN65HVD11-HT SLLS934D – NOVEMBER 2008 – REVISED DECEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) DRIVER DIFFERENTIAL OUTPUT vs FREE-AIR TEMPERATURE DRIVER OUTPUT CURRENT vs SUPPLY VOLTAGE 2.5 VTest = 12 V 2.2 2.1 2.0 1.9 1.8 1.7 1.6 1.5 -100 TA = 25°C DE at VCC D at VCC RL = 54 Ω −35 I O − Driver Output Current − mA 2.3 VCC = 3.3 V −30 −25 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 VOD – Driver Differential Output – V 2.4 −40 −20 −15 −10 −5 0 -50 0 50 100 150 200 0 250 0.50 1 1.50 2 2.50 3 3.50 VCC − Supply Voltage − V TA – Free-Air Temperature – °C Figure 17. Figure 18. ENABLE TIME vs COMMON-MODE VOLTAGE (SEE Figure 20) 600 Enable Time − ns 500 400 300 200 100 0 -7 -2 3 8 13 V(TEST) − Common-Mode Voltage − V Figure 19. 18 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVD11-HT SN65HVD11-HT www.ti.com SLLS934D – NOVEMBER 2008 – REVISED DECEMBER 2010 TYPICAL CHARACTERISTICS (continued) 375 W ± 1% Y D 0 or 3 V -7 V < V(TEST) < 12 V VOD 60 W ± 1% Z DE 375 W ± 1% V 50 W 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Input Generator 50% tpZH(diff) VOD (high) 1.5 V 0V tpZL(diff) -1.5 V VOD (low) Figure 20. Driver Enable Time From DE to VOD The time tpZL(x) is the measure from DE to VOD(x). VOD is valid when it is greater than 1.5 V. Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVD11-HT 19 SN65HVD11-HT SLLS934D – NOVEMBER 2008 – REVISED DECEMBER 2010 www.ti.com APPLICATION INFORMATION 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 256 Devices on Bus Figure 21. Typical Application Circuit 20 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVD11-HT SN65HVD11-HT www.ti.com SLLS934D – NOVEMBER 2008 – REVISED DECEMBER 2010 THERMAL CHARACTERISTICS OF IC PACKAGES qJA (Junction-to-Ambient Thermal Resistance) is defined as the difference in junction temperature to ambient temperature divided by the operating power. qJA is not a constant and is a strong function of: • the PCB design (50% variation) • altitude (20% variation) • device power (5% variation) 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 qJA can be used to compare the thermal performance of packages if the specific test conditions are defined and used. Standardized testing includes specification of PCB construction, test chamber volume, sensor locations, and the thermal characteristics of holding fixtures. qJA is often misused when it is used to calculate junction temperatures for other installations. TI uses two test PCBs as defined by JEDEC specifications. The low-k board gives average in-use condition thermal performance, and it consists of a single copper trace layer 25 mm long and 2-oz thick. The high-k board gives best case in-use condition, and it consists of two 1-oz buried power planes with a single copper trace layer 25 mm long and 2-oz thick. A 4% to 50% difference in qJA can be measured between these two test cards. qJC (Junction-to-Case Thermal Resistance) is defined as difference in junction temperature to case divided by the operating power. It is measured by putting the mounted package up against a copper block cold plate to force heat to flow from die, through the mold compound into the copper block. qJC is a useful thermal characteristic when a heatsink is applied to package. It is not a useful characteristic to predict junction temperature because it provides pessimistic numbers if the case temperature is measured in a nonstandard system and junction temperatures are backed out. It can be used with qJB in 1-dimensional thermal simulation of a package system. qJB (Junction-to-Board Thermal Resistance) is defined as the difference in the junction temperature and the PCB temperature at the center of the package (closest to the die) when the PCB is clamped in a cold-plate structure. qJB is only defined for the high-k test card. qJB provides an overall thermal resistance between the die and the PCB. It includes a bit of the PCB thermal resistance (especially for BGA’s with thermal balls) and can be used for simple 1-dimensional network analysis of package system, see Figure 22. Figure 22. Thermal Resistance Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVD11-HT 21 PACKAGE OPTION ADDENDUM www.ti.com 30-Apr-2012 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 PACKAGING INFORMATION Orderable Device SN65HVD11HD (1) Status (1) Package Type Package Drawing ACTIVE SOIC (2) Pins Package Qty D 8 75 Green (RoHS & no Sb/Br) Eco Plan Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) CU NIPDAU Level-1-260C-UNLIM SN65HVD11SHKJ ACTIVE CFP HKJ 8 1 TBD Call TI N / A for Pkg Type SN65HVD11SHKQ PREVIEW CFP HKQ 8 25 TBD Call TI Call TI SN65HVD11SJD ACTIVE CDIP SB JDJ 8 1 TBD SN65HVD11SKGDA ACTIVE XCEPT KGD 0 130 TBD POST-PLATE N / A for Pkg Type Call TI N / A for Pkg Type The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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