tm TE CH T14M1024A SRAM 128K X 8 HIGH SPEED CMOS STATIC RAM FEATURES GENERAL DESCRIPTION The T14M1024A is a one-megabit density, fast static random access memory organized as 131,072 • Fast Address Access Times : 10/12/15ns • Single 5V +10% power supply words by 8 bits. It is designed for use in high performance memory applications such as main • Low Power Consumption : 110/105/100mA • TTL I/O compatible memory storage and high speed communication buffers. Fabricated using high performance CMOS technology, access times down to 10ns are achieved. Memory expansion by banking is easily accomplished using the chip enable pins CE1 and CE2. This device is packaged in a standard 32-pin 300 mil SOJ and 32-pin TSOP-I. • 2.0V data retention mode • Automatic power-down when deselected • Available packages : 32-pin 300 mil SOJ & 32-pin TSOP-I • Industry Standard Pin Assignment BLOCK DIAGRAM PIN CONFIGURATION NC 1 32 Vcc A10 2 31 A11 A9 3 30 CE2 A8 4 29 WE A7 5 28 A12 A6 6 27 A13 A5 7 26 A14 A4 8 25 A15 SOJ A3 9 24 OE A2 10 23 A16 A1 11 22 CE1 A0 12 21 I/O7 I/O0 13 20 I/O6 I/O1 14 19 I/O5 I/O2 15 18 I/O4 Vss 16 17 I/O3 Vcc Vss A0 .. . . A16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 TSOP-I CORE ARRAY CE1 CE2 DATA I/O WE OE I/O0 . . . I/O7 PIN DESCRIPTION SYMBOL A0 - A16 I/O0 - I/O7 CE1,CE2 WE A15 A14 A13 A12 WE CE2 A11 VCC NC A10 A9 A8 A7 A6 A5 A4 DECODER 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A16 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 A1 A2 A3 TM Technology Inc. reserves the right to change products or specifications without notice. OE Vcc Vss DESCRIPTION Address Inputs Data Inputs/Outputs Chip Select Inputs Write Enable Output Enable Power Supply Ground PART NUMBER EXAMPLES PACKAGE SPEED T14M1024A-10J SOJ 300mil 10ns T14M1024A-10P TSOP-I 8x13.4mm 10ns T14M1024A-10H TSOP-I 8x20mm 10ns P. 1 Publication Date: SEP. 2002 Revision:E tm TE CH T14M1024A DC CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS PARAMETER Power Supply Voltage Input Voltage Output Voltage Operating Temperatrue Storage Temperature Power Dissipation Short Circuit Output Current SYM Vcc VIN VOUT TOPR TSTG PD IOUT RATING -0.5 to 7.0 -0.5 to Vcc+0.5 -0.5 to Vcc+0.5 0 to +70 -55 to +150 1.0 50 UNIT V V V °C °C W mA TRUTH TABLE CE1 H CE2 X OE X WE X MODE Not Selected I/O0- I/O7 High-Z X L X X Not Selected High-Z I SB, I SB1 I SB, I SB1 Vcc L L L H H H H L X H H L Output Disable Read Write High-Z Data Out Data In Icc Icc Icc OPERATING CHARACTERISTICS (Vcc = 5V ± 10%, Ta = 0 to 70°C) PARAMETER Power Supply Voltage Input Low Voltage Input High Voltage Input Leakage Current SYM. Vcc VIL VIH ILI Output Leakage Current ILO Output Low Voltage Output High Voltage Operating Power Supply Current MIN. 4.5 -0.5 2.2 - MAX. 5.5 0.8 Vcc+0.5 5 UNIT V V V uA - 5 uA 2.4 - 0.4 110 V V mA CE2 = VIH ;f=max 12ns IO = 0mA 15ns CE1 = VIH , CE2 = VIL, IO = 0mA - 105 100 25 mA mA mA Vcc = max; CE1 ≥ Vcc-0.2V or CE2 ≤ Vss+0.2V; f=0mhz; IO = 0mA - 5 mA VIN =Vss to Vcc VIN=Vss to Vcc , CE1 = VIH or CE2 VOL VOH = VIL or OE = VIH or WE = VIL I OL = 4.0 mA I OH =-2.0 mA Icc CE1 = VIL Supply Current Standby Power TEST CONDITIONS I SB I SB1 10ns Note: Typical characteristics are at Vcc = 5V, Ta = 25°C TM Technology Inc. reserves the right to change products or specifications without notice. P. 2 Publication Date: SEP. 2002 Revision:E tm TE CH T14M1024A RECOMMENDED OPERATING CONDITIONS PARAMETER Supply Voltage Input Voltage, low Input Voltage, high Ambient Temperature SYM Vcc MIN Typ-10% -0.3 2.2 0 VIL VIH TA TYP 5 - MAX Typ+10% 0.8 Vcc+0.3 70 UNIT V V V °C MAX. 6 8 UNIT pF pF CAPACITANCE PARAMETER Input Capacitance Input/ Output Capacitance SYMBOL CONDITION VIN = 0V VOUT = 0V C IN C I/O Note: These parameters are sampled but not 100% tested. AC TEST CONDITIONS PARAMETER CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load 0V to 3V 3.0 ns 1.5V C L =30pF, I OH / I OL = -2mA/4mA AC TEST LOADS AND WAVEFORM 5V R1 480 ohm RL=50 ohm Vt=1.5V OUTPUT Zo=50 ohm OUTPUT 30pF 5pF Including Jig and Scope R2 255 ohm (For TCLZ, TOLZ, TCHZ, TOHZ, TWHZ, TOW ) TM Technology Inc. reserves the right to change products or specifications without notice. P. 3 Publication Date: SEP. 2002 Revision:E tm TE CH T14M1024A AC CHARACTERISTICS ( Vcc =5V ± 10%, Vss = 0V, Ta = 0 to 70°C) (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable to Output Valid Chip Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z Output Hold from Address Change SYM. tRC tAA tACS tAOE tCLZ* tOLZ* tCHZ* tOHZ* tOH T14M1024A-10 T14M1024A-12 T14M1024A-15 UNIT MIN. MAX. MIN. MAX. MIN. MAX. 10 12 15 ns - 10 - 12 - 15 ns - 10 - 12 - 15 ns - 6 - 7 - 7 ns 3 - 3 - 3 - ns 0 - 0 - 0 - ns - 5 - 6 - 7 ns - 5 - 6 - 7 ns 3 - 3 - 3 - ns * These parameters are sampled but not 100% tested. (2)WRITE CYCLE PARAMETER Write Cycle Time Chip Enable to End of Write Address Valid to End of Write Address Setup Time Write Pulse Width Write Recovery Time Data Valid to End of Write Data Hold from End of Write Write to Output in High Z Output Disable to Output in High Z Output Active from End of Write SYM. tWC tCW tAW tAS tWP tWR tDW tDH tWHZ* tOHZ* tOW T14M1024A-10 T14M1024A-12 T14M1024A-15 UNIT MIN. MAX. MIN. MAX. MIN. MAX. 10 12 15 ns 8 - 10 - 11 - ns 8 - 10 - 11 - ns 0 - 0 - 0 - ns 8 - 10 - 11 - ns 0 - 0 - 0 - ns 6 - 8 - 8 - ns 0 - 0 - 0 - ns - 5 - 6 - 6 ns - 5 - 6 - 7 ns 0 - 0 - 0 - ns * These parameters are sampled but not 100% tested. TM Technology Inc. reserves the right to change products or specifications without notice. P. 4 Publication Date: SEP. 2002 Revision:E tm TE CH T14M1024A TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) tR C A d d re s s tA A tO H tO H D O U T READ CYCLE 2 (Chip Enable Controlled) tRC Address tA A OE tOH t AOE tOLZ C E t ACS tOHZ tCLZ tCHZ DOUT DON' T CARE UNDEFINED TM Technology Inc. reserves the right to change products or specifications without notice. P. 5 Publication Date: SEP. 2002 Revision:E tm TE CH WRITE CYCLE 1 T14M1024A ( OE CLOCK) tW C Ad d r es s t WR OE tC W CE t AW tW P WE t t AS OHZ (1,4) DOUT tD W tD H DIN WRITE CYCLE 2 ( OE = V IL Fixed) t WC Ad d r es s t t CW WR CE t t AW WP WE t t AS t W HZ t OH OW (1,4) (2) ( 3) DOUT t DW t DH DIN DON'T CARE UNDEFINED TM Technology Inc. reserves the right to change products or specifications without notice. P. 6 Publication Date: SEP. 2002 Revision:E tm TE CH T14M1024A Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. The data output from D OUT are the same as the data written to D IN during the write cycle. 3. D OUT provides the read data for the next address. 4. Transition is measured ± 500 mV from steady state with C L = 5pF. guaranteed but not 100% tested. This parameter is 5. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. TM Technology Inc. reserves the right to change products or specifications without notice. P. 7 Publication Date: SEP. 2002 Revision:E tm TE CH T14M1024A PACKAGE DIMENSIONS 32-LEAD SOJ SRAM (300 mil) SYMBOL A A1 A2 B B1 C D E E1 e L y DIMENSIONS IN INCHES 0.140(MAX) 0.026(MIN) 0.100±0.005 0.018(TYP) 0.028(TYP) 0.008(TYP) 0.823±0.005 0.335±0.010 0.300±0.005 0.050(TYP) 0.086±0.010 0.003(MAX) TM Technology Inc. reserves the right to change products or specifications without notice. DIMENSIONS IN MM 3.556(MAX) 0.660(MIN) 2.540±0.127 0.457(TYP) 0.711(TYP) 0.203(TYP) 20.904±0.127 8.509±0.254 7.620±0.127 1.270(TYP) 2.184±0.254 0.076(MAX) P. 8 Publication Date: SEP. 2002 Revision:E tm TE CH T14M1024A PACKAGE DIMENSIONS 32-LEAD TSOP-I (8x20mm) HD C 1 32 b E e 16 17 A2 "A " A1 Seating plane A D Seating plane L D etail"A " SYMBOL A A1 A2 b C HD D E e L L1 θ DIMENSIONS IN INCHES MIN 0.002 0.035 0.007 0.004 0.020 0° NOM 0.040 0.008 0.006 0.787 TYP 0.724 TYP 0.315 TYP 0.020 TYP 0.024 0.032 TYP 3° DIMENSIONS IN MM MAX 0.047 0.006 0.041 0.011 0.008 MIN 0.05 0.90 0.17 0.10 0.028 0.50 5° 0° TM Technology Inc. reserves the right to change products or specifications without notice. P. 9 L1 NOM 1.00 0.20 0.15 20.00 TYP 18.40 TYP 8.00 TYP 0.50 TYP 0.60 0.813 TYP 3° MAX 1.20 0.15 1.05 0.27 0.21 0.70 5° Publication Date: SEP. 2002 Revision:E y tm TE CH T14M1024A PACKAGE DIMENSIONS 32-LEAD TSOP-I (8x13.4mm) HD C 1 32 b E e 16 17 A2 "A " A A1 S e a t in g p la n e y D S e a t in g p la n e L D e t a il " A " SYMBOL A A1 A2 b C HD D E e L L1 θ DIMENSIONS IN INCHES MIN 0.002 0.035 0.007 0.004 0.020 0° NOM 0.040 0.008 0.006 0.528 TYP 0.465 TYP 0.315 TYP 0.020 TYP 0.024 0.032TYP 3° L1 DIMENSIONS IN MM MAX 0.047 0.006 0.041 0.011 0.008 MIN 0.05 0.90 0.17 0.10 0.028 0.50 5° 0° TM Technology Inc. reserves the right to change products or specifications without notice. P. 10 NOM 1.00 0.20 0.15 13.40 TYP 11.80 TYP 8.00 TYP 0.50 TYP 0.60 0.813 TYP 3° MAX 1.20 0.15 1.05 0.27 0.21 0.7 5° Publication Date: SEP. 2002 Revision:E