tm TE CH T15N1M16A SRAM 64K X 16 LOW POWER CMOS STATIC RAM FEATURES GENERAL DESCRIPTION The T15N1M16A is a low power CMOS Static • Fast access time : 55/70/100 ns RAM organized as 65,536 words by 16 bits. That • Single +2.4 to 3.6V Power Supply operates on a wide voltage range from +2.4 to 3.6V • Low power supply current : power supply, Fabricated using high performance - Operating :30mA(max) CMOS technology, Inputs and three-state outputs - Standby : 10uA are TTL compatible and allow for direct interfacing • TTL compatible , Tri-state output with common system bus structures. Data retention • Common I/O capability is guaranteed at a power supply voltage as low as • Automatic power-down when deselected 1.5V. • Full static operation, no clock or refresh required • Available packages type : - 44-PIN SOJ (400 mil) BLOCK DIAGRAM - 44-PIN TSOP-II (400 mil) - 48-PIN CSP • Operating temperature : - 0 ~ +70 °C -40 ~ +85 °C PART NUMBER EXAMPLES PART NO. T15N1M16A-70J T15N1M16A-70S T15N1M16A-70C T15N1M16A-70JI T15N1M16A-70SI T15N1M16A-70CI PACKAGE CODE J=SOJ S=TSOP-II C= CSP J=SOJ S=TSOP-II C= CSP Vcc Vss A0 . . CORE ARRAY DECODER Operating Temperature 0 ~ +70 °C -40 ~ +85 °C TM Technology Inc. reserves the right to change products or specifications without notice. A15 CE WE OE LB UB P. 1 CONTROL CIRCUIT DATA I/O I/O1 .. . I/O16 Publication Date: JUL . 2002 Revision: A tm TE CH T15N1M16A PIN CONFIGURATIONS A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 48-Ball CSP 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 SOJ & TSOP-II A5 A6 A7 OE UB LB I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 NC TOP VIEW (Ball Down) 1 2 3 4 5 6 A LB OE A0 A1 A2 NC B I/O 9 UB A3 A4 CE I/O 1 C I/O 1 0 I/O 1 1 A5 A6 I/O 2 I/O 3 D VSS I/O 1 2 NC A7 I/O 4 VCC E VCC I/O 1 3 NC NC I/O 5 VSS F I/O 1 5 I/O 1 4 A 14 A 15 I/O 6 I/O 7 G I/O 1 6 NC A 12 A 13 WE I/O 8 H NC A8 A9 A 10 A 11 NC PIN DESCRIPTIONS SYMBOL DESCRIPTIONS A0 ~ A15 Address inputs SYMBOL DESCRIPTIONS Lower byte (I/O 1~8) LB I/O1~I/O16 Data inputs/outputs UB Upper byte (I/O 9~16) CE Chip enable VCC Power supply WE Write enable input VSS Ground OE Output enable input NC No connection TM Technology Inc. reserves the right to change products or specifications without notice. P. 2 Publication Date: JUL . 2002 Revision: A tm TE CH T15N1M16A ABSOLUTE MAXIMUM RATINGS* PARAMETER Voltage on Any Pin Relative to VSS Power Dissipation Storage Temperature Temperature Under Bias SYM VR PD TSTG IBIAS MIN. -0.5 -55 0 / -40 MAX. +4.6 V 0.7 +150 +70 / +85 UNIT V W °C °C *Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and function operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. TRUTH TABLE I/O 1~8 I/O 9~16 MODE LB OE WE UB CE H X* X* X* X* High-Z High-Z Deselected X* X* X* H H High-Z High-Z Deselected L H H L X* High-Z High-Z Output Disabled L H H X* L High-Z High-Z Output Disabled L L H L H Data Out High-Z Lower Byte Read L L H H L High-Z Data Out Upper Byte Read L L H L L Data Out Data Out Word Read L X* L L H Data In High-Z Lower Byte Write L X* L H L High-Z Data In Upper Byte Write L X* L L L Data In Data In Word Write *Note: X = Don’t Care (Must be low or high state), L = Low, H = High Power Standby Standby Active Active Active Active Active Active Active Active RECOMMENDED OPERATING CONDITIONS (Ta = 0°C to +70°C / -40 °C ~ +85 °C *) PARAMETER Supply Voltage Input Voltage * VIL SYM Vcc VSS VIH VIL MIN 2.4 0.0 2.0 -0.5* TYP 0.0 - MAX 3.6 0.0 Vcc+0.3 0.4 UNIT V V V V min = -1.0V for pulse width less than tRC/2 TM Technology Inc. reserves the right to change products or specifications without notice. P. 3 Publication Date: JUL . 2002 Revision: A tm TE CH T15N1M16A OPERATING CHARACTERISTICS (Vcc = +2.4 to 3.6V , VSS = 0V, Ta = 0°C to +70°C / -40°C to +85 °C) PARAMETER SYM. TEST CONDITIONS Input Leakage Current ILI Vcc = Max, VIN = VSS to Vcc -55 -70 -100 UNIT Min Max Min Max Min Min -1 1 -1 1 -1 1 uA -1 1 -1 1 -1 1 uA - 30 - 25 - 20 mA - 0.3 - 0.3 - 0.3 mA - 10 - 10 - 10 uA - 0.4 - 0.4 - 0.4 V 2.2 - 2.2 - V CE = VIH Output Leakage Current ILO or OE = VIH or WE = VIL VIO = VSS to Vcc Operating Power Supply Current ICC Cycle time=min, 100% duty CE = VIH or Standby Power Supply Current I SB (TTL Level) I SB1 (CMOS Level) Output Low Voltage Output High Voltage LB = UB = VIH other input= VIL or VIH Standby Power Supply Current CE = VIL, VIN = VIH or VIL, IOUT=0mA VOL VOH CE ≥ Vcc-0.2V or LB = UB ≥ Vcc-0.2V, VIN ≤ 0.2V or VIN ≥ Vcc-0.2V I OL = 2.1mA I OH = -1 mA 2.2 TM Technology Inc. reserves the right to change products or specifications without notice. - P. 4 Publication Date: JUL . 2002 Revision: A tm TE CH T15N1M16A CAPACITANCE (f = 1 MHz, Ta = 25°C,) PARAMETER Input Capacitance Input/ Output Capacitance SYMBOL CONDITION VIN = 0V VIN = VOUT = 0V C IN C I/O MAX. 8 10 UNIT pF pF Note: This parameter is guaranteed by device characterization and is not production tested. AC TEST CONDITIONS PARAMETER CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load 0.4V to 2.0V 5.0 ns 1.4V C L =30pF+1TTL Load AC TEST LOADS AND WAVEFORM TTL DQ C L* RL CL 50 ohm 30 pF Z 0 = 50 ohm Vt =1.4V Fig.B Output Load Equivalent Fig.A * Including Scope and Jig Capacitance TM Technology Inc. reserves the right to change products or specifications without notice. P. 5 Publication Date: JUL . 2002 Revision: A tm TE CH T15N1M16A AC CHARACTERISTICS( Vcc =+2.4 to 3.6V , Vss = 0V, Ta = 0 to +70°C / -40 to +85 °C) (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Output Hold from Address Change Chip Enable to Output in Low-Z Chip Disable to Output in High-Z Output Enable to Output in Low-Z Output Disable to Output in High-Z LB , UB Access Time LB , UB Enable to Output in Low-Z LB , UB Disable to Output in High-Z -55 SYM. -70 -100 UNIT Min Max Min Max Min Max 55 10 10 5 10 - 55 55 25 20 20 55 20 70 10 10 5 10 - 70 70 35 25 25 70 25 100 10 10 5 10 100 100 50 25 25 100 tRC tAA tACE tOE tOH tLZ tHZ tOLZ tOHZ tBA tBLZ tBHZ 25 ns ns ns ns ns ns ns ns ns ns ns ns (2)WRITE CYCLE PARAMETER Write Cycle Time Chip Enable to Write End Address Valid to Write End Address Setup Time Write Pulse Width Write Recovery Time Data Valid to Write End Data Hold Time Write Enable to Output in High-Z Output Active from Write End LB , UB Setup to Write End -55 SYM. tWC tCW tAW tAS tWP tWR tDW tDH tWHZ tOW tBW -70 -100 UNIT Min Max Min Max Min Max 55 45 45 0 40 0 25 0 0 5 45 20 - 70 60 60 0 50 0 30 0 0 5 60 20 - 100 80 80 0 70 0 40 0 0 5 80 30 - TM Technology Inc. reserves the right to change products or specifications without notice. P. 6 ns ns ns ns ns ns ns ns ns ns Publication Date: JUL . 2002 Revision: A tm TE CH T15N1M16A TIMING WAVEFORMS READ CYCLE 1 (Address Controlled, CE = OE = VIL , WE = VIH , LB or/and UB = VIL ) tRC Address t AA t OH DOUT Previous Data Valid Data Valid READ CYCLE 2 ( WE = VIH ) tRC Ad d re s s tA A t OH t ACE CE tHZ t BA UB / LB t BHZ tOE OE tLZ D OUT tBLZ tOLZ t OHZ High-Z DON'T CARE UNDEFINED (Chip Enable Controlled) Notes (READ CYCLE) : 1. WE are high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition referenced to VOH or VOL levels. 4. At any given temperature and voltage condition. tHZ (max.) is less than tLZ (min.) both for a given device and from device to device interconnection. 5. Transition is measured ±200mV from steady state voltage with load. This parameter is sampled and not 100% tested. 6. Device is continuously selected with CE =VIL . TM Technology Inc. reserves the right to change products or specifications without notice. P. 7 Publication Date: JUL . 2002 Revision: A tm TE CH WRITE CYCLE 1 T15N1M16A ( WE Controlled) tWC Ad d r es s tAW tWR tCW CE tBW UB / LB tA S tWP WE tWHZ tOW DOUT High-Z tDW DIN WRITE CYCLE 2 tDH High -Z ( CE Controlled) tWC Ad d res s tAW tWR tCW CE tAS tBW UB / LB tWP WE DOUT Hig h -Z tDW DIN Hig h -Z tDH Hig h -Z DO N' T CARE UNDE FINE D TM Technology Inc. reserves the right to change products or specifications without notice. P. 8 Publication Date: JUL. 2002 Revision: A tm TE CH WRITE CYCLE 3 T15N1M16A ( UB , LB Controlled) tWC Add res s tAW tWR tCW UB / LB t AS tBW CE tWP WE DOUT Hig h -Z tDW DIN Hig h -Z tDH Hig h -Z DO N' T CARE UNDE FINE D NOTES ( WRITE CYCLE ) : 1. A write occurs during the overlap of a low CE , a low WE . A write begins at the lateat transition among CE goes low, WE going low. A write end at the earliest transition among CE going high, WE going high. tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the later of CE going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. TM Technology Inc. reserves the right to change products or specifications without notice. P. 9 Publication Date: JUL. 2002 Revision: A tm TE CH T15N1M16A DATA RETENTION CHARACTERISTICS PARAMETER VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time SYM. VDR ICCDR tCDR TEST CONDITION CE ≥ VCC -0.2V VIN ≥ Vcc -0.2V or VIN ≤ 0.2V Vcc=3.0V tR MIN. 1.5 0 MAX. 10 - UNIT V uA ns tRC - ns DATA RETENTION WAVEFORM (Ta = 0°C to +70° / -40°C to +85 °C) TM Technology Inc. reserves the right to change products or specifications without notice. P. 10 Publication Date: JUL. 2002 Revision: A tm TE CH T15N1M16A PACKAGE DIMENSIONS 44-LEAD SOJ (400 mil) A1 44 23 E1 1 E 22 C D A2 e Seating Plane B SYMBOL DIMENSIONS IN INCHES A y DIMENSIONS IN MM A Min. 0.128 Typ. 0.138 Max. 0.148 Min. 3.25 Typ. 3.51 Max. 3.76 A1 0.082 - - 2.08 - - A2 0.110 (ref) 2.79 (ref) B 0.015 0.018 0.020 0.38 0.46 0.51 C 0.007 0.008 0.013 0.18 0.20 0.33 D 1.120 1.125 1.130 28.45 28.58 28.70 E 0.395 0.400 0.405 10.03 10.16 10.29 e 0.050 1.27 E1 0.435 0.440 0.445 11.05 11.18 11.30 y - - 0.004 - - 0.102 TM Technology Inc. reserves the right to change products or specifications without notice. P. 11 Publication Date: JUL. 2002 Revision: A tm TE CH T15N1M16A PACKAGE DIMENSIONS 44-LEAD TSOP-II D 44 23 E2 E E1 L1 22 INDEX MARK Mirror finish c e b1 b A £c A3 A2 SEATING PLANE c1 Symbol A A1 A2 A3 b b1 c c1 D e E E1 E2 L L1 θ Dimension in mm Min Nom Max 1.20 0.05 0.1 0.95 1.00 1.05 0.25 0.35(typ) 0.10 0. 15 0.25 0.805 0.10 18.31 18.41 18.51 0.80(typ) 11.56 11.76 11.96 10.03 10.16 10.29 10.76 0.4 0.5 0.6 0.8(typ) 0 8 A1 L Dimension in inch Min Nom Max 0.047 0.002 0.004 0.037 0.039 0.041 0.010 0.014(typ) 0.004 0.006 0.010 0.032 0.004 0.721 0.725 0.729 0.031(typ) 0.455 0.463 0.471 0.394 0.400 0.405 0.458 0.016 0.020 0.024 0.032(typ) 0 8 TM Technology Inc. reserves the right to change products or specifications without notice. P. 12 Publication Date: JUL. 2002 Revision: A tm TE CH T15N1M16A PACKAGE DIMENSIONS 48-pin CSP (8 row x 6 column) 48 BALL FINE PITCH BGA (0.75mm ball pitch) Units : millimeters B ottom V ie w To p V ie w A 1 IN DE X MA RK B 0 .5 0 B1 0.50 # A1 C C1 C1/2 B /2 A Y E2 D E Symbol A B B1 C C1 D E E1 E2 Y min 5.95 7.95 0.25 0.20 - typ 0.75 6.00 3.75 8.00 5.25 0.30 1.10 0.95 0.25 - max 6.05 8.05 0.35 1.20 0.30 0.08 0.3 0 E1 Notes : 1. Bump counts : 48 (8 row x 6column) 2. Bump pitch : (x,y)=(0.75 x 0.75) typ. 3. All tolerance are ±0.050 unless otherwise specified. 4. ‘Y’ is coplanarity : 0.08(max) 5. Units : mm TM Technology Inc. reserves the right to change products or specifications without notice. P. 13 Publication Date: JUL. 2002 Revision: A