tm TE CH T15V2M16B 128K X 16 LOW POWER CMOS STATIC RAM SRAM FEATURES • Access time : 45/55/70/100 ns • Low-power consumption - Active: 5mA (ICC1) - Stand-by: (CMOS input/output) Max.. 15 uA for 55/70/100ns Max.. 40 uA for 45ns • Equal access and cycle time GENERAL DESCRIPTION The T15V2M16B is a very Low Power CMOS Static RAM organized as 131,072 words by 16 bits . This device is fabricated by high performance CMOS technology. It can be operated under wide power supply voltage range from +2.7V to +3.6V. • Single +2.7V to 3.6V Power Supply The T15V2M16B inputs and three-state • TTL compatible , Tri-state output outputs are TTL compatible and allow for direct • Common I/O capability interfacing with common system bus structures. • Automatic power-down when deselected Data retention is guaranteed at a power supply • Available in 44-PIN TSOP-II and 48-pin CSP voltage as low as 2V. packages • Operating temperature : - -10 ~ +70 °C - -40 ~ +85 °C BLOCK DIAGRAM PART NUMBER EXAMPLES PART NUMBER PACKAGE Temperature T15V2M16B-55S TSOP-II -10 ~ +70 °C T15V2M16B-70C CSP -10 ~ +70 °C T15V2M16B-55SI TSOP-II -40 ~ +85 °C T15V2M16B-70CI CSP -40 ~ +85 °C Vcc Vss A0 . . . CORE ARRAY DECODER A16 CE WE OE LB UB TM Technology Inc. reserves the right to change products or specifications without notice. P. 1 CONTROL CIRCUIT DATA I/O I/O1 . . . I/O16 Publication Date: NOV. 2002 Revision:A tm TE CH T15V2M16B PIN CONFIGURATIONS A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 TSOP-II 1 2 3 4 5 6 A LB OE A0 A1 A2 NC B I/O9 UB A3 A4 CE I/O1 C I/O10 I/O11 A5 A6 I/O2 I/O3 D VSS I/O12 NC A7 I/O4 VCC E VCC I/O13 NC A16 I/O5 VSS F I/O15 I/O14 A14 A15 I/O6 I/O7 G I/O16 NC A12 A13 WE I/O8 H NC A8 A9 A10 A11 NC 48-Ball CSP A5 A6 A7 OE UB LB I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 NC TOP VIEW (Ball Down) PIN DESCRIPTIONS SYMBOL DESCRIPTIONS A0 ~ A16 Address inputs SYMBOL DESCRIPTIONS Lower byte (I/O 1~8) LB I/O1~I/O16 Data inputs/outputs UB Upper byte (I/O 9~16) CE Chip enable VCC Power supply WE Write enable input VSS Ground OE Output enable input NC No connection TM Technology Inc. reserves the right to change products or specifications without notice. P. 2 Publication Date: NOV. 2002 Revision:A tm TE CH T15V2M16B ABSOLUTE MAXIMUM RATINGS* PARAMETER Voltage on Any Pin Relative to VSS Power Dissipation Storage Temperature Temperature Under Bias SYM VR PD TSTG IBIAS MIN. -0.2 -55 -10 / -40 MAX. +4.6 V 1.0 +150 +70 / +85 UNIT V W °C °C *Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and function operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. TRUTH TABLE I/O 1~8 I/O 9~16 MODE LB OE WE UB CE H X* X* X* X* High-Z High-Z Deselected X* X* X* H H High-Z High-Z Deselected L H H L X* High-Z High-Z Output Disabled L H H X* L High-Z High-Z Output Disabled L L H L H Data Out High-Z Lower Byte Read L L H H L High-Z Data Out Upper Byte Read L L H L L Data Out Data Out Word Read L X* L L H Data In High-Z Lower Byte Write L X* L H L High-Z Data In Upper Byte Write L X* L L L Data In Data In Word Write *Note: X = Don’t Care (Must be low or high state), L = Low, H = High TM Technology Inc. reserves the right to change products or specifications without notice. P. 3 Power Standby Standby Active Active Active Active Active Active Active Active Publication Date: NOV. 2002 Revision:A tm TE CH T15V2M16B RECOMMENDED OPERATING CONDITIONS - (Ta = -10 ~ +70 °C / -40°C ~ 85°C) PARAMETER Supply Voltage SYM Vcc VSS VIH VIL Input Voltage MIN 2.7 0.0 0.7Vcc -0.2 TYP 3.0 0.0 - MAX 3.6 0.0 Vcc+0.3 0.6 UNIT V V V V OPERATING CHARACTERISTICS - (Vcc = 2.7 to 3.6V, VSS = 0V, Ta = -10 ~ +70 °C / -40°C ~ 85°C) PARAMETER SYM. -45 TEST CONDITIONS -55 -70 -100 UNIT Min Max Min Max Min Max Min Max Input Leakage Current Output Leakage Current Operating Power Supply Current Average Operating Current Standby Power Supply Current (TTL Level) Standby Power Supply Current (CMOS Level) Output Low Voltage Output High Voltage Vcc = Max, ILI VIN = VSS to Vcc CE = VIH or OE = VIH ILO or WE = VIL VIO = VSS to Vcc CE = VIL, WE =VIH, OE = VIH , ICC VIN = VIH or VIL, IOUT=0mA Cycle time=1us, 100% duty, IIO=0mA, ICC1 CE ≤ 0.2V, VIN ≥ VCC-0.2V or VIN ≤ 0.2V Cycle time=min, 100% duty, IIO=0mA, ICC2 CE = VIL, VIN = VIH or VIL CE = VIH or I SB LB = UB = VIH other input= VIL or VIH CE ≥ Vcc-0.2V or LB = UB ≥Vcc-0.2V, I SB1 VIN ≤ 0.2V or VIN ≥ Vcc-0.2V VOL I OL = 2.1mA VOH I OH = -1.0 mA TM Technology Inc. reserves the right to change products or specifications without notice. - 1 - 1 - 1 - 1 uA - 1 - 1 - 1 - 1 uA - 3 - 3 - 3 - 3 mA - 5 - 5 - 5 - 5 mA - 45 - 40 - 35 - 25 mA - 0.3 - 0.3 - 0.3 - 0.3 mA - 40 - 15 - 15 - 15 uA 2.2 0.4 - - 0.4 2.2 - V V P. 4 - 0.4 2.2 - - 0.4 2.2 - Publication Date: NOV. 2002 Revision:A tm TE CH T15V2M16B CAPACITANCE (f = 1 MHz, Ta = 25°C,) PARAMETER Input Capacitance Input/ Output Capacitance SYMBOL C IN C I/O CONDITION VIN = 0V VIN = VOUT = 0V MAX. 8 10 UNIT pF pF Note: This parameter is guaranteed by device characterization and is not production tested. AC TEST CONDITIONS PARAMETER CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level 0.6V to 0.7Vcc 3.0 ns 1.4V C L =30pF+1TTL Load(45/55/70ns) C L =100pF+1TTL Load(Load for 100ns) Output Load AC TEST LOADS AND WAVEFORM TTL DQ RL 50 ohm C L* CL 30 pF Z0 = 50 ohm Vt =1.4V Fig.B Output Load Equivalent Fig.A * Including Scope and Jig Capacitance TM Technology Inc. reserves the right to change products or specifications without notice. P. 5 Publication Date: NOV. 2002 Revision:A tm TE CH T15V2M16B AC CHARACTERISTICS( Vcc =2.7 to 3.6V, VSS = 0V, Ta = -10 ~ +70 °C / -40°C ~ 85°C) (1) READ CYCLE PARAMETER -45 SYM. Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Output Hold from Address Change Chip Enable to Output in Low-Z Chip Disable to Output in High-Z Output Enable to Output in Low-Z Output Disable to Output in High-Z LB , UB Access Time LB , UB Enable to Output in Low-Z LB , UB Disable to Output in High-Z tRC tAA tACE tOE tOH tLZ tHZ tOLZ tOHZ tBA tBLZ tBHZ -55 -70 -100 UNIT Min Max Min Max Min Max Min Max 45 10 10 5 10 45 45 25 15 15 45 - 55 10 10 5 10 55 55 30 20 20 55 - 70 10 10 5 10 70 70 35 25 25 70 - 100 10 10 5 10 100 100 50 30 30 100 - ns ns ns ns ns ns ns ns ns ns ns - 15 - 20 - 25 - 30 ns (2)WRITE CYCLE PARAMETER Write Cycle Time Chip Enable to Write End Address Valid to Write End Address Setup Time Write Pulse Width Write Recovery Time Data Valid to Write End Data Hold Time Write Enable to Output in High-Z Output Active from Write End -45 SYM. tWC tCW tAW tAS tWP tWR tDW tDH tWHZ tOW -55 -70 -100 Min Max Min Max Min Max Min Max 45 35 35 0 30 0 20 0 5 15 - 55 50 50 0 45 0 25 0 5 20 - 70 60 60 0 50 0 30 0 5 25 - 100 80 80 0 70 0 40 0 5 30 - TM Technology Inc. reserves the right to change products or specifications without notice. P. 6 UNIT ns ns ns ns ns ns ns ns ns ns Publication Date: NOV. 2002 Revision:A tm TE CH T15V2M16B TIMING WAVEFORMS READ CYCLE 1 (Address Controlled, CE = OE = VIL , WE = VIH , LB or/and UB = VIL ) tRC Address t AA t OH DOUT Previous Data Valid Data Valid READ CYCLE 2 ( WE = VIH ) tRC Ad d re s s tA A t OH t ACE CE tHZ t BA UB / LB t BHZ tOE OE tLZ D OUT tBLZ tOLZ t OHZ High-Z DON'T CARE UNDEFINED Notes (READ CYCLE) : 1. WE are high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition referenced to VOH or VOL levels. 4. At any given temperature and voltage condition. tHZ (max.) is less than tLZ (min.) both for a given device and from device to device interconnection. 5. Transition is measured ±200mV from steady state voltage with load. This parameter is sampled and not 100% tested. 6. Device is continuously selected with CE =VIL . TM Technology Inc. reserves the right to change products or specifications without notice. P. 7 Publication Date: NOV. 2002 Revision:A tm TE CH WRITE CYCLE 1 T15V2M16B ( WE Controlled) tWC Ad d res s tAW tWR tCW CE UB / LB tA S tWP WE tWHZ tOW DOUT High-Z tDW DIN WRITE CYCLE 2 tDH Hi g h - Z ( CE Controlled) tWC Ad d res s tAW tWR tCW CE tAS UB / LB tWP WE DOUT Hig h -Z tDW DIN Hig h -Z tDH Hig h -Z DO N' T CARE UNDE FINE D TM Technology Inc. reserves the right to change products or specifications without notice. P. 8 Publication Date: NOV. 2002 Revision:A tm TE CH WRITE CYCLE 3 T15V2M16B ( UB , LB Controlled) tWC Add res s tAW tWR tCW UB / LB t AS CE tWP WE DOUT Hig h -Z tDW DIN Hig h -Z tDH Hig h -Z DO N' T CARE UNDE FINE D NOTES ( WRITE CYCLE ) : 1. A write occurs during the overlap of a low CE , a low WE . A write begins at the lateat transition among CE goes low, WE going low. A write end at the earliest transition among CE going high, WE going high. tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the later of CE going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. TM Technology Inc. reserves the right to change products or specifications without notice. P. 9 Publication Date: NOV. 2002 Revision:A tm TE CH T15V2M16B DATA RETENTION CHARACTERISTICS PARAMETER VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time SYM. VDR ICCDR tCDR TEST CONDITION CE ≥VCC -0.2V VIN ≥ Vcc -0.2V or VIN ≤ 0.2V tR MIN. 2.0 0 MAX. 15/40* - UNIT V uA ns tRC - ns *note : the data retention current ‘max=40uA’ only for –45ns . DATA RETENTION WAVEFORM (Ta = -10 ~ +70 °C / -40°C ~ 85°C) Data Retentio n Mo de Vcc Vcc_typ Vcc_typ V DR > 2.0V t CDR CE V IH tR CE > Vcc- 0. 2V TM Technology Inc. reserves the right to change products or specifications without notice. P. 10 V IH Publication Date: NOV. 2002 Revision:A tm TE CH T15V2M16B PACKAGE DIMENSIONS 44-LEAD TSOP-II D 44 23 E2 E E1 L1 22 INDEX MARK Mirror finish c e b b1 A £c A3 A2 SEATING PLANE c1 Symbol A A1 A2 A3 b b1 c c1 D e E E1 E2 L L1 θ Dimension in mm Min Nom Max 1.20 0.05 0.1 0.95 1.00 1.05 0.25 0.35(typ) 0.10 0. 15 0.25 0.805 0.10 18.31 18.41 18.51 0.80(typ) 11.56 11.76 11.96 10.03 10.16 10.29 10.76 0.4 0.5 0.6 0.8(typ) 0 8 A1 L Dimension in inch Min Nom Max 0.047 0.002 0.004 0.037 0.039 0.041 0.010 0.014(typ) 0.004 0.006 0.010 0.032 0.004 0.721 0.725 0.729 0.031(typ) 0.455 0.463 0.471 0.394 0.400 0.405 0.458 0.016 0.020 0.024 0.032(typ) 0 8 TM Technology Inc. reserves the right to change products or specifications without notice. P. 11 Publication Date: NOV. 2002 Revision:A tm TE CH T15V2M16B PACKAGE DIMENSIONS 48-pin CSP (8 row x 6 column) 48 BALL FINE PITCH BGA (0.75mm ball pitch) Units : millimeters B ottom V ie w To p V ie w A 1 IN DE X MA RK B 0 .5 0 B1 0.50 # A1 C C1 C1/2 B /2 A Y E2 D E Symbol A B B1 C C1 D E E1 E2 Y min 5.95 7.95 0.25 0.20 - typ 0.75 6.00 3.75 8.00 5.25 0.30 1.10 0.95 0.25 - max 6.05 8.05 0.35 1.20 0.30 0.08 0.3 6 E1 Notes : 1. Bump counts : 48 (8 row x 6column) 2. Bump pitch : (x,y)=(0.75 x 0.75) typ. 3. All tolerance are ±0.050 unless otherwise specified. 4. ‘Y’ is coplanarity : 0.08(max) 5. Units : mm TM Technology Inc. reserves the right to change products or specifications without notice. P. 12 Publication Date: NOV. 2002 Revision:A