RENESAS R5F10RLAANB

Preliminary Datasheet
Specifications in this document are tentative and subject to change.
RL78/L12
R01DS0157EJ0001
Rev.0.01
2012.02.20
RENESAS MCU
Integrated LCD controller/driver, True Low Power Platform (as low as 75 µA/MHz, and 0.64 µA for RTC +
LVD), 1.6 V to 5.5 V operation, 8 to 32 Kbyte Flash, 31 DMIPS at 24 MHz, for All LCD Based Applications
1.
1.1
OUTLINE
Features
Ultra-Low Power Technology
• 1.6 V to 5.5 V operation from a single supply
• Stop (RAM retained): 0.23 µA, (LVD enabled): 0.31
µA
• Halt (RTC + LVD): 0.64 µA
• Supports snooze
• Operating: 75 µA/MHz
• LCD operating current (Capacitor split method): 0.12
µA
• LCD operating current (Internal voltage boost
method): 1.0 µA
16-bit RL78 CPU Core
• Delivers 31 DMIPS at maximum operating frequency
of 24 MHz
• Instruction Execution: 86% of instructions can be
executed in 1 to 2 clock cycles
• CISC Architecture (Harvard) with 3-stage pipeline
• Multiply Signed & Unsigned: 16 x 16 to 32-bit result in
1 clock cycle
• MAC: 16 x 16 to 32-bit result in 2 clock cycles
• 16-bit barrel shifter for shift & rotate in 1 clock cycle
• 1-wire on-chip debug function
Code Flash Memory
• Density: 8 KB to 32 KB
• Block size: 1 KB
• On-chip single voltage flash memory with protection
from block erase/writing
• Self-programming with secure boot swap function
and flash shield window function
Data Flash Memory
• Data flash with background operation
• Data flash size: 2 KB size
• Erase cycles: 1 Million (typ.)
• Erase/programming voltage: 1.8 V to 5.5 V
RAM
• 1 KB and 1.5 KB size options
• Supports operands or instructions
• Back-up retention in all modes
High-speed On-chip Oscillator
• 24 MHz with +/− 1% accuracy over voltage (1.8 V to
5.5 V) and temperature (−20°C to 85°C) <target>
• Pre-configured settings: 24 MHz, 16 MHz, 12 MHz, 8
MHz, 4 MHz & 1 MHz
Reset and Supply Management
• Power-on reset (POR) monitor/generator
• Low voltage detection (LVD) with 14 setting options
(Interrupt and/or reset function)
R01DS0157EJ0001 Rev.0.01
2012.02.20
LCD Controller/Driver
• Up to 35 seg x 8 com or 39 seg x 4 com
• Supports capacitor split method, internal voltage
boost method and resistance division method
• Supports waveform types A and B
• Supports LCD contrast adjustment (18 steps)
• Supports LCD blinking
Data Memory Access (DMA) Controller
• Up to 2 fully programmable channels
• Transfer unit: 8- or 16-bit
Multiple Communication Interfaces
2
• Up to 1 × I C multi-master
• Up to 2 × CSI/SPI (7-, 8-bit)
• Up to 1 × UART (7-, 8-, 9-bit)
• Up to 1 × LIN
Extended-Function Timers
• Multi-function 16-bit timers: Up to 8 channels
• Real-time clock (RTC): 1 channel (full calendar and
alarm function with watch correction function)
• Interval Timer: 12-bit, 1 channel
• 15 kHz watchdog timer: 1 channel (window function)
Rich Analog
• ADC: Up to 10 channels, 10-bit resolution, 2.1 µs
conversion time
• Supports 1.6 V
• Internal voltage reference (1.45 V)
• On-chip temperature sensor
Safety Features (IEC or UL 60730 compliance)
• Flash memory CRC calculation
• RAM parity error check
• RAM write protection
• SFR write protection
• Illegal memory access detection
• Clock frequency detection
• ADC self-test
General Purpose I/O
• 5V tolerant, high-current (up to 20 mA per pin)
• Open-Drain, Internal Pull-up support
Operating Ambient Temperature
• Standard: −40 °C to +85 °C
Package Type and Pin Count
From 7mm x 7mm to 12mm x 12mm
QFP: 32, 44, 48, 52, 64
QFN: 64
Page 1 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
1. OUTLINE
{ ROM, RAM capacities
Flash
Data
ROM
flash
32 KB
2 KB
RAM
1.5
RL78/L12
32 pins
44 pins
48 pins
52 pins
64 pins
R5F10RBC
R5F10RFC
R5F10RGC
R5F10RJC
R5F10RLC
R5F10RBA
R5F10RFA
R5F10RGA
R5F10RJA
R5F10RLA
R5F10RB8
R5F10RF8
R5F10RG8
R5F10RJ8
−
Note
KB
16 KB
2 KB
1
KB
8KB
2 KB
1
KB
Note
Note
Note
In the case of the 1 KB, and 1.5 KB, this is 630 bytes when the self-programming function and data flash
function is used.
Remark The functions mounted depend on the product. See 1.6 Outline of Functions.
1.2
Ordering Information
• Flash memory version (lead-free product)
Pin count
Package
Part Number
32 pins
32-pin plastic LQFP (7 × 7)
R5F10RB8AFP, R5F10RBAAFP, R5F10RBCAFP
44 pins
44-pin plastic LQFP (10 × 10)
R5F10RF8AFP, R5F10RFAAFP, R5F10RFCAFP
48 pins
48-pin plastic LQFP
R5F10RG8AFB, R5F10RGAAFB, R5F10RGCAFB
(fine pitch) (7 × 7)
52 pins
52-pin plastic LQFP (10 × 10)
R5F10RJ8AFA, R5F10RJAAFA, R5F10RJCAFA
64 pins
64-pin plastic WQFN (8 × 8)
R5F10RLAANB, R5F10RLCANB
64-pin plastic LQFP (fine pitch)
R5F10RLAAFB, R5F10RLCAFB
(10 × 10)
4-pin plastic LQFP (12 × 12)
R01DS0157EJ0001 Rev.0.01
2012.02.20
R5F10RLAAFA, R5F10RLCAFA
Page 2 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
1.3
1.3.1
1. OUTLINE
Pin Configuration (Top View)
32-pin products
COM0
COM1
COM2
COM3
COMEXP/SEG0
P15/SCK01/INTP1/SEG4
P16/SI01/INTP2/SEG5
P17/SO01/TI02/TO02/SEG6
• 32-pin plastic LQFP (7 × 7)
24 23 22 21 20 19 18 17
25
16
26
15
27
14
28
13
29
12
30
11
31
10
32
9
1 2 3 4 5 6 7 8
P30/TI01/TO01/SEG19
VL4
VL2
VL1
P126/CAPL
P127/CAPH
P61/SDAA0/SEG20
P60/SCLA0/SEG21
P40/TOOL0
RESET
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P14/ANI19/SEG32
P13/ANI18/TI00/SEG31
P12/SO00/TXD0/TOOLTxD/KR0/SEG30/(TI02)/(TO02)
P11/SI00/RXD0/TOOLRxD/KR1/SEG29/(INTP2)
P10/SCK00/TI07/TO07/KR2/SEG28/(INTP1)
P140/TO00/PCLBUZ0/KR3/SEG27
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4
Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 3 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
1.3.2
1. OUTLINE
44-pin products
COM0
COM1
COM2
COM3
COM4/COMEXP/SEG0
COM5/SEG1
COM6/SEG2
COM7/SEG3
P15/SCK01/INTP1/SEG4
P16/SI01/INTP2/SEG5
P17/SO01/TI02/TO02/SEG6
• 44-pin plastic LQFP (10 × 10)
33 32 31 30 29 28 27 26 25 24 23
34
35
36
37
38
39
40
41
42
43
44
22
21
20
19
18
17
16
15
14
13
12
1 2 3 4 5 6 7 8 9 10 11
P32/TI03/TO03/INTP4/SEG17
P31/INTP3/RTC1HZ/SEG18
P30/TI01/TO01/SEG19
P125/VL3
VL4
VL2
VL1
P126/CAPL
P127/CAPH
P61/SDAA0/SEG20
P60/SCLA0/SEG21
P120/ANI17/SEG25
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P143/ANI21/SEG34
P142/ANI20/SEG33
P14/ANI19/SEG32
P13/ANI18/SEG31
P12/SO00/TxD0/TOOLTxD/KR0/SEG30/(TI02)/(TO02)
P11/SI00/RxD0/TOOLRxD/KR1/SEG29/(INTP2)
P10/SCK00/TI07/TO07/KR2/SEG28/(INTP1)
P140/TO00/PCLBUZ0/KR3/SEG27
P141/TI00/PCLBUZ1/SEG26
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4
Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 4 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
1.3.3
1. OUTLINE
48-pin products
COM0
COM1
COM2
COM3
COM4/COMEXP/SEG0
COM5/SEG1
COM6/SEG2
COM7/SEG3
P15/SCK01/INTP1/SEG4
P16/SI01/INTP2/SEG5
P17/SO01/TI02/TO02/SEG6
P50/INTP5/SEG7/(PCLBUZ0)
• 48-pin plastic LQFP (fine pitch) (7 × 7)
36 35 34 33 32 31 30 29 28 27 26 25
24
37
23
38
22
39
21
40
20
41
19
42
18
43
17
44
16
45
15
46
14
47
13
48
1 2 3 4 5 6 7 8 9 10 11 12
P70/KR0/SEG16
P32/TI03/TO03/INTP4/KR1/SEG17
P31/INTP3/RTC1HZ/KR2/SEG18
P30/TI01/TO01/KR3/SEG19
P125/VL3
VL4
VL2
VL1
P126/CAPL
P127/CAPH
P61/SDAA0/SEG20
P60/SCLA0/SEG21
P120/ANI17/SEG25
P41/ANI16/TI04/TO04/SEG24
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P144/ANI22/SEG35
P143/ANI21/SEG34
P142/ANI20/SEG33
P14/ANI19/SEG32
P13/ANI18/SEG31
P12/SO00/TxD0/TOOLTxD/SEG30/(TI02)/(TO02)
P11/SI00/RxD0/TOOLRxD/SEG29/(INTP2)
P10/SCK00/TI07/TO07/SEG28/(INTP1)
P140/TO00/PCLBUZ0/SEG27
P141/TI00/PCLBUZ1/SEG26
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4
Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 5 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
1.3.4
1. OUTLINE
52-pin products
P51/TI06/TO06/SEG8
P50/INTP5/SEG7/(PCLBUZ0)
P17/SO01/TI02/TO02/SEG6
P16/SI01/INTP2/SEG5
P15/SCK01/INTP1/SEG4
COM7/SEG3
COM6/SEG2
COM5/SEG1
COM4/COMEXP/SEG0
COM3
COM2
COM1
COM0
• 52-pin plastic LQFP (10 × 10)
39 38 37 36 35 34 33 32 31 30 29 28 27
24
P32/TI03/TO03/INTP4/SEG17
P144/ANI22/SEG35
43
23
P31/INTP3/RTC1HZ/KR2/SEG18
P143/ANI21/SEG34
44
22
P30/TI01/TO01/KR3/SEG19
P142/ANI20/SEG33
45
21
P125/VL3
P14/ANI19/SEG32
46
20
VL4
P13/ANI18/SEG31
47
19
VL2
P12/SO00/TxD0/TOOLTxD/SEG30/(TI02)/(TO02)
48
18
VL1
P11/SI00/RxD0/TOOLRxD/SEG29/(INTP2)
49
17
P126/CAPL
P10/SCK00/TI07/TO07/SEG28/(INTP1)
50
16
P127/CAPH
P140/TO00/PCLBUZ0/SEG27
51
15
P61/SDAA0/SEG20
P141/TI00/PCLBUZ1/SEG26
52
14
P60/SCLA0/SEG21
VDD
VSS
8 9 10 11 12 13
REGC
6 7
P121/X1
5
P122/X2/EXCLK
3 4
P123/XT1
2
P40/TOOL0
1
P137/INTP0
42
P124/XT2/EXCLKS
P70/KR0/SEG16
P145/ANI23/SEG36
RESET
25
P42/TI05/TO05/SEG23
P71/KR1/SEG15
41
P120/ANI17/SEG25
26
P20/ANI0/AVREFP
P41/ANI16/TI04/TO04/SEG24
P21/ANI1/AVREFM
40
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4
Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 6 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
1.3.5
1. OUTLINE
64-pin products
COM0
COM1
COM2
COM3
COM4/COMEXP/SEG0
COM5/SEG1
COM6/SEG2
COM7/SEG3
P15/SCK01/INTP1/SEG4
P16/SI01/INTP2/SEG5
P17/SO01/TI02/TO02/SEG6
P50/INTP5/SEG7/(PCLBUZ0)
P51/TI06/TO06/SEG8
P52/INTP6/SEG9
P53/TI07/TO07/SEG10/(INTP1)
P54/SEG11/(TI02)/(TO02)/(INTP2)
• 64-pin plastic WQFN (8 × 8)
exposed die pad
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P130
P147/SEG38
P146/SEG37
P145/ANI23/SEG36
P144/ANI22/SEG35
P143/ANI21/SEG34
P142/ANI20/SEG33
P14/ANI19/SEG32
P13/ANI18/SEG31
P12/SO00/TxD0/TOOLTxD/SEG30
P11/SI00/RxD0/TOOLRxD/SEG29
P10/SCK00/SEG28
P140/TO00/PCLBUZ0/SEG27/(INTP6)
P141/TI00/PCLBUZ1/SEG26/(INTP7)
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
6 7 8 9 10 11 12 13 14 15 16
P120/ANI17/SEG25
P41/ANI16/TI04/TO04/SEG24
P42/TI05/TO05/SEG23
P43/INTP7/SEG22
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
EVSS
VDD
EVDD
1 2 3 4 5
P74/SEG12
P73/KR3/SEG13
P72/KR2/SEG14
P71/KR1/SEG15
P70/KR0/SEG16
P32/TI03/TO03/INTP4/SEG17
P31/INTP3/RTC1HZ/SEG18
P30/TI01/TO01/SEG19
P125/VL3
VL4
VL2
VL1
P126/CAPL
P127/CAPH
P61/SDAA0/SEG20
P60/SCLA0/SEG21
Cautions 1. Make EVSS pin the same potential as VSS pin.
2. Make VDD pin the potential that is higher than EVDD pin.
3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4
Pin Identification.
2. When using the microcontroller for an application where the noise generated inside the
microcontroller must be reduced, it is recommended to supply separate powers to the VDD and
EVDD pins and connect the VSS and EVSS pins to separate ground lines.
3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 7 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
1. OUTLINE
• 64-pin plastic LQFP (fine pitch) (10 × 10)
COM0
COM1
COM2
COM3
COM4/COMEXP/SEG0
COM5/SEG1
COM6/SEG2
COM7/SEG3
P15/SCK01/INTP1/SEG4
P16/SI01/INTP2/SEG5
P17/SO01/TI02/TO02/SEG6
P50/INTP5/SEG7/(PCLBUZ0)
P51/TI06/TO06/SEG8
P52/INTP6/SEG9
P53/TI07/TO07/SEG10/(INTP1)
P54/SEG11/(TI02)/(TO02)/(INTP2)
• 64-pin plastic LQFP (12 × 12)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P130
P147/SEG38
P146/SEG37
P145/ANI23/SEG36
P144/ANI22/SEG35
P143/ANI21/SEG34
P142/ANI20/SEG33
P14/ANI19/SEG32
P13/ANI18/SEG31
P12/SO00/TxD0/TOOLTxD/SEG30
P11/SI00/RxD0/TOOLRxD/SEG29
P10/SCK00/SEG28
P140/TO00/PCLBUZ0/SEG27/(INTP6)
P141/TI00/PCLBUZ1/SEG26/(INTP7)
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
6 7 8 9 10 11 12 13 14 15 16
P120/ANI17/SEG25
P41/ANI16/TI04/TO04/SEG24
P42/TI05/TO05/SEG23
P43/INTP7/SEG22
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
EVSS
VDD
EVDD
1 2 3 4 5
P74/SEG12
P73/KR3/SEG13
P72/KR2/SEG14
P71/KR1/SEG15
P70/KR0/SEG16
P32/TI03/TO03/INTP4/SEG17
P31/INTP3/RTC1HZ/SEG18
P30/TI01/TO01/SEG19
P125/VL3
VL4
VL2
VL1
P126/CAPL
P127/CAPH
P61/SDAA0/SEG20
P60/SCLA0/SEG21
Cautions 1. Make EVSS pin the same potential as VSS pin.
2. Make VDD pin the potential that is higher than EVDD pin.
3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4
Pin Identification.
2. When using the microcontroller for an application where the noise generated inside the
microcontroller must be reduced, it is recommended to supply separate powers to the VDD and
EVDD pins and connect the VSS and EVSS pins to separate ground lines.
3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 8 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
1.4
1. OUTLINE
Pin Identification
ANI0, ANI1,
P120 to P127:
Port 12
ANI16 to ANI23:
Analog Input
P130, P137:
Port 13
AVREFM:
Analog Reference
P140 to P147:
Port 14
Voltage Minus
PCLBUZ0, PCLBUZ1:
Programmable Clock
AVREFP:
CAPH, CAPL:
Analog Reference
Output/Buzzer Output
Voltage Plus
REGC:
Regulator Capacitance
Capacitor for LCD
RESET:
Reset
RTC1HZ:
Real-time Clock Correction Clock
COM0 to COM7,
COMEXP:
LCD Common Output
EVDD:
Power Supply for Port
RxD0:
Receive Data
EVSS:
Ground for Port
SCK00, SCK01:
Serial Clock Input/Output
EXCLK:
External Clock Input
SCLA0:
Serial Clock Input/Output
(Main System Clock)
SDAA0:
Serial Data Input/Output
External Clock Input
SEG0 to SEG38:
LCD Segment Output
(Sub System Clock)
SI00, SI01:
Serial Data Input
INTP0 to INTP7:
External Interrupt Input
SO00, SO01:
Serial Data Output
KR0-KR3:
Key Return
TI00 to TI07:
Timer Input
P10 to P17:
Port 1
TO00 to TO07:
Timer Output
P20, P21:
Port 2
TOOL0:
Data Input/Output for Tool
P30 to P32:
Port 3
TOOLRxD, TOOLTxD:
Data Input/Output for External Device
P40 to P43:
Port 4
TxD0:
Transmit Data
P50 to P54:
Port 5
VDD:
Power Supply
P60, P61:
Port 6
VL1 to VL4:
LCD Power Supply
P70 to P74:
Port 7
VSS:
Ground
X1, X2:
Crystal Oscillator (Main System Clock)
XT1, XT2:
Crystal Oscillator (Subsystem Clock)
EXCLKS:
R01DS0157EJ0001 Rev.0.01
2012.02.20
(1 Hz) Output
Page 9 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
1.5
1. OUTLINE
Block Diagram
1.5.1
32-pin products
TIMER ARRAY
UNIT0 (8ch)
TI00/P13
TO00/P140
ch0
TI01/TO01/P30
ch1
TI02/TO02/P17
(TI02/TO02/P12)
ch2
INTERVAL
TIMER
ch3
ch4
2
ANI0/P20, ANI1/P21
2
ANI18/P13, ANI19/P14
PORT 1
8
P10 to P17
PORT 2
2
P20, P21
PORT 3
P30
PORT 4
P40
A/D CONVERTER
ch5
AVREFP/P20
AVREFM/P21
ch6
PORT 6
2
P60, P61
ch7
TI07/TO07/P10
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
PORT 12
RL78
CPU
CORE
2
P126, P127
2
P121, P122
CODE FLASH MEMORY
PORT 13
P137
PORT 14
P140
DATA FLASH MEMORY
REAL-TIME
CLOCK
BUZZER OUTPUT
PCLBUZ0/P140
SERIAL ARRAY
UNIT0 (2ch)
RxD0/P11
TxD0/P12
UART0
CLOCK OUTPUT
CONTROL
RAM
KEY RETURN
SCK00/P10
SI00/P11
SO00/P12
CSI00
SCK01/P15
SI01/P16
SO01/P17
CSI01
POWER ON RESET/
VOLTAGE
DETECTOR
VDD
VSS
3
KR0/P12 to KR2/P10
KR3/P140
POR/LVD
CONTROL
TOOLRxD/P11,
TOOLTxD/P12
RESET CONTROL
SDAA0/P61
SERIAL
INTERFACE IICA0
SCLA0/P60
MULTIPLIER&
DIVIDER,
MULITIPLYACCUMULATOR
SEG0, SEG4 to SEG6,
SEG19 to SEG21,
SEG27 to SEG32
COM0 to COM3, COMEXP
VL1, VL2, VL4
CAPH
CAPL
13
5
LCD
CONTROLLER/
DRIVER
DIRECT MEMORY
ACCESS CONTROL
TOOL0/P40
ON-CHIP DEBUG
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
ON-CHIP
OSCILLATOR
VOLTAGE
REGULATOR
REGC
RAM SPACE
FOR LCD DATA
INTP0/P137
2
BCD
ADJUSTMENT
Remark
INTP1/P15(INTP1/P10),
INTP2/P16(INTP2/P11)
INTERRUPT
CONTROL
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 10 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
1.5.2
1. OUTLINE
44-pin products
TIMER ARRAY
UNIT0 (8ch)
TI00/P141
TO00/P140
ch0
TI01/TO01/P30
ch1
TI02/TO02/P17
(TI02/TO02/P12)
ch2
TI03/TO03/P32
ch3
INTERVAL
TIMER
2
ch4
ANI0/P20, ANI1/P21
ANI17/P120, ANI18/P13,
ANI19/P14
ANI20/P142, ANI21/P143
3
A/D CONVERTER
ch5
2
PORT 1
8
P10 to P17
PORT 2
2
P20, P21
PORT 3
3
P30 to P32
PORT 4
P40
AVREFP/P20
AVREFM/P21
ch6
PORT 6
2
P60, P61
ch7
TI07/TO07/P10
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
PORT 12
RL78
CPU
CORE
4
P120, P125 to P127
4
P121 to P124
CODE FLASH MEMORY
PORT 13
P137
DATA FLASH MEMORY
PORT 14
4
P140 to P143
2
PCLBUZ0/P140,
PCLBUZ1/P141
3
KR0/P12 to KR2/P10
REAL-TIME
CLOCK
RTC1HZ/P31
BUZZER OUTPUT
SERIAL ARRAY
UNIT0 (2ch)
RxD0/P11
TxD0/P12
UART0
CLOCK OUTPUT
CONTROL
RAM
KEY RETURN
SCK00/P10
SI00/P11
SO00/P12
CSI00
SCK01/P15
SI01/P16
SO01/P17
CSI01
POWER ON RESET/
VOLTAGE
DETECTOR
VDD
VSS
KR3/P140
POR/LVD
CONTROL
TOOLRxD/P11,
TOOLTxD/P12
RESET CONTROL
SDAA0/P61
SERIAL
INTERFACE IICA0
SCLA0/P60
MULTIPLIER&
DIVIDER,
MULITIPLYACCUMULATOR
SEG0 to SEG6,
SEG17 to SEG21,
SEG25 to SEG34
COM0 to COM7, COMEXP
VL1 to VL4
CAPH
CAPL
22
9
LCD
CONTROLLER/
DRIVER
TOOL0/P40
ON-CHIP DEBUG
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
XT1/P123
ON-CHIP
OSCILLATOR
XT2/EXCLKS/P124
VOLTAGE
REGULATOR
REGC
RAM SPACE
FOR LCD DATA
BCD
ADJUSTMENT
Remark
DIRECT MEMORY
ACCESS CONTROL
INTP0/P137
INTERRUPT
CONTROL
2
INTP1/P15(INTP1/P10),
INTP2/P16(INTP2/P11)
2
INTP3/P31,
INTP4/P32
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 11 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
1.5.3
1. OUTLINE
48-pin products
TIMER ARRAY
UNIT0 (8ch)
TI00/P141
TO00/P140
ch0
TI01/TO01/P30
ch1
TI02/TO02/P17
(TI02/TO02/P12)
ch2
TI03/TO03/P32
ch3
INTERVAL
TIMER
2
ch4
TI04/TO04/P41
ANI0/P20, ANI1/P21
ANI16/P41, ANI17/P120,
ANI18/P13, ANI19/P14
ANI20/P142 to ANI22/P144
4
A/D CONVERTER
ch5
3
PORT 1
8
P10 to P17
PORT 2
2
P20, P21
PORT 3
3
P30 to P32
PORT 4
2
P40, P41
PORT 5
P50
AVREFP/P20
AVREFM/P21
ch6
PORT 6
2
P60, P61
ch7
TI07/TO07/P10
PORT 7
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
PORT 12
RL78
CPU
CORE
P70
4
P120, P125 to P127
4
P121 to P124
CODE FLASH MEMORY
PORT 13
P137
DATA FLASH MEMORY
PORT 14
5
P140 to P144
2
PCLBUZ0/P140
(PCLBUZ0/P50),
PCLBUZ1/P141
REAL-TIME
CLOCK
RTC1HZ/P31
BUZZER OUTPUT
SERIAL ARRAY
UNIT0 (2ch)
RxD0/P11
TxD0/P12
UART0
CLOCK OUTPUT
CONTROL
RAM
KEY RETURN
SCK00/P10
SI00/P11
SO00/P12
CSI00
SCK01/P15
SI01/P16
SO01/P17
CSI01
POWER ON RESET/
VOLTAGE
DETECTOR
VDD
VSS
KR0/P70
3
KR1/P32 to KR3/P30
POR/LVD
CONTROL
TOOLRxD/P11,
TOOLTxD/P12
RESET CONTROL
SDAA0/P61
SERIAL
INTERFACE IICA0
SCLA0/P60
MULTIPLIER&
DIVIDER,
MULITIPLYACCUMULATOR
SEG0 to SEG7,
SEG16 to SEG21,
SEG24 to SEG35
COM0 to COM7, COMEXP
VL1 to VL4
CAPH
CAPL
26
9
LCD
CONTROLLER/
DRIVER
DIRECT MEMORY
ACCESS CONTROL
TOOL0/P40
ON-CHIP DEBUG
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
XT1/P123
ON-CHIP
OSCILLATOR
XT2/EXCLKS/P124
VOLTAGE
REGULATOR
REGC
RAM SPACE
FOR LCD DATA
BCD
ADJUSTMENT
INTP0/P137
INTERRUPT
CONTROL
2
INTP1/P15(INTP1/P10),
INTP2/P16(INTP2/P11)
2
INTP3/P31,
INTP4/P32
INTP5/P50
Remark
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 12 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
1.5.4
1. OUTLINE
52-pin products
TIMER ARRAY
UNIT0 (8ch)
TI00/P141
TO00/P140
ch0
TI01/TO01/P30
ch1
TI02/TO02/P17
(TI02/TO02/P12)
ch2
TI03/TO03/P32
ch3
INTERVAL
TIMER
2
ch4
TI04/TO04/P41
4
A/D CONVERTER
TI05/TO05/P42
ch5
TI06/TO06/P51
ch6
TI07/TO07/P10
ch7
ANI0/P20, ANI1/P21
ANI16/P41, ANI17/P120,
ANI18/P13, ANI19/P14
ANI20/P142 to ANI23/P145
4
8
P10 to P17
PORT 2
2
P20, P21
PORT 3
3
P30 to P32
PORT 4
3
P40 to P42
PORT 5
2
P50, P51
PORT 6
2
P60, P61
PORT 7
2
P70, P71
AVREFP/P20
AVREFM/P21
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
PORT 1
PORT 12
RL78
CPU
CORE
4
P120, P125 to P127
4
P121 to P124
CODE FLASH MEMORY
PORT 13
P137
DATA FLASH MEMORY
PORT 14
6
P140 to P145
2
PCLBUZ0/P140
(PCLBUZ0/P50),
PCLBUZ1/P141
REAL-TIME
CLOCK
RTC1HZ/P31
BUZZER OUTPUT
SERIAL ARRAY
UNIT0 (2ch)
RxD0/P11
TxD0/P12
UART0
CLOCK OUTPUT
CONTROL
RAM
KEY RETURN
SCK00/P10
SI00/P11
SO00/P12
CSI00
SCK10/P15
SI10/P16
SO10/P17
CSI01
POWER ON RESET/
VOLTAGE
DETECTOR
VDD
VSS
2
KR0/P70, KR1/P71
2
KR2/P31, KR3/P30
POR/LVD
CONTROL
TOOLRxD/P11,
TOOLTxD/P12
RESET CONTROL
SDAA0/P61
SERIAL
INTERFACE IICA0
SCLA0/P60
MULTIPLIER&
DIVIDER,
MULITIPLYACCUMULATOR
SEG0 to SEG8,
SEG15 to SEG21,
SEG23 to SEG36
COM0 to COM7, COMEXP
VL1 to VL4
CAPH
CAPL
30
9
LCD
CONTROLLER/
DRIVER
DIRECT MEMORY
ACCESS CONTROL
TOOL0/P40
ON-CHIP DEBUG
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
XT1/P123
ON-CHIP
OSCILLATOR
XT2/EXCLKS/P124
VOLTAGE
REGULATOR
REGC
RAM SPACE
FOR LCD DATA
BCD
ADJUSTMENT
INTP0/P137
INTERRUPT
CONTROL
2
INTP1/P15(INTP1/P10),
INTP2/P16(INTP2/P11)
2
INTP3/P31,
INTP4/P32
INTP5/P50
Remark
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 13 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
1.5.5
1. OUTLINE
64-pin products
TIMER ARRAY
UNIT0 (8ch)
TI00/P141
TO00/P140
ch0
TI01/TO01/P30
ch1
TI02/TO02/P17
(TI02/TO02/P54)
ch2
TI03/TO03/P32
ch3
INTERVAL
TIMER
2
ch4
TI04/TO04/P41
4
A/D CONVERTER
TI05/TO05/P42
ch5
TI06/TO06/P51
ch6
TI07/TO07/P53
ch7
4
ANI0/P20, ANI1/P21
ANI16/P41, ANI17/P120,
ANI18/P13, ANI19/P14
ANI20/P142 to ANI23/P145
8
P10 to P17
PORT 2
2
P20, P21
PORT 3
3
P30 to P32
PORT 4
4
P40 to P43
PORT 5
5
P50 to P54
PORT 6
2
P60, P61
PORT 7
5
P70 to P74
AVREFP/P20
AVREFM/P21
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
PORT 1
PORT 12
RL78
CPU
CORE
4
P120, P125 to P127
4
P121 to P124
CODE FLASH MEMORY
P130
P137
PORT 13
DATA FLASH MEMORY
PORT 14
8
P140 to P147
2
PCLBUZ0/P140
(PCLBUZ0/P50),
PCLBUZ1/P141
REAL-TIME
CLOCK
RTC1HZ/P31
BUZZER OUTPUT
SERIAL ARRAY
UNIT0 (2ch)
RxD0/P11
TxD0/P12
UART0
CLOCK OUTPUT
CONTROL
RAM
KEY RETURN
SCK00/P10
SI00/P11
SO00/P12
CSI00
SCK01/P15
SI01/P16
SO01/P17
CSI01
POWER ON RESET/
VOLTAGE
DETECTOR
VDD,
EVDD
KR0/P70 to
KR3/P73
4
POR/LVD
CONTROL
VSS, TOOLRxD/P11,
EVSS TOOLTxD/P12
RESET CONTROL
SDAA0/P61
SERIAL
INTERFACE IICA0
SCLA0/P60
MULTIPLIER&
DIVIDER,
MULITIPLYACCUMULATOR
SEG0 to SEG38
39
COM0 to COM7, COMEXP
VL1 to VL4
CAPH
CAPL
9
LCD
CONTROLLER/
DRIVER
DIRECT MEMORY
ACCESS CONTROL
TOOL0/P40
ON-CHIP DEBUG
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
XT1/P123
ON-CHIP
OSCILLATOR
XT2/EXCLKS/P124
VOLTAGE
REGULATOR
REGC
RAM SPACE
FOR LCD DATA
INTP0/P137
2
BCD
ADJUSTMENT
INTERRUPT
CONTROL
2
INTP1/P15(INTP1/P53),
INTP2/P16(INTP2/P54)
INTP3/P31,
INTP4/P32
INTP5/P50
INTP6/P52(INTP6/P140)
INTP7/P43(INTP7/P141)
Remark
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 14 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
1.6
1. OUTLINE
Outline of Functions
Caution
This outline describes the functions at the time when Peripheral I/O redirection register (PIOR)
is set to 00H.
(1/2)
Item
Code flash memory (KB)
32-pin
44-pin
48-pin
52-pin
64-pin
R5F10RBx
R5F10RFx
R5F10RGx
R5F10RJx
R5F10RLx
8 to 32
8 to 32
8 to 32
8 to 32
16, 32
Data flash memory (KB)
RAM (KB)
2
1, 1.5
Memory space
Main system
clock
2
Note 1
1, 1.5
2
Note 1
1, 1.5
2
Note 1
1, 1.5
2
Note 1
Note 1
1, 1.5
1 MB
High-speed system
clock
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD =
1.6 to 1.8 V
High-speed on-chip
oscillator clock
High-speed operation: 1 to 24 MHz (VDD = 2.7 to 5.5 V), High-speed operation: 1
to 16 MHz (VDD = 2.4 to 5.5 V), Low-speed operation: 1 to 8 MHz (VDD = 1.8 to 5.5
V), Low-voltage operation: 1 to 4 MHz (VDD = 1.6 to 5.5 V)
Subsystem clock
−
XT1 (crystal) oscillation , external subsystem clock input (EXCLKS)
32.768 kHz (TYP.): VDD = 1.6 to 5.5 V
Low-speed on-chip oscillator clock
Internal oscillation
15 kHz (TYP.): VDD = 1.6 to 5.5 V
General-purpose register
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution time
0.04167 μs (High-speed on-chip oscillator clock: fIH = 24 MHz operation)
0.05 μs (High-speed system clock: fMX = 20 MHz operation)
30.5 μs (Subsystem clock: fSUB = 32.768 kHz operation)
• Data transfer (8/16 bits)
• Adder and subtractor/logical operation (8/16 bits)
• Multiplication (8 bits × 8 bits)
• Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean
operation), etc.
Instruction set
I/O port
Timer
Total
20
29
33
37
47
CMOS I/O
15
22
26
30
39
CMOS input
3
5
5
5
5
CMOS output
−
−
−
−
1
N-ch open-drain I/O
(6 V tolerance)
2
2
2
2
2
16-bit timer
8 channels
8 channels (with 1 channel remote control output function)
Watchdog timer
1 channel
Real-time clock (RTC)
1 channel
Interval timer (IT)
Timer output
RTC output
Notes 1.
1 channel
5 channels
6 channels
8 channels (PWM outputs: 7
4 channels
(PWM outputs: (PWM outputs: (PWM outputs:
Note 2
Note 2
Note 2
)
4
)
5
)
3
−
Note 2
)
1
• 1 Hz (subsystem clock: fSUB = 32.768 kHz or )
In the case of the 1 KB, and 1.5 KB, this is 630 bytes when the self-programming function and data
flash function is used.
2.
The number of outputs varies, depending on the setting.
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 15 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
1. OUTLINE
(2/2)
Item
Clock output/buzzer output
32-pin
44-pin
48-pin
52-pin
64-pin
R5F10RBx
R5F10RFx
R5F10RGx
R5F10RJx
R5F10RLx
1
2
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz,
32.768 kHz
(Subsystem clock: fSUB = 32.768 kHz operation)
8/10-bit resolution A/D converter
4 channels
Serial interface
•
2
I C bus
9 channels
10 channels
10 channels
CSI: 2 channel/UART (LIN-bus supported): 1 channel
1 channel
LCD controller/driver
7 channels
1 channel
1 channel
1 channel
1 channel
Internal voltage boosting method, capacitor split method, and external resistance
division
method are switchable.
Segment signal output
13
Common signal output
4
Note 1
22 (18)
26 (22)
Note 1
30 (26)
4 (8)
Multiplier and
• 16 bits × 16 bits = 32 bits (Unsigned or signed)
divider/multiply-accumulator
• 32 bits ÷ 32 bits = 32 bits (Unsigned)
Note 1
39 (35)
Note 1
Note 1
• 16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed)
DMA controller
2 channels
Vectored interrupt Internal
23
23
23
23
23
sources
4
6
7
7
9
External
Key interrupt
4
•
Reset
Power-on-reset circuit
Reset by RESET pin
•
Internal reset by watchdog timer
•
Internal reset by power-on-reset
•
Internal reset by voltage detector
•
Internal reset by illegal instruction execution
•
Internal reset by RAM parity error
•
Internal reset by illegal-memory access
• Power-on-reset:
Note 2
1.51 ±0.03 V
• Power-down-reset: 1.50 ±0.03 V
Voltage detector
1.63 V to 4.06 V (14 stages)
On-chip debug function
Provided
Power supply voltage
VDD = 1.6 to 5.5 V
Operating ambient temperature
TA = −40 to +85 °C
Notes 1.
2.
The values in parentheses are the number of signal outputs when 8 com is used.
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or
on-chip debug emulator.
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 16 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
2.
2. ELECTRICAL SPECIFICATIONS (TARGET)
ELECTRICAL
SPECIFICATIONS (TARGET)
Cautions 1. These specifications show target values, which may change after device evaluation.
2. The RL78/L12 have an on-chip debug function, which is provided for development and
evaluation.
Do not use the on-chip debug function in products designated for mass
production, because the guaranteed number of rewritable times of the flash memory may be
exceeded when this function is used, and product reliability therefore cannot be guaranteed.
Renesas Electronics is not liable for problems occurring when the on-chip debug function is
used.
3. The pins mounted depend on the product. Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 17 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
Caution
2. ELECTRICAL SPECIFICATIONS (TARGET)
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
2.1
Absolute Maximum Ratings
Absolute Maximum Ratings (TA = 25°C) (1/3)
Parameter
Supply voltage
Symbols
Conditions
Ratings
Unit
VDD
VDD = EVDD
−0.5 to +6.5
V
EVDD
VDD = EVDD
−0.5 to +6.5
V
VSS
−0.5 to +0.3
V
EVSS
−0.5 to +0.3
V
REGC pin input voltage VIREGC
−0.3 to +2.8
REGC
V
and −0.3 to VDD +0.3
Input voltage
VI1
−0.3 to EVDD +0.3
P10 to P17, P30 to P32, P40 to P43, P50 to P54,
P70 to P74, P120, P125 to P127,
Note 1
and −0.3 to VDD +0.3
V
Note 2
P140 to P147
VI2
VI3
−0.3 to +6.5
P60, P61 (N-ch open-drain)
−0.3 to VDD +0.3
P20, P21, P121 to P124, P137, EXCLK,
V
Note 2
V
EXCLKS, RESET
Output voltage
VO1
−0.3 to EVDD +0.3
P10 to P17, P30 to P32, P40 to P43,
P50 to P54, P60, P61, P70 to P74, P120,
and −0.3 to VDD +0.3
V
Note 2
P125 to P127, P130, P140 to P147
Analog input voltage
VO2
P20, P21
VAI1
ANI16 to ANI23
−0.3 to VDD +0.3
V
−0.3 to EVDD +0.3
V
and −0.3 to AVREFP +0.3
Note 2
VAI2
−0.3 to VDD +0.3
ANI0, ANI1
V
and −0.3 to AVREFP +0.3
Note 2
Notes 1.
Connect the REGC pin to Vss via a capacitor (0.47 to 1 μ F).
absolute maximum rating of the REGC pin.
2.
This value regulates the
Do not use this pin with voltage applied to it.
Must be 6.5 V or lower.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product is
on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 18 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
Caution
2. ELECTRICAL SPECIFICATIONS (TARGET)
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
Absolute Maximum Ratings (TA = 25°C) (2/3)
Parameter
LCD voltage
Symbols
VLI1
VLI2
VLI3
VLI4
Conditions
VL1 input voltage
Note 1
VL2 input voltage
Note 1
VL3 input voltage
Note 1
VL4 input voltage
Note 1
VLI5
CAPL, CAPH input voltage
VLO1
VL1 output voltage
VLO2
VL2 output voltage
VLO3
VL3 output voltage
Unit
−0.3 to +VLI2
V
Note 2
VLI1 to VLI3
VLI2 to VLI4
Note 3
VLI3
Note 1
to +6.5
V
−0.3 to +VLO2
V
VLO2 to VLO4
Note 5
VLO5
CAPL, CAPH output voltage
VLO3
When other than
SEG0 to SEG38, resistance
a memory-type
COMEXP
liquid crystal
division method
output voltage
V
V
to +6.5
−0.3 to +6.5
COM0 to COM7, External
V
−0.3 to +6.5
Note 4
VL4 output voltage
V
V
VLO1 to VLO3
VLO4
VLO6
Ratings
V
V
−0.3 to VDD +0.3
Note 6
V
Note 6
V
waveform is
used
When a
−0.3 to VLI4 +0.3
memory-type
liquid crystal
waveform is
used
Notes 1.
Capacitor split method
−0.3 to VDD +0.3
Internal voltage boosting method
−0.3 to VLI4 +0.3
Note 6
V
Note 6
V
This value only indicates the absolute maximum ratings when applying voltage to the V L1 , VL2 ,
V L3 , and V L4 pins; it does not mean that applying voltage to these pins is recommended.
When using the internal voltage boosting method or capacitance split method, connect these
pins to V SS via a capacitor (0.47 μ F ± 30%) and connect a capacitor (0.47 μ F ± 30%)
between the CAPL and CAPH pins.
2.
3.
This is VLI4 in 32-pin products or when the 1/3 bias method is used.
This is VLI2 in 32-pin products or when the 1/3 bias method is used. It is VLI1 when the 1/2 bias
method is used. It is -0.3 in static mode.
4.
This is VLO4 in 32-pin products or when the 1/3 bias method is used.
5.
This is VLO2 in 32-pin products or when the 1/3 bias method is used. It is VLO1 when the 1/2 bias
method is used. It is -0.3 in static mode.
6.
Must be 6.5 V or lower.
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 19 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
Caution
2. ELECTRICAL SPECIFICATIONS (TARGET)
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
Absolute Maximum Ratings (TA = 25°C) (3/3)
Parameter
Output current, high
Symbols
IOH1
Conditions
Per pin
P10 to P17, P30 to P32, P40 to
Ratings
Unit
−40
mA
−70
mA
−100
mA
−0.5
mA
−1
mA
40
mA
70
mA
100
mA
1
mA
2
mA
−40 to +85
°C
−65 to +150
°C
P43, P50 to P54, P70 to P74,
P120, P125 to P127, P130, P140
to P147
Total of all pins
P10 to P14, P40 to P43, P120,
−170 mA
P130, P140 to P147
P15 to P17, P30 to P32, P50 to
P54, P70 to P74, P125-P127
IOH2
Per pin
P20, P21
Total of all pins
Output current, low
IOL1
Per pin
P10 to P17, P30 to P32, P40 to
P43, P50 to P54, P60, P61, P70
to P74, P120, P125 to P127,
P130, P140 to P147
Total of all pins
P10 to P14, P40 to P43, P120,
170 mA
P130, P140 to P147
P15 to P17, P30 to P32, P50 to
P54, P60, P61, P70 to P74, P125
to P127
IOL2
Per pin
P20, P21
Total of all pins
Operating ambient
TA
temperature
In normal operation mode
In flash memory programming mode
Storage temperature
Tstg
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product is
on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 20 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
Caution
2. ELECTRICAL SPECIFICATIONS (TARGET)
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
2.2
2.2.1
Oscillator Characteristics
Main system clock oscillator characteristics
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Recommended
Resonator
Parameter
Conditions
MIN.
TYP.
MAX.
Unit
Circuit
Ceramic resonator
VSS X1
C1
X2
Rd
X1 clock oscillation
Note
frequency (fX)
1.0
20.0
MHz
1.8 V ≤ VDD < 2.7 V
1.0
8.0
MHz
1.6 V ≤ VDD <1.8 V
1.0
4.0
MHz
2.7 V ≤ VDD ≤ 5.5 V
1.0
20.0
MHz
1.8 V ≤ VDD < 2.7 V
1.0
8.0
MHz
1.6 V ≤ VDD <1.8 V
1.0
4.0
MHz
C2
X1 clock oscillation
Crystal resonator
VSS X1
C1
2.7 V ≤ VDD ≤ 5.5 V
X2
Rd
Note
frequency (fX)
C2
Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Cautions 1. When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the
above figures to avoid an adverse effect from wiring capacitance.
•
Keep the wiring length as short as possible.
•
Do not cross the wiring with the other signal lines.
•
Do not route the wiring near a signal line through which a high fluctuating current flows.
•
Always make the ground point of the oscillator capacitor the same potential as VSS.
•
Do not ground the capacitor to a ground pattern through which a high current flows.
•
Do not fetch signals from the oscillator.
2. Since the CPU is started by the high-speed on-chip oscillator clock after a reset release,
check the X1 clock oscillation stabilization time using the oscillation stabilization time
counter status register (OSTC) by the user. Determine the oscillation stabilization time of the
OSTC register and the oscillation stabilization time select register (OSTS) after sufficiently
evaluating the oscillation stabilization time with the resonator to be used.
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 21 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
2.2.2
On-chip oscillator characteristics
(TA = −20 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Oscillators
High-speed
Parameters
Conditions
1.8 V ≤ VDD < 5.5 V
fIH
on-chip oscillator
clock frequency
1.6 V ≤ VDD <1.8 V
Note
MIN.
TYP.
MAX.
Unit
24 MHz selected
23.76
24.00
24.24
MHz
16 MHz selected
15.84
16.00
16.16
MHz
24 MHz selected
22.80
24.00
25.20
MHz
16 MHz selected
11.40
16.00
16.80
MHz
Note This only indicates the oscillator characteristics.
Refer to AC Characteristics for instruction execution
time.
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Oscillators
High-speed
Parameters
Conditions
1.8 V ≤ VDD < 5.5 V
fIH
on-chip oscillator
clock frequency
1.6 V ≤ VDD <1.8 V
Note
MIN.
TYP.
MAX.
Unit
24 MHz selected
23.64
24.00
24.36
MHz
16 MHz selected
15.76
16.00
16.24
MHz
24 MHz selected
22.68
24.00
25.32
MHz
16 MHz selected
15.12
16.00
16.88
MHz
Note This only indicates the oscillator characteristics.
Refer to AC Characteristics for instruction execution
time.
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Oscillators
Parameters
Low-speed on-chip fIL
Conditions
MIN.
TYP.
MAX.
Unit
12.75
15
17.25
kHz
oscillator clock
frequency
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 22 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
Caution
2. ELECTRICAL SPECIFICATIONS (TARGET)
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
2.2.3
Subsystem clock oscillator characteristics
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Recommended
Resonator
Items
Conditions
MIN.
TYP.
MAX.
Unit
32
32.768
35
kHz
Circuit
Crystal resonator
XT1 clock oscillation
VSS XT2
XT1
Note
frequency (fXT)
Rd
C4
C3
Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Cautions 1. When using the XT1 oscillator, wire as follows in the area enclosed by the broken lines in
the above figures to avoid an adverse effect from wiring capacitance.
•
Keep the wiring length as short as possible.
•
Do not cross the wiring with the other signal lines.
•
Do not route the wiring near a signal line through which a high fluctuating current flows.
•
Always make the ground point of the oscillator capacitor the same potential as VSS.
•
Do not ground the capacitor to a ground pattern through which a high current flows.
•
Do not fetch signals from the oscillator.
2. The XT1 oscillator is designed as a low-amplitude circuit for reducing power consumption,
and is more prone to malfunction due to noise than the X1 oscillator. Particular care is
therefore required with the wiring method when the XT1 clock is used.
Remark
For the resonator selection and oscillator constant, customers are requested to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 23 of 73
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
2.3
DC Characteristics
2.3.1
Pin characteristics
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Items
Symbol
Output current,
Note 1
high
IOH1
Conditions
TYP.
Per pin for P10 to P17, P30 to P32, P40 to P43, P50 to P54,
P70 to P74, P120, P125 to P127, P130, P140 to P147
Unit
−10.0
mA
Note 3
−40.0
mA
2.7 V ≤ EVDD < 4.0 V
−8.0
mA
1.8 V ≤ EVDD < 2.7 V
−4.0
mA
1.6 V ≤ EVDD < 1.8 V
−2.0
mA
4.0 V ≤ EVDD ≤ 5.5 V
−60.0
mA
2.7 V ≤ EVDD < 4.0 V
−15.0
mA
1.8 V ≤ EVDD < 2.7 V
−8.0
mA
1.6 V ≤ EVDD < 1.8 V
−4.0
mA
Total of all pins
Note 2
)
(When duty = 70%
−100.0
mA
P20, P21
−0.1
mA
Total of P15 to P17, P30 to P32,
P50 to P54, P70 to P74, P125 to P127
Note 2
(When duty = 70%
)
IOH2
MAX.
4.0 V ≤ EVDD ≤ 5.5 V
Total of P10 to P14, P40 to P43, P120,
P130, P140 to P147
Note 2
)
(When duty = 70%
Per pin
Total of all pins
Note 2
)
(When duty = 70%
Notes 1.
MIN.
1.6 V ≤ VDD ≤ 5.5 V
Note 3
−1.5
mA
Value of current at which the device operation is guaranteed even if the current flows from the EVDD
pin to an output pin.
2.
Specification under conditions where the duty factor is 70%.
The output current value that has changed the duty ratio can be calculated with the following
expression (when changing the duty factor from 70% to n%).
•
Total output current of pins = (IOH × 0.7)/(n × 0.01)
<Example> Where n = 50% and IOH = −10.0 mA
Total output current of pins = (−10.0 × 0.7)/(50 × 0.01) = −14.0 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
A current higher than the absolute maximum rating must not flow into one pin.
3.
Do not exceed the total current value.
Caution P10, P12, P15, P17 do not output high level in N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 24 of 73
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Items
Symbol
Output current,
Note 1
low
IOL1
Conditions
MIN.
TYP.
Per pin for P10 to P17, P30 to P32, P40 to P43,
P50 to P54, P70 to P74, P120, P125 to P127, P130,
P140 to P147
Per pin for P60, P61
20.0
mA
Note 3
15.0
Note 3
mA
70.0
mA
2.7 V ≤ EVDD < 4.0 V
15.0
mA
1.8 V ≤ EVDD < 2.7 V
9.0
mA
1.6 V ≤ EVDD < 1.8 V
4.5
mA
4.0 V ≤ EVDD ≤ 5.5 V
80.0
mA
2.7 V ≤ EVDD < 4.0 V
35.0
mA
1.8 V ≤ EVDD < 2.7 V
20.0
mA
1.6 V ≤ EVDD < 1.8 V
10.0
mA
Total of all pins
Note 2
(When duty = 70%
)
150.0
mA
P20, P21
0.4
Total of P15 to P17, P30 to P32,
P50 to P54, P60, P61, P70 to P74,
P125 to P127
Note 2
)
(When duty = 70%
Per pin for
Total of all pins
Note 2
)
(When duty = 70%
Notes 1.
Unit
4.0 V ≤ EVDD ≤ 5.5 V
Total of P10 to P14, P40 to P43,
P120, P130, P140 to P147
Note 2
(When duty = 70%
)
IOL2
MAX.
1.6 V ≤ VDD ≤ 5.5 V
Note 3
5.0
mA
mA
Value of current at which the device operation is guaranteed even if the current flows from an output
pin to the EVSS and VSS pin.
2.
Specification under conditions where the duty factor is 70%.
The output current value that has changed the duty ratio can be calculated with the following
expression (when changing the duty factor from 70% to n%).
•
Total output current of pins = (IOL × 0.7)/(n × 0.01)
<Example> Where n = 50% and IOL = 10.0 mA
Total output current of pins = (10.0 × 0.7)/(50 × 0.01) = 14.0 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
A current higher than the absolute maximum rating must not flow into one pin.
3.
Remark
Do not exceed the total current value.
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of
the port pins.
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 25 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Items
Input voltage,
Symbol
VIH1
Conditions
P10 to P17, P30 to P32, P40 to P43,
MIN.
TYP.
MAX.
Unit
Normal input buffer 0.8EVDD
EVDD
V
TTL input buffer
2.2
EVDD
V
2.0
EVDD
V
1.50
EVDD
V
VDD
V
P50 to P54, P70 to P74, P120,
high
P125 to P127, P140 to P147
VIH2
P10, P11, P15, P16
4.0 V ≤ EVDD ≤ 5.5 V
TTL input buffer
3.3 V ≤ EVDD < 4.0 V
TTL input buffer
1.6 V ≤ EVDD < 3.3 V
Input voltage,
VIH3
P20, P21
0.7VDD
VIH4
P60, P61
0.7EVDD
6.0
V
VIH5
P121 to P124, P137, EXCLK, EXCLKS, RESET
0.8VDD
VDD
V
VIL1
P10 to P17, P30 to P32, P40 to P43,
Normal input buffer
0
0.2EVDD
V
TTL input buffer
0
0.8
V
0
0.5
V
0
0.32
V
P50 to P54, P70 to P74, P120,
low
P125 to P127, P140 to P147
VIL2
P10, P11, P15, P16
4.0 V ≤ EVDD ≤ 5.5 V
TTL input buffer
3.3 V ≤ EVDD < 4.0 V
TTL input buffer
1.6 V ≤ EVDD < 3.3 V
Cautions
Remark
VIL3
P20, P21
0
0.3VDD
V
VIL4
P60, P61
0
0.3EVDD
V
VIL5
P121 to P124, P137, EXCLK, EXCLKS, RESET
0
0.2VDD
V
The maximum value of VIH of P10, P12, P15, P17 is VDD, even in the N-ch open-drain mode.
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 26 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Items
Symbol
Output voltage,
VOH1
high
Conditions
MIN.
P10 to P17, P30 to P32, P40 to P43,
4.0 V ≤ EVDD ≤ 5.5 V,
P50 to P54, P70 to P74, P120,
T.B.D.
P125 to P127, P130, P140 to P147
4.0 V ≤ EVDD ≤ 5.5 V,
TYP.
MAX.
Unit
T.B.D.
V
T.B.D.
V
T.B.D.
V
T.B.D.
V
T.B.D.
V
T.B.D
V
T.B.D.
2.7 V ≤ EVDD ≤ 5.5 V,
T.B.D.
1.8 V ≤ EVDD ≤ 5.5 V,
T.B.D.
1.6 V ≤ EVDD < 5.5 V,
T.B.D.
VOH2
P20, P21
1.6 V ≤ VDD ≤ 5.5 V,
T.B.D.
Output voltage,
VOL1
low
P10 to P17, P30 to P32, P40 to P43,
4.0 V ≤ EVDD ≤ 5.5 V,
P50 to P54, P70 to P74, P120,
T.B.D.
P125 to P127, P130, P140 to P147
4.0 V ≤ EVDD ≤ 5.5 V,
T.B.D.
V
T.B.D.
V
T.B.D.
V
T.B.D.
V
T.B.D.
V
T.B.D.
V
T.B.D.
V
T.B.D.
V
T.B.D.
V
T.B.D.
V
T.B.D.
V
T.B.D.
V
T.B.D.
2.7 V ≤ EVDD ≤ 5.5 V,
T.B.D.
2.7 V ≤ EVDD ≤ 5.5 V,
T.B.D.
1.8 V ≤ EVDD ≤ 5.5 V,
T.B.D.
1.6 V ≤ EVDD < 5.5 V,
T.B.D.
VOL2
P20, P21
1.6 V ≤ VDD ≤ 5.5 V,
T.B.D.
VOL3
P60, P61
4.0 V ≤ EVDD ≤ 5.5 V,
T.B.D.
4.0 V ≤ EVDD ≤ 5.5 V,
T.B.D.
2.7 V ≤ EVDD ≤ 5.5 V,
T.B.D.
1.8 V ≤ EVDD ≤ 5.5 V,
T.B.D.
1.6 V ≤ EVDD < 5.5 V,
T.B.D.
Caution P10, P12, P15, P17 do not output high level in N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 27 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Items
Input leakage
Symbol
ILIH1
Conditions
P10 to P17, P30 to P32,
MIN.
TYP.
MAX.
Unit
VI = EVDD
1
μA
1
μA
1
μA
10
μA
VI = EVSS
−1
μA
−1
μA
−1
μA
−10
μA
100
kΩ
P40 to P43, P50 to P54, P60,
current, high
P61, P70 to P74, P120,
P125 to P127, P140 to P147
ILIH2
P20, P21, P137, RESET
VI = VDD
ILIH3
P121 to P124
VI = VDD
In input port or
(X1, X2, XT1, XT2, EXCLK,
external clock
EXCLKS)
input
In resonator
connection
Input leakage
ILIL1
P10 to P17, P30 to P32,
P40 to P43, P50 to P54, P60,
current, low
P61, P70 to P74, P120,
P125 to P127, P140 to P147
ILIL2
P20, P21, P137, RESET
VI = VSS
ILIL3
P121 to P124
VI = VSS
In input port or
(X1, X2, XT1, XT2, EXCLK,
external clock
EXCLKS)
input
In resonator
connection
On-chip pll-up
RU
P10 to P17, P30 to P32,
VI = EVSS, In input port
10
20
P40 to P43, P50 to P54,
resistance
P70 to P74, P120,
P125 to P127, P140 to P147
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 28 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
2.3.2
Supply current characteristics
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Supply
current
IDD1
Note 1
Conditions
Operating
mode
High-speed
Note 5
operation
fIH = 24 MHz
Note 3
MIN.
Basic
VDD = 5.0 V
operation VDD = 3.0 V
Normal
VDD = 5.0 V
operation VDD = 3.0 V
fIH = 16 MHz
Note 3
Normal
VDD = 5.0 V
operation VDD = 3.0 V
Note 3
Low-speed
Note 5
operation
fIH = 8 MHz
Low-voltage
Note 5
operation
fIH = 4 MHz
High-speed
Note 5
operation
fMX = 20 MHz
Unit
T.B.D.
mA
1.8
T.B.D.
mA
3.7
T.B.D.
mA
3.7
T.B.D.
mA
2.7
T.B.D.
mA
2.7
T.B.D.
mA
T.B.D.
mA
1.2
T.B.D.
mA
Normal
VDD = 3.0 V
operation VDD = 2.0 V
1.2
T.B.D.
mA
1.2
T.B.D.
mA
Note 2
Normal
Square wave input
operation Resonator connection
3.0
T.B.D.
mA
3.2
T.B.D.
mA
Note 2
Normal
Square wave input
operation Resonator connection
3.0
T.B.D.
mA
3.2
T.B.D.
mA
Normal
Square wave input
operation Resonator connection
1.9
T.B.D.
mA
1.9
T.B.D.
mA
Normal
Square wave input
operation Resonator connection
1.9
T.B.D.
mA
1.9
T.B.D.
mA
Note 2
Normal
Square wave input
operation Resonator connection
1.1
T.B.D.
mA
1.1
T.B.D.
mA
Note 2
Normal
Square wave input
operation Resonator connection
1.1
T.B.D.
mA
1.1
T.B.D.
mA
Normal
Square wave input
operation Resonator connection
4.1
T.B.D.
μA
4.2
T.B.D.
μA
Note 4
Normal
Square wave input
operation Resonator connection
4.1
T.B.D.
μA
4.2
T.B.D.
μA
Note 4
Normal
Square wave input
operation Resonator connection
4.2
T.B.D.
μA
4.3
T.B.D.
μA
Note 4
Normal
Square wave input
operation Resonator connection
4.2
T.B.D.
μA
4.3
T.B.D.
μA
Normal
Square wave input
operation Resonator connection
4.8
T.B.D.
μA
4.9
T.B.D.
μA
Note 3
,
VDD = 5.0 V
,
Note 2
fMX = 10 MHz
,
VDD = 5.0 V
Note 2
fMX = 10 MHz
,
VDD = 3.0 V
fMX = 8 MHz
,
VDD = 3.0 V
fMX = 8 MHz
,
VDD = 2.0 V
fSUB = 32.768 kHz
Note 4
TA = −40°C
fSUB = 32.768 kHz
TA = +25°C
fSUB = 32.768 kHz
TA = +50°C
fSUB = 32.768 kHz
TA = +70°C
fSUB = 32.768 kHz
TA = +85°C
MAX.
1.8
1.2
VDD = 3.0 V
Subsystem
clock
operation
TYP.
Normal
VDD = 3.0 V
operation VDD = 2.0 V
fMX = 20 MHz
Low-speed
Note 5
operation
(1/2)
Note 4
(Notes and Remarks are listed on the next page.)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 29 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Notes 1. Total current flowing into VDD and EVDD, including the input leakage current flowing when the level of the
input pin is fixed to VDD, EVDD or VSS, EVSS. The values below the MAX. column include the peripheral
operation current (except for back ground operation (BGO)). However, not including the current flowing
into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors.
2. When high-speed on-chip oscillator and subsystem clock are stopped.
3. When high-speed system clock and subsystem clock are stopped.
4. When high-speed on-chip oscillator and high-speed system clock are stopped. When real-time clock
and watchdog timer are stopped. When AMPHS1 = 1 (Ultra-low power consumption oscillation).
5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as
below.
High speed operation: VDD = 2.4 V to 5.5 V@1 MHz to 24 MHz
Low speed operation:
VDD = 1.8 V to 5.5 V@1 MHz to 8 MHz
Low voltage operation: VDD = 1.6 V to 5.5 V@1 MHz to 4 MHz
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system
clock frequency)
2. fIH:
High-speed on-chip oscillator clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
4. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 30 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Supply
current
IDD2
Note 2
Conditions
HALT
mode
High-speed
Note 7
operation
TYP.
MAX.
Unit
fIH = 24 MHz
Note 4
VDD = 5.0 V
MIN.
0.44
T.B.D.
mA
VDD = 3.0 V
0.44
T.B.D.
mA
fIH = 16 MHz
Note 4
VDD = 5.0 V
0.40
T.B.D.
mA
VDD = 3.0 V
0.40
T.B.D.
mA
Note 1
Note 4
Low-speed
Note 7
operation
fIH = 8 MHz
Low-voltage
operation
fIH = 4 MHz
High-speed
Note 7
operation
fMX = 20 MHz
Note 4
Note 3
,
VDD = 5.0 V
Note 3
fMX = 20 MHz
,
VDD = 3.0 V
Note 3
fMX = 10 MHz
,
VDD = 5.0 V
Note 3
fMX = 10 MHz
,
VDD = 3.0 V
Low-speed
Note 7
operation
Note 3
fMX = 8 MHz
,
VDD = 3.0 V
Note 3
fMX = 8 MHz
,
VDD = 2.0 V
Subsystem
clock
operation
fSUB = 32.768 kHz
Note 5
TA = −40C
fSUB = 32.768 kHz
Note 5
TA = +25°C
fSUB = 32.768 kHz
Note 5
TA = +50°C
fSUB = 32.768 kHz
Note 5
TA = +70°C
STOP
mode
260
T.B.D.
μA
260
T.B.D.
μA
VDD = 3.0 V
420
T.B.D.
μA
VDD = 2.0 V
420
T.B.D.
μA
Square wave input
0.28
T.B.D.
mA
Resonator connection
0.45
T.B.D.
mA
Square wave input
0.28
T.B.D.
mA
Resonator connection
0.45
T.B.D.
mA
Square wave input
0.19
T.B.D.
mA
Resonator connection
0.26
T.B.D.
mA
Square wave input
0.19
T.B.D.
mA
Resonator connection
0.26
T.B.D.
mA
Square wave input
95
T.B.D.
μA
Resonator connection
145
T.B.D.
μA
Square wave input
95
T.B.D.
μA
Resonator connection
145
T.B.D.
μA
Square wave input
0.32
T.B.D.
μA
Resonator connection
0.51
T.B.D.
μA
Square wave input
0.37
T.B.D.
μA
Resonator connection
0.56
T.B.D.
μA
Square wave input
0.40
T.B.D.
μA
Resonator connection
0.59
T.B.D.
μA
Square wave input
0.43
T.B.D.
μA
Resonator connection
0.62
T.B.D.
μA
Square wave input
1.04
T.B.D.
μA
1.23
T.B.D.
μA
TA = −40°C
0.18
T.B.D.
μA
TA = +25°C
0.23
T.B.D.
μA
TA = +50°C
0.26
T.B.D.
μA
TA = +70°C
0.29
T.B.D.
μA
TA = +85°C
0.90
T.B.D.
μA
TA = +85°C
Note 6
VDD = 3.0 V
VDD = 2.0 V
Resonator connection
fSUB = 32.768 kHz
IDD3
(2/2)
Note 5
(Notes and Remarks are listed on the next page.)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 31 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Notes 1. Total current flowing into VDD and EVDD, including the input leakage current flowing when the level of the
input pin is fixed to VDD, EVDD or VSS, EVSS. The values below the MAX. column include the peripheral
operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port,
and on-chip pull-up/pull-down resistors.
2. During HALT instruction execution by flash memory.
3. When high-speed on-chip oscillator and subsystem clock are stopped.
4. When high-speed system clock and subsystem clock are stopped.
5. When operating real-time clock (RTC) and setting ultra-low current consumption (AMPHS1 = 1). When
high-speed on-chip oscillator and high-speed system clock are stopped.
When watchdog timer is
stopped.
6. When high-speed on-chip oscillator, high-speed system clock, and subsystem clock are stopped. When
watchdog timer is stopped.
7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as
below.
High speed operation: VDD = 2.4 V to 5.5 V@1 MHz to 24 MHz
Low speed operation:
VDD = 1.8 V to 5.5 V@1 MHz to 8 MHz
Low voltage operation: VDD = 1.6 V to 5.5 V@1 MHz to 4 MHz
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system
clock frequency)
2. fIH:
High-speed on-chip oscillator clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
4. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA =
25°C
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 32 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
Caution
2. ELECTRICAL SPECIFICATIONS (TARGET)
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
IRTC
Notes 1, 2
IWDT
Notes 2, 3
A/D converter
operating
current
IADC
Note 4
Temperature
sensor
operating
current
ITMPS
LVD operating
ILVI
RTC operating
Conditions
fSUB = 32.768 kHz
current
Watchdog timer
MIN.
TYP.
Real-time clock operation
0.02
Interval timer operation
0.02
fIL = 15 kHz
MAX.
Unit
μA
μA
0.22
operating
current
Normal mode, AVREFP = VDD = 5.0 V
1.3
1.7
mA
Low voltage mode, AVREFP = VDD = 3.0 V
0.5
0.7
mA
Note 5
75
μA
0.08
μA
current
BGO operating
IBGO
Note 6
2.50
12.20
mA
current
LCD operating
ILCD1
External resistance
current
Notes 7, 8
division method
ILCD2
Note7
Internal voltage
LCD clock = 128 Hz
VDD = 5.0 V
T.B.D.
T.B.D.
μA
LCD clock = 128 Hz
VDD = 3.0 V
1.0
T.B.D.
μA
LCD clock = 128 Hz
VDD = 3.0 V
0.12
T.B.D.
μA
boosting method
ILCD3
Note7
Capacitor split
method
Notes 1. Current flowing only to the real-time clock (excluding the operating current of the XT1 oscillator). The
TYP. value of the current value of the RL78/L12 is the sum of the TYP. values of either IDD1 or IDD2, and
IRTC, when the real-time clock operates in operation mode or HALT mode. The IDD1 and IDD2 MAX.
values also include the real-time clock operating current. However, IDD2 subsystem clock operation
includes the operational current of the real-time clock.
2. When high-speed on-chip oscillator and high-speed system clock are stopped.
3. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip
oscillator). The current value of the RL78/L12 is the sum of IDD1, IDD2 or IDD3 and IWDT when fCLK = fSUB
when the watchdog timer operates in STOP mode.
4. Current flowing only to the A/D converter. The current value of the RL78/L12 is the sum of IDD1 or IDD2
and IADC when the A/D converter operates in an operation mode or the HALT mode.
5. Current flowing only to the LVD circuit. The current value of the RL78/L12 is the sum of IDD1, IDD2 or
IDD3 and ILVI when the LVD circuit operates in the Operating, HALT or STOP mode.
6. Current flowing only when the BGO operates. The current value of the RL78/L12 is the sum of IDD1 or
IDD2 and IBGO when the BGO operates in an operation mode.
7. Current flowing only to the LCD controller/driver (VDD pin). The current value of the RL78/L12
microcontrollers is the sum of the LCD operating current (ILCD1, ILCD2 or ILCD3) to the supply current (IDD1,
or IDD2) when the LCD controller/driver operates in an operation mode or HALT mode. Not including the
current that flows through the LCD panel.
8. Not including the current that flows through the LCD divider resistor.
Remarks 1. fIL: Low-speed on-chip oscillator clock frequency
2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
3. fCLK: CPU/peripheral hardware clock frequency
4. Temperature condition of the TYP. value is TA = 25°C
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 33 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
Caution
2. ELECTRICAL SPECIFICATIONS (TARGET)
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
2.4
AC Characteristics
2.4.1
Basic operation
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Items
Instruction cycle (minimum
instruction execution time)
Symbol
TCY
Conditions
Main
system
clock (fMAIN)
operation
MAX.
Unit
High-speed 2.7 V ≤ VDD ≤ 5.5 V 0.04167
main mode
2.4 V ≤ VDD < 2.7 V 0.0625
1
μs
1
μs
Low voltage 1.6 V ≤ VDD ≤ 5.5 V
main mode
0.25
1
μs
1.8 V ≤ VDD ≤ 5.5 V
0.125
1
μs
1.8 V ≤ VDD ≤ 5.5 V
28.5
31.3
μs
1
1
μs
μs
Low-speed
main mode
Subsystem clock (fSUB)
operation
MIN.
In the self
High-speed 2.7 V ≤ VDD ≤ 5.5 V 0.04167
programming main mode 2.4 V ≤ VDD < 2.7 V 0.0625
mode
fEX
0.25
1
μs
1.8 V ≤ VDD ≤ 5.5 V
0.125
1
μs
2.7 V ≤ VDD ≤ 5.5 V
1.0
20.0
MHz
1.8 V ≤ VDD < 2.7 V
1.0
8.0
MHz
1.6 V ≤ VDD < 1.8 V
1.0
4.0
MHz
32
35
kHz
2.7 V ≤ VDD ≤ 5.5 V
24
ns
1.8 V ≤ VDD < 2.7 V
60
ns
1.6 V ≤ VDD < 1.8 V
120
ns
fEXS
External main system clock input
high-level width, low-level width
tEXH, tEXL
tEXHS, tEXLS
TI00 to TI07 input high-level
width, low-level width
tTIH,
tTIL
TO00 to TO07 output frequency
fTO
PCLBUZ0, PCLBUZ1 output
frequency
Interrupt input high-level width,
low-level width
fPCL
tINTH,
tINTL
Key interrupt input low-level width tKR
RESET low-level width
30.5
Low voltage 1.8 V ≤ VDD ≤ 5.5 V
main mode
Low-speed
main mode
External main system clock
frequency
TYP.
μs
13.7
Note
1/fMCK+10
High-speed main
mode
ns
4.0 V ≤ EVDD ≤ 5.5 V
12
MHz
2.7 V ≤ EVDD < 4.0 V
8
MHz
1.8 V ≤ EVDD < 2.7 V
4
MHz
1.6 V ≤ EVDD < 1.8 V
2
MHz
Low voltage main
mode
1.6 V ≤ EVDD ≤ 5.5 V
2
MHz
Low-speed main
mode
1.8 V ≤ EVDD ≤ 5.5 V
4
MHz
1.6 V ≤ EVDD < 1.8 V
2
MHz
High-speed main
mode
4.0 V ≤ EVDD ≤ 5.5 V
16
MHz
2.7 V ≤ EVDD < 4.0 V
8
MHz
1.8 V ≤ EVDD < 2.7 V
4
MHz
1.6 V ≤ EVDD < 1.8 V
2
MHz
Low voltage main
mode
1.8 V ≤ EVDD ≤ 5.5 V
4
MHz
1.6 V ≤ EVDD < 1.8 V
2
MHz
Low-speed main
mode
1.8 V ≤ EVDD ≤ 5.5 V
4
MHz
1.6 V ≤ EVDD < 1.8 V
2
MHz
INTP0
1.6 V ≤ VDD ≤ 5.5 V
1
INTP1 to INTP7
1.6 V ≤ EVDD ≤ 5.5 V
1
1.8 V ≤ EVDD ≤ 5.5 V
250
ns
1.6 V ≤ EVDD < 1.8 V
1
μs
μs
KR0 to KR3
tRSL
10
μs
μs
(Note and Remark are listed on the next page.)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 34 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
Caution
2. ELECTRICAL SPECIFICATIONS (TARGET)
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
Note
The following conditions are required for low voltage interface when EVDD<VDD
1.8 V ≤ EVDD < 2.7 V : MIN. 125 ns
1.6 V ≤ EVDD < 1.8 V : MIN. 250 ns
Remark
fMCK: Timer array unit operation clock frequency
(Operation clock to be set by the CKS0n bit of timer mode register 0n (TMR0n). n: Channel number (n =
0 to 7))
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 35 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
Caution
2. ELECTRICAL SPECIFICATIONS (TARGET)
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
2.5
2.5.1
Peripheral Functions Characteristics
Serial array unit
(1) During communication at same potential (UART mode) (dedicated baud rate generator output)
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Transfer rate
Symbol
Conditions
MIN.
TYP.
Note 1
MAX.
fMCK/6
Theoretical value of the
Note 2
4.0
Unit
bps
Mbps
maximum transfer rate
fCLK=24MHz, fMCK= fCLK
UART mode connection diagram (during communication at same potential)
Rx
TxDq
User's device
RL78/L12
Tx
RxDq
UART mode bit width (during communication at same potential) (reference)
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
TxDq
RxDq
Notes 1. Transfer rate in the SNOOZE mode is max. 9600 bps, min. 4800 bps.
2. The following conditions are required for low voltage interface when EVDD<VDD.
2.4 V ≤ EVDD < 2.7 V : MAX. 2.6 Mbps
1.8 V ≤ EVDD < 2.4 V : MAX. 1.3 Mbps
1.6 V ≤ EVDD < 1.8 V : MAX. 0.6 Mbps
Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by
using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1.
2.
q: UART number (q = 0), g: PIM and POM number (g = 1)
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number,
n: Channel number (mn = 00, 01))
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 36 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
Caution
2. ELECTRICAL SPECIFICATIONS (TARGET)
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
(2) During communication at same potential (CSI mode) (master mode (fMCK/2, fMCK/4), SCKp... internal
clock output)
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
SCKp cycle time
tKCY1
Conditions
2.7 V ≤ EVDD ≤ 5.5 V
2.4 V ≤ EVDD ≤ 5.5 V
1.8 V ≤ EVDD ≤ 5.5 V
1.6 V ≤ EVDD ≤ 5.5 V
SCKp high-/low-level width
MIN.
TYP.
MAX.
Unit
167
Note 1
ns
250
Note 1
ns
500
Note 1
ns
1000
Note 1
ns
tKH1,
4.0 V ≤ EVDD ≤ 5.5 V
tKCY1/2 − 12
ns
tKL1
2.7 V ≤ EVDD ≤ 5.5 V
tKCY1/2 − 18
ns
2.4 V ≤ EVDD ≤ 5.5 V
tKCY1/2 − 38
ns
1.8 V ≤ EVDD ≤ 5.5 V
tKCY1/2 − 50
ns
1.6 V ≤ EVDD ≤ 5.5 V
tKCY1/2 −
ns
100
SIp setup time (to SCKp↑)
Note 2
SIp hold time (from SCKp↑)
Note 3
Delay time from SCKp↓ to
SOp output
tSIK1
4.0 V ≤ EVDD ≤ 5.5 V
44
ns
2.7 V ≤ EVDD ≤ 5.5 V
44
ns
2.4 V ≤ EVDD ≤ 5.5 V
75
ns
1.8 V ≤ EVDD ≤ 5.5 V
110
ns
1.6 V ≤ EVDD ≤ 5.5 V
220
ns
19
ns
tKSI1
tKSO1
Note 5
C = 30 pF
25
ns
Note 4
Notes 1. For CSI00, set a cycle of 2/fCLK or longer. For other than CSI00, set a cycle of 4/fCLK or longer.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
5. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and
SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1.
p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),
g: PIM and POM numbers (g = 1)
2.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number,
n: Channel number (mn = 00, 01))
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 37 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
Caution
2. ELECTRICAL SPECIFICATIONS (TARGET)
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
(3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
SCKp cycle time
Note 5
SCKp high-/low-level width
Symbol
tKCY2
tKH2,
Conditions
MIN.
TYP.
MAX.
Unit
4.0 V ≤ EVDD ≤
20 MHz < fMCK
8/fMCK
ns
5.5 V
fMCK ≤ 20 MHz
6/fMCK
ns
2.7 V ≤ EVDD <
16 MHz < fMCK
8/fMCK
ns
4.0 V
fMCK ≤ 16 MHz
6/fMCK
ns
1.8 V ≤ EVDD <
16 MHz < fMCK
8/fMCK
ns
2.7 V
fMCK ≤ 16 MHz
6/fMCK
ns
1.6 V ≤ EVDD < 1.8 V
6/fMCK
ns
1.6 V ≤ EVDD ≤ 5.5 V
tKCY2/2
ns
2.7 V ≤ EVDD ≤ 5.5 V
1/fMCK+20
ns
1.8 V ≤ EVDD < 2.7 V
1/fMCK+30
ns
1.6 V ≤ EVDD < 1.8 V
1/fMCK+40
ns
2.7 V ≤ EVDD ≤ 5.5 V
1/fMCK+31
ns
1.8 V ≤ EVDD < 2.7 V
1/fMCK+31
ns
1.6 V ≤ EVDD < 1.8 V
1/fMCK+
ns
tKL2
SIp setup time
(to SCKp↑)
tSIK2
Note 1
SIp hold time
(from SCKp↑)
tKSI2
Note 2
250
Delay time from SCKp↓ to
SOp output
tKSO2
C = 30 pF
Note 3
Note 4
4.0 V ≤ EVDD ≤ 5.5 V
2/fMCK+44
ns
2.7 V ≤ EVDD < 4.0 V
2/fMCK+44
ns
2.4 V ≤ EVDD < 2.7 V
2/fMCK+75
ns
1.8 V ≤ EVDD < 2.4 V
2/fMCK+110
ns
2/fMCK+
ns
1.6 V ≤ EVDD < 1.8 V
220
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. C is the load capacitance of the SOp output lines.
5. Transfer rate in the SNOOZE mode : MAX. 1 Mbps
Caution Select the TTL input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp
pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks
1. p: CSI number (p = 00, 01), m: Unit number (m = 0),
n: Channel number (n = 0, 1), g: PIM number (g = 1)
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 01))
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 38 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
Caution
2. ELECTRICAL SPECIFICATIONS (TARGET)
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
CSI mode connection diagram (during communication at same potential)
SCK
SCKp
RL78/L12
SIp
SO
SOp
SI
User's device
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY1, 2
tKL1, 2
tKH1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
Output data
SOp
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1, 2
tKH1, 2
tKL1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
SOp
Remarks 1.
2.
Output data
p: CSI number (p = 00, 01)
m: Unit number, n: Channel number (mn = 00, 01)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 39 of 73
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
RL78/L12
Caution
2. ELECTRICAL SPECIFICATIONS (TARGET)
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
(4) Communication at different potential (2.5 V, 3 V) (UART mode) (dedicated baud rate generator output) (1/2)
(TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
reception 4.0 V ≤ EVDD ≤ 5.5 V,
Transfer rate
2.7 V ≤ Vb ≤ 4.0 V
TYP.
MAX.
fMCK/6
Theoretical value of the
Unit
Note 1
4.0
bps
Mbps
maximum transfer rate
fCLK = 24 MHz, fMCK = fCLK
2.7 V ≤ EVDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V
fMCK/6
Theoretical value of the
Note 1
bps
4.0
Mbps
fMCK/6
bps
maximum transfer rate
fCLK = 24 MHz, fMCK = fCLK
1.8 V ≤ EVDD < 3.3 V,
Notes 1 to 3
1.6 V ≤ Vb ≤ 2.0 V
Theoretical value of the
1.3
Mbps
maximum transfer rate
fCLK = 8 MHz, fMCK = fCLK
Notes 1. Transfer rate in the SNOOZE mode : MAX. 9600 bps, MIN. 4800 bps
2. Use it with EVDD≥Vb.
3. The following conditions are required for low voltage interface when EVDD<VDD.
2.4 V ≤ EVDD < 2.7 V : MAX. 2.6 Mbps
1.8 V ≤ EVDD < 2.4 V : MAX. 1.3 Mbps
1.6 V ≤ EVDD < 1.8 V : MAX. 0.6 Mbps
Caution
Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode
for the TxDq pin by using port input mode register g (PIMg) and port output mode register g
(POMg).
Remarks 1.
Vb[V]: Communication line voltage
2.
q: UART number (q = 0), g: PIM and POM number (g = 1)
3.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 01)
4.
VIH and VIL below are observation points for the AC characteristics of the serial array unit when
communicating at different potentials in UART mode.
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V: VIH = 2.2 V, VIL = 0.8 V
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V: VIH = 2.0 V, VIL = 0.5 V
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V: VIH = 1.50 V, VIL = 0.32 V
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 40 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
Caution
2. ELECTRICAL SPECIFICATIONS (TARGET)
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
(4) Communication at different potential (2.5 V, 3 V) (UART mode) (dedicated baud rate generator output) (2/2)
(TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Transfer rate
Symbol
Conditions
MIN.
TYP.
transmission 4.0 V ≤ EVDD ≤ 5.5 V,
MAX.
Unit
Notes
bps
1, 2
2.7 V ≤ Vb ≤ 4.0 V
Theoretical
value
of
the
2.8
Note 3
Mbps
maximum transfer rate
Cb = 50 pF, Rb = 1.4 kΩ, Vb = 2.7 V
2.7 V ≤ EVDD < 4.0 V,
Notes
bps
2, 4
2.3 V ≤ Vb ≤ 2.7 V
Theoretical
value
of
the
1.2
Note 5
Mbps
maximum transfer rate
Cb = 50 pF, Rb = 2.7 kΩ, Vb = 2.3 V
1.8 V ≤ EVDD < 3.3 V,
Notes
1.6 V ≤ Vb ≤ 2.0 V
2, 6, 7
Theoretical
value
of
the
maximum transfer rate
bps
0.43
Mbps
Notes 8
Cb = 50 pF, Rb = 5.5 kΩ, Vb = 1.6 V
Notes 1.
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 4.0 V ≤ EVDD ≤ 5.5 V and 2.7 V ≤ Vb ≤ 4.0 V
1
Maximum transfer rate =
{−Cb × Rb × ln (1 −
Baud rate error (theoretical value) =
2.2
Vb )} × 3
[bps]
2.2
1
− {−Cb × Rb × ln (1 − Vb )}
Transfer rate × 2
1
( Transfer rate ) × Number of transferred bits
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
2.
Transfer rate in the SNOOZE mode : MAX. 9600 bps, MIN. 4800 bps
3.
This value as an example is calculated when the conditions described in the “Conditions” column are
met. Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer.
4.
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 2.7 V ≤ EVDD < 4.0 V and 2.3 V ≤ Vb ≤ 2.7 V
1
Maximum transfer rate =
{−Cb × Rb × ln (1 −
Baud rate error (theoretical value) =
2.0
Vb )} × 3
[bps]
2.0
1
− {−Cb × Rb × ln (1 − Vb )}
Transfer rate × 2
1
( Transfer rate ) × Number of transferred bits
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
5.
This value as an example is calculated when the conditions described in the “Conditions” column are
met. Refer to Note 4 above to calculate the maximum transfer rate under conditions of the customer.
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 41 of 73
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
RL78/L12
Notes 6.
7.
2. ELECTRICAL SPECIFICATIONS (TARGET)
Use it with EVDD ≥ Vb.
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 1.8 V ≤ EVDD < 3.3 V and 1.6 V ≤ Vb ≤ 2.0 V
1
Maximum transfer rate =
{−Cb × Rb × ln (1 −
Baud rate error (theoretical value) =
1.5
Vb )} × 3
[bps]
1.5
1
− {−Cb × Rb × ln (1 − Vb )}
Transfer rate × 2
1
( Transfer rate ) × Number of transferred bits
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
8.
This value as an example is calculated when the conditions described in the “Conditions” column are
met. Refer to Note 7 above to calculate the maximum transfer rate under conditions of the customer.
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode
for the TxDq pin by using port input mode register g (PIMg) and port output mode register g
(POMg).
Remarks 1.
Rb[Ω]:Communication line (TxDq) pull-up resistance,
Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage
2.
q: UART number (q = 0, 1), g: PIM and POM number (g = 1)
3.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00, 01))
4. VIH and VIL below are observation points for the AC characteristics of the serial array unit when
communicating at different potentials in UART mode.
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V: VIH = 2.2 V, VIL = 0.8 V
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V: VIH = 2.0 V, VIL = 0.5 V
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V: VIH = 1.50 V, VIL = 0.32 V
UART mode connection diagram (during communication at different potential)
Vb
Rb
TxDq
Rx
User's device
RL78/L12
RxDq
R01DS0157EJ0001 Rev.0.01
2012.02.20
Tx
Page 42 of 73
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
RL78/L12
Caution
2. ELECTRICAL SPECIFICATIONS (TARGET)
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
UART mode bit width (during communication at different potential) (reference)
1/Transfer rate
Low-bit width
High-bit width
Baud rate error tolerance
TxDq
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
RxDq
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode
for the TxDq pin by using port input mode register g (PIMg) and port output mode register g
(POMg).
Remarks 1.
2.
Rb[Ω]:Communication line (TxDq) pull-up resistance, Vb[V]: Communication line voltage
q: UART number (q = 0), g: PIM and POM number (g = 1)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 43 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
Caution
2. ELECTRICAL SPECIFICATIONS (TARGET)
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
(5) Communication at different potential (2.5 V, 3 V) (fMCK/2) (CSI mode) (master mode, SCKp... internal clock
output)
(TA = −40 to +85°C, 2.7 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
SCKp cycle time
Symbol
tKCY1
Conditions
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
MIN.
TYP.
MAX.
Unit
200
Note 1
ns
300
Note 1
ns
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SCKp high-level width
tKH1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, tKCY1/2 − 50
ns
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SCKp low-level width
tKL1
tKCY1/2 −
ns
120
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, tKCY1/2 − 7
ns
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, tKCY1/2 − 10
ns
Cb = 20 pF, Rb = 2.7 kΩ
SIp setup time
(to SCKp↑)
tSIK1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
58
ns
121
ns
10
ns
10
ns
Note 2
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SIp hold time
(from SCKp↑)
tKSI1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Note 2
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
Delay time from SCKp↓ to
SOp output
tKSO1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
60
ns
130
ns
Note 2
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SIp setup time
(to SCKp↓)
tSIK1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
23
ns
33
ns
10
ns
10
ns
Note 3
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SIp hold time
(from SCKp↓)
tKSI1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Note 3
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
Delay time from SCKp↑ to
SOp output
tKSO1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
10
ns
10
ns
Note 3
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
(Note, Caution and Remark are listed on the next page.)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 44 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
Caution
2. ELECTRICAL SPECIFICATIONS (TARGET)
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
CSI mode connection diagram (during communication at different potential)
<Master>
Vb
Rb
Vb
Rb
SCKp
RL78/L12
SCK
SIp
SO
SOp
SI
User's device
Notes 1. The value must also be 2/fCLK or more.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
3. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for
the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode
register g (POMg).
Remarks 1. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp)
load capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),
g: PIM and POM number (g = 1)
3. VIH and VIL below are observation points for the AC characteristics of the serial array unit when
communicating at different potentials in CSI mode.
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V: VIH = 2.2 V, VIL = 0.8 V
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V: VIH = 2.0 V, VIL = 0.5 V
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V: VIH = 1.50 V, VIL = 0.32 V
4. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 01)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 45 of 73
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
RL78/L12
Caution
2. ELECTRICAL SPECIFICATIONS (TARGET)
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
(6) Communication at different potential (2.5 V, 3 V) (fMCK/4) (CSI mode) (master mode, SCKp... internal clock
output) (1/2)
(TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
SCKp cycle time
Symbol
tKCY1
Conditions
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
MIN.
TYP.
MAX.
Unit
300
Note
ns
500
Note
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2.7 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
1150
Note
ns
Cb = 30 pF, Rb = 5.5 kΩ
SCKp high-level width
tKH1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, tKCY1/2 − 75
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
SCKp low-level width
tKL1
tKCY1/2 −
ns
170
tKCY1/2 −
ns
458
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, tKCY1/2 − 12
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, tKCY1/2 − 18
ns
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, tKCY1/2 − 50
ns
Cb = 30 pF, Rb = 5.5 kΩ
Note
The value must also be 4/fCLK or more.
Cautions 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance)
mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port
output mode register g (POMg).
2. Use it with EVDD ≥ Vb.
Remarks 1. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp)
load capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM and POM
number (g = 1)
3. VIH and VIL below are observation points for the AC characteristics of the serial array unit when
communicating at different potentials in CSI mode.
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V: VIH = 2.2 V, VIL = 0.8 V
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V: VIH = 2.0 V, VIL = 0.5 V
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V: VIH = 1.50 V, VIL = 0.32 V
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 46 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
Caution
2. ELECTRICAL SPECIFICATIONS (TARGET)
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
(6) Communication at different potential (2.5 V, 3 V) (fMCK/4) (CSI mode) (master mode, SCKp... internal clock
output) (2/2)
(TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
SIp setup time
Note 1
(to SCKp↑)
Symbol
tSIK1
Conditions
MIN.
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
81
TYP.
MAX.
Unit
ns
177
ns
479
ns
19
ns
19
ns
19
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
SIp hold time
Note 1
(from SCKp↑)
tKSI1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
Delay time from SCKp↓ to
Note 1
SOp output
tKSO1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
100
ns
195
ns
483
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
SIp setup time
Note 2
(to SCKp↓)
tSIK1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
44
ns
44
ns
110
ns
19
ns
19
ns
19
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
SIp hold time
Note 2
(from SCKp↓)
tKSI1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
Delay time from SCKp↑ to
Note 2
SOp output
tKSO1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
25
ns
25
ns
25
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
(Note, Caution and Remark are listed on the next page.)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 47 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
Caution
2. ELECTRICAL SPECIFICATIONS (TARGET)
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
CSI mode connection diagram (during communication at different potential)
<Master>
Vb
Rb
Vb
Rb
SCKp
RL78/L12
SCK
SIp
SO
SOp
SI
User's device
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Cautions 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance)
mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port
output mode register g (POMg).
2. Use it with EVDD ≥ Vb.
Remarks 1. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp)
load capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),
g: PIM and POM number (g = 1)
3. VIH and VIL below are observation points for the AC characteristics of the serial array unit when
communicating at different potentials in CSI mode.
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V: VIH = 2.2 V, VIL = 0.8 V
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V: VIH = 2.0 V, VIL = 0.5 V
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V: VIH = 1.50 V, VIL = 0.32 V
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 48 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
Caution
2. ELECTRICAL SPECIFICATIONS (TARGET)
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY1
tKL1
tKH1
SCKp
tSIK1
SIp
tKSI1
Input data
tKSO1
SOp
Output data
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1
tKL1
tKH1
SCKp
tSIK1
SIp
tKSI1
Input data
tKSO1
SOp
Output data
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for
the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode
register g (POMg).
Remark
p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),
g: PIM and POM number (g = 1)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 49 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
(7) Communication at different potential (2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input)
(TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
SCKp cycle time
Note 1
Symbol
tKCY2
Conditions
width
Note 2
tKH2,
TYP.
MAX.
Unit
4.0 V ≤ EVDD ≤ 5.5 V, 20 MHz < fMCK ≤ 24 MHz
12/fMCK
ns
2.7 V ≤ Vb ≤ 4.0 V
8 MHz < fMCK ≤ 20 MHz
10/fMCK
ns
4 MHz < fMCK ≤ 8 MHz
8/fMCK
ns
fMCK ≤ 4 MHz
SCKp high-/low-level
MIN.
6/fMCK
ns
2.7 V ≤ EVDD < 4.0 V, 20 MHz < fMCK ≤ 24 MHz
16/fMCK
ns
2.3 V ≤ Vb ≤ 2.7 V
16 MHz < fMCK ≤ 20 MHz
14/fMCK
ns
8 MHz < fMCK ≤ 16 MHz
12/fMCK
ns
4 MHz < fMCK ≤ 8 MHz
8/fMCK
ns
fMCK ≤ 4 MHz
6/fMCK
ns
1.8 V ≤ EVDD < 3.3 V, 20 MHz < fMCK ≤ 24 MHz
36/fMCK
ns
1.6 V ≤ Vb ≤ 2.0 V
32/fMCK
ns
8 MHz < fMCK ≤ 16 MHz
26/fMCK
ns
4 MHz < fMCK ≤ 8 MHz
16/fMCK
ns
fMCK ≤ 4 MHz
10/fMCK
ns
tKCY2/2 −
ns
Note2
16 MHz < fMCK ≤ 20 MHz
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V
tKL2
12
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V
tKCY2/2 −
ns
18
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
tKCY2/2 −
ns
50
SIp setup time
(to SCKp↑)
tSIK2
Note 3
SIp hold time
(from SCKp↑)
1/fMCK + 20
ns
1.8 V ≤ Vb ≤ 3.3 V
1/fMCK + 30
ns
1/fMCK + 31
ns
tKSI2
Note 4
Delay time from SCKp↓ to
SOp output
2.7 V ≤ VDD < 5.5 V
tKSO2
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Notes 2, 5
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
2/fMCK +
ns
120
2/fMCK +
ns
214
2/fMCK +
ns
573
(Note, Caution and Remark are listed on the next page.)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 50 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
Caution
2. ELECTRICAL SPECIFICATIONS (TARGET)
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
CSI mode connection diagram (during communication at different potential)
<Slave>
Vb
Rb
SCKp
RL78/L12
SCK
SIp
SO
SOp
SI
User's device
Notes 1. Transfer rate in the SNOOZE mode : MAX. 1 Mbps
2. Use it with EVDD ≥ Vb.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
5. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (VDD
tolerance) mode for the SOp pin by using port input mode register g (PIMg) and port output mode
register g (POMg).
Remarks 1. Rb[Ω]:Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load
capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),
g: PIM and POM number (g = 1)
3.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00, 01))
4. VIH and VIL below are observation points for the AC characteristics of the serial array unit when
communicating at different potentials in CSI mode.
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V: VIH = 2.2 V, VIL = 0.8 V
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V: VIH = 2.0 V, VIL = 0.5 V
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V: VIH = 1.50 V, VIL = 0.32 V
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 51 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
Caution
2. ELECTRICAL SPECIFICATIONS (TARGET)
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY2
tKL2
tKH2
SCKp
tSIK2
SIp
tKSI2
Input data
tKSO2
Output data
SOp
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY2
tKL2
tKH2
SCKp
tSIK2
SIp
tKSI2
Input data
tKSO2
SOp
Output data
Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (VDD
tolerance) mode for the SOp pin by using port input mode register g (PIMg) and port output mode
register g (POMg).
Remark
p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),
g: PIM and POM number (g = 1)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 52 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
2.5.2
Serial interface IICA
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Standard
Conditions
Fast Mode
Fast Mode
MIN.
SCLA0 clock frequency
fSCL
Fast mode plus:
MAX.
Unit
Plus
Mode
MIN.
MAX.
MIN.
MAX.
0
1000
2.7 V ≤ EVDD ≤ 5.5 V
kHz
fCLK ≥ 10 MHz
Fast mode:
1.8 V ≤ EVDD ≤ 5.5 V
0
400
kHz
fCLK ≥ 3.5 MHz
Normal mode:
1.6 V ≤ EVDD ≤ 5.5 V
0
100
kHz
fCLK ≥ 1 MHz
tSU:STA
4.7
0.6
0.26
μs
Hold time
tHD:STA
4.0
0.6
0.26
μs
Hold time when SCLA0 = “L”
tLOW
4.7
1.3
0.5
μs
Hold time when SCLA0 = “H”
tHIGH
4.0
0.6
0.26
μs
tSU:DAT
250
100
50
ns
Data hold time (transmission)
tHD:DAT
0
0
μs
Setup time of stop condition
tSU:STO
4.0
0.6
0.26
μs
Bus-free time
tBUF
4.7
1.3
0.5
μs
Setup time of restart condition
Note 1
Data setup time (reception)
Note 2
Notes 1.
2.
Remark
3.45
0
0.9
The first clock pulse is generated after this period when the start/restart condition is detected.
The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
The maximum value of Cb (communication line capacitance) and the value of Rb (communication line
pull-up resistor) at that time in each mode are as follows.
Standard mode: Cb = 400 pF, Rb = 2.7 kΩ
Fast mode:
Cb = 320 pF, Rb = 1.1 kΩ
Fast mode plus: Cb = 120 pF, Rb = 1.1 kΩ
IICA serial transfer timing
tLOW
SCL0
tHD:DAT
tHD:STA
tHIGH
tSU:STA
tHD:STA
tSU:STO
tSU:DAT
SDA0
tLOW
Stop
condition
Start
condition
R01DS0157EJ0001 Rev.0.01
2012.02.20
Restart
condition
Stop
condition
Page 53 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
2.5.3
On-chip debug (UART)
(TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
Transfer rate
2.6
2.6.1
MIN.
TYP.
115.2 k
MAX.
Unit
1M
bps
Analog Characteristics
A/D converter characteristics
(1) When AVREF (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), AVREF (−) = AVREFM/ANI1 (ADREFM = 1), target
ANI pin : ANI16 to ANI23 (supply ANI pin to EVDD)
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V, Reference voltage (+) = AVREFP, Reference
voltage (−) = AVREFM)
Parameter
Symbol
Resolution
Conditions
RES
Notes 1, 2
Overall error
tCONV
Notes 1, 2
Zero-scale error
Full-scale error
EZS
Notes 1, 2
Integral linearity error
EFS
Note 1
Differential linearity error
ILE
Note 1
TYP.
8
AINL
Conversion time
MIN.
DLE
Reference voltage (+)
AVREFP
Analog input voltage
VAIN
MAX.
Unit
10
bit
10-bit resolution
1.8 V ≤ VDD ≤ 5.5 V
1.2
±5.0
LSB
AVREFP = VDD
1.6 V ≤ VDD ≤ 5.5 V
1.2
±8.5
LSB
10-bit resolution
3.6 V ≤ VDD ≤ 5.5 V
2.125
39
μs
AVREFP = VDD
2.7 V ≤ VDD ≤ 5.5 V
3.1875
39
μs
1.8 V ≤ VDD ≤ 5.5 V
17
39
μs
1.6 V ≤ VDD ≤ 5.5 V
57
95
μs
1.8 V ≤ VDD ≤ 5.5 V
±0.35
%FSR
1.6 V ≤ VDD ≤ 5.5 V
±0.60
%FSR
1.8 V ≤ VDD ≤ 5.5 V
±0.35
%FSR
1.6 V ≤ VDD ≤ 5.5 V
±0.60
%FSR
10-bit resolution
1.8 V ≤ VDD ≤ 5.5 V
±3.5
LSB
AVREFP = VDD
1.6 V ≤ VDD ≤ 5.5 V
±6.0
LSB
10-bit resolution
1.8 V ≤ VDD ≤ 5.5 V
±2.0
LSB
AVREFP = VDD
1.6 V ≤ VDD ≤ 5.5 V
±2.5
LSB
VDD
V
AVREFP
V
10-bit resolution
AVREFP = VDD
10-bit resolution
AVREFP = VDD
1.6
0
and EVDD
VBGR
Note3
2.4 V ≤ VDD ≤ 5.5 V
1.38
1.45
1.5
V
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. HS (high-speed main) mode only
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 54 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
(2) When AVREF (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), AVREF (−) = VSS (ADREFM = 0), target ANI pin : ANI0,
ANI1, ANI16 to ANI23
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V, Reference voltage (+) = VDD, Reference
voltage (−) = VSS)
Parameter
Symbol
Resolution
Conditions
RES
Notes 1, 2
Overall error
tCONV
Notes 1, 2
Zero-scale error
Full-scale error
EZS
Notes 1, 2
Integral linearity error
EFS
Note 1
Differential linearity error
ILE
Note 1
Analog input voltage
10-bit resolution
10-bit resolution
10-bit resolution
10-bit resolution
10-bit resolution
DLE
VAIN
VBGR
TYP.
8
AINL
Conversion time
MIN.
Note3
10-bit resolution
MAX.
Unit
10
bit
1.8 V ≤ VDD ≤ 5.5 V
1.2
±7.0
LSB
1.6 V ≤ VDD ≤ 5.5 V
1.2
±10.5
LSB
3.6 V ≤ VDD ≤ 5.5 V
2.125
39
μs
2.7 V ≤ VDD ≤ 5.5 V
3.1875
39
μs
1.8 V ≤ VDD ≤ 5.5 V
17
39
μs
1.6 V ≤ VDD ≤ 5.5 V
57
95
μs
1.8 V ≤ VDD ≤ 5.5 V
±0.60
%FSR
1.6 V ≤ VDD ≤ 5.5 V
±0.85
%FSR
1.8 V ≤ VDD ≤ 5.5 V
±0.60
%FSR
1.6 V ≤ VDD ≤ 5.5 V
±0.85
%FSR
1.8 V ≤ VDD ≤ 5.5 V
±4.0
LSB
1.6 V ≤ VDD ≤ 5.5 V
±6.5
LSB
1.8 V ≤ VDD ≤ 5.5 V
±2.0
LSB
1.6 V ≤ VDD ≤ 5.5 V
±2.5
LSB
ANI0, ANI1
0
VDD
V
ANI16 to ANI23
0
EVDD
V
1.5
V
2.4 V ≤ VDD ≤ 5.5 V
1.38
1.45
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. HS (high-speed main) mode only
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 55 of 73
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
(3) When AVREF
(+)
= Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), AVREF
(−)
= AVREFM/ANI1
(ADREFM = 1), target ANI pin : ANI0, ANI16 to ANI23
(TA = −40 to +85°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V, Reference voltage (+) = VBGR, Reference
voltage (−) = AVREFM = 0 V) (HS (high-speed main) mode only)
Parameter
Symbol
Resolution
Conditions
MIN.
RES
Conversion time
Notes 1, 2
Zero-scale error
Integral linearity error
Note 1
Differential linearity error
Note 1
2.4 V ≤ VDD ≤ 5.5 V
±0.60
%FSR
8-bit resolution
2.4 V ≤ VDD ≤ 5.5 V
±2.0
LSB
8-bit resolution
2.4 V ≤ VDD ≤ 5.5 V
±1.0
LSB
1.5
V
EZS
8-bit resolution
ILE
DLE
AVREFM
Analog input voltage
VAIN
bit
μs
2.4 V ≤ VDD ≤ 5.5 V
Reference voltage (−)
Unit
39
8-bit resolution
VBGR
MAX.
8
tCONV
Reference voltage (+)
TYP.
17
1.38
1.45
VSS
0
V
VBGR
V
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 56 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
Caution
2. ELECTRICAL SPECIFICATIONS (TARGET)
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
2.6.2
Temperature sensor characteristics
(TA = −40 to +85°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) (HS (high-speed main) mode only)
Parameter
Symbol
Conditions
Temperature sensor output voltage VTMPS25
Setting ADS register = 80H, TA = +25°C
Reference output voltage
VCONST
Setting ADS register = 81H
Temperature coefficient
FVTMPS
Temperature sensor that depends on the
MIN.
TYP.
MAX.
1.05
1.38
1.45
Unit
V
1.5
−3.6
V
mV/C
temperature
Operation stabilization wait time
2.6.3
tAMP
5
μs
POR circuit characteristics
(TA = −40 to +85°C, VSS = 0 V)
Parameter
Detection voltage
Minimum pulse width
Detection delay time
R01DS0157EJ0001 Rev.0.01
2012.02.20
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
VPOR
Power supply rise time
1.48
1.51
1.54
V
VPDR
Power supply fall time
1.47
1.50
1.53
V
TPW
μs
300
350
μs
Page 57 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
2.6.4
LVD circuit characteristics
(TA = −40 to +85°C, VPDR ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Detection
Supply voltage level
Symbol
VLVI0
voltage
VLVI1
VLVI2
VLVI3
VLVI4
VLVI5
VLVI6
VLVI7
VLVI8
VLVI9
VLVI10
VLVI11
VLVI12
VLVI13
Minimum pulse width
tLW
Detection delay time
tLD
Remark
Conditions
MIN.
TYP.
MAX.
Unit
Power supply rise time
3.98
4.06
4.14
V
Power supply fall time
3.90
3.98
4.06
V
Power supply rise time
3.68
3.75
3.82
V
Power supply fall time
3.60
3.67
3.74
V
Power supply rise time
3.07
3.13
3.19
V
Power supply fall time
3.00
3.06
3.12
V
Power supply rise time
2.96
3.02
3.08
V
Power supply fall time
2.90
2.96
3.02
V
Power supply rise time
2.86
2.92
2.97
V
Power supply fall time
2.80
2.86
2.91
V
Power supply rise time
2.76
2.81
2.87
V
Power supply fall time
2.70
2.75
2.81
V
Power supply rise time
2.66
2.71
2.76
V
Power supply fall time
2.60
2.65
2.70
V
Power supply rise time
2.56
2.61
2.66
V
Power supply fall time
2.50
2.55
2.60
V
Power supply rise time
2.45
2.50
2.55
V
Power supply fall time
2.40
2.45
2.50
V
Power supply rise time
2.05
2.09
2.13
V
Power supply fall time
2.00
2.04
2.08
V
Power supply rise time
1.94
1.98
2.02
V
Power supply fall time
1.90
1.94
1.98
V
Power supply rise time
1.84
1.88
1.91
V
Power supply fall time
1.80
1.84
1.87
V
Power supply rise time
1.74
1.77
1.81
V
Power supply fall time
1.70
1.73
1.77
V
Power supply rise time
1.64
1.67
1.70
V
Power supply fall time
1.60
1.63
1.66
V
μs
300
300
μs
VLVI(n − 1) > VLVIn: n = 1 to 13
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 58 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
Caution
2. ELECTRICAL SPECIFICATIONS (TARGET)
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
LVD Detection Voltage of Interrupt & Reset Mode
(TA = −40 to +85°C, VPDR ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Interrupt and reset VLVI13
mode
VLVI12
VLVI11
VLVI4
VLVI11
VLVI10
VLVI9
VLVI2
VLVI8
VLVI7
VLVI6
VLVI1
VLVI5
VLVI4
VLVI3
VLVI0
R01DS0157EJ0001 Rev.0.01
2012.02.20
Conditions
VPOC0, VPOC1, VPOC2 = 0, 0, 0, falling reset voltage: 1.6 V
LVIS0, LVIS1 = 1, 0 Rising release reset voltage
(+0.1 V)
Falling interrupt voltage
MIN.
TYP.
MAX.
Unit
1.60
1.63
1.66
V
1.74
1.77
1.81
V
1.70
1.73
1.77
V
LVIS0, LVIS1 = 0, 1 Rising release reset voltage
1.84
1.88
1.91
V
(+0.2 V)
1.80
1.84
1.87
V
LVIS0, LVIS1 = 0, 0 Rising release reset voltage
2.86
2.92
2.97
V
(+1.2 V)
2.80
2.86
2.91
V
1.80
1.84
1.87
V
LVIS0, LVIS1 = 1, 0 Rising release reset voltage
1.94
1.98
2.02
V
(+0.1 V)
1.90
1.94
1.98
V
Falling interrupt voltage
Falling interrupt voltage
VPOC0, VPOC1, VPOC2 = 0, 0, 1, falling reset voltage: 1.8 V
Falling interrupt voltage
LVIS0, LVIS1 = 0, 1 Rising release reset voltage
(+0.2 V)
Falling interrupt voltage
2.05
2.09
2.13
V
2.00
2.04
2.08
V
LVIS0, LVIS1 = 0, 0 Rising release reset voltage
3.07
3.13
3.19
V
(+1.2 V)
3.00
3.06
3.12
V
2.40
2.45
2.50
V
LVIS0, LVIS1 = 1, 0 Rising release reset voltage
2.56
2.61
2.66
V
(+0.1 V)
2.50
2.55
2.60
V
LVIS0, LVIS1 = 0, 1 Rising release reset voltage
2.66
2.71
2.76
V
(+0.2 V)
2.60
2.65
2.70
V
Falling interrupt voltage
VPOC0, VPOC1, VPOC2 = 0, 1, 0, falling reset voltage: 2.4 V
Falling interrupt voltage
Falling interrupt voltage
LVIS0, LVIS1 = 0, 0 Rising release reset voltage
(+1.2 V)
Falling interrupt voltage
VPOC0, VPOC1, VPOC2 = 0, 1, 1, falling reset voltage: 2.7 V
3.68
3.75
3.82
V
3.60
3.67
3.74
V
2.70
2.75
2.81
V
LVIS0, LVIS1 = 1, 0 Rising release reset voltage
(+0.1 V)
Falling interrupt voltage
2.86
2.92
2.97
V
2.80
2.86
2.91
V
LVIS0, LVIS1 = 0, 1 Rising release reset voltage
2.96
3.02
3.08
V
(+0.2 V)
2.90
2.96
3.02
V
LVIS0, LVIS1 = 0, 0 Rising release reset voltage
3.98
4.06
4.14
V
(+1.2 V)
3.90
3.98
4.06
V
Falling interrupt voltage
Falling interrupt voltage
Page 59 of 73
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
RL78/L12
Caution
2. ELECTRICAL SPECIFICATIONS (TARGET)
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
2.6.5
Supply voltage rise time
(TA = −40 to +85°C, VSS = 0 V)
Parameter
Symbol
Maximum time to rise to
tPUP1
Conditions
MIN.
When RESET input is not used
TYP.
MAX.
Unit
3.2
ms
Note
1.6 V (VDD (MIN.))
(VDD: 0 V → 1.6 V)
Note
Make sure to raise the power supply in a shorter time than this.
Supply Voltage Rise Time Timing
• When RESET pin input is not used
Supply voltage
(VDD)
1.6 V
0V
Time
POR internal
signal
tPUP1
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 60 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
Caution
2. ELECTRICAL SPECIFICATIONS (TARGET)
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
2.7
2.7.1
LCD Characteristics
Resistance division method
(1) Static display mode
(TA = −40 to +85°C, VL4 (MIN.) ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
LCD drive voltage
Symbol
Conditions
VL4
MIN.
TYP.
2.0
MAX.
Unit
VDD
V
LCD output resistor
(Common)
Note
RODC
IO = ±5 μA
40
kΩ
LCD output resistor
(Segment)
Note
ROCS
IO = ±1 μA
200
kΩ
MAX.
Unit
VDD
V
(2) 1/2 bias method, 1/4 bias method
(TA = −40 to +85°C, VL4 (MIN.) ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
LCD drive voltage
Symbol
Conditions
VL4
MIN.
TYP.
2.7
LCD output resistor
(Common)
Note
RODC
IO = ±5 μA
40
kΩ
LCD output resistor
(Segment)
Note
ROCS
IO = ±1 μA
200
kΩ
MAX.
Unit
(3) 1/3 bias method
(TA = −40 to +85°C, VL4 (MIN.) ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
LCD drive voltage
Symbol
Conditions
VL4
MIN.
2.5
TYP.
VDD
Note2
V
LCD output resistor
(Common)
Note1
RODC
IO = ±5 μA
40
kΩ
LCD output resistor
(Segment)
Note1
ROCS
IO = ±1 μA
200
kΩ
Notes 1. The output resistor is a resistor connected between one of the VL1, VL2, VL3, VL4 and VSS pins, and either
of the SEG and COM pins.
2. 5.5 V (MAX) when driving a memory-type liquid crystal (the MLCDEN bit of the MLCD register = 1).
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 61 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
2.7.2
Internal voltage boosting method
(1) 1/3 bias method
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
LCD output voltage variation range
VL1
Conditions
Note 1
C1 to C4
Note 2
= 0.47 μF
Doubler output voltage
VL2
C1 to C4
Note 1
Tripler output voltage
VL3
C1 to C4
Note 1
C1 to C4
Note 1
Reference voltage setup time
Voltage boost wait time
Note 2
Note 3
Note 4
LCD output resistor
Note 4
(Common)
(Segment)
TYP.
MAX.
Unit
VLCD = 02H
T.B.D.
0.90
T.B.D.
V
VLCD = 03H
T.B.D.
0.95
T.B.D.
V
VLCD = 04H
T.B.D.
1.00
T.B.D.
V
VLCD = 05H
T.B.D.
1.05
T.B.D.
V
VLCD = 06H
T.B.D.
1.10
T.B.D.
V
VLCD = 07H
T.B.D.
1.15
T.B.D.
V
VLCD = 08H
T.B.D.
1.20
T.B.D.
V
VLCD = 09H
T.B.D.
1.25
T.B.D.
V
VLCD = 0AH
T.B.D.
1.30
T.B.D.
V
VLCD = 0BH
T.B.D.
1.35
T.B.D.
V
VLCD = 0CH
T.B.D.
1.40
T.B.D.
V
VLCD = 0DH
T.B.D.
1.45
T.B.D.
V
VLCD = 0EH
T.B.D.
1.50
T.B.D.
V
VLCD = 0FH
T.B.D.
1.55
T.B.D.
V
VLCD = 10H
T.B.D.
1.60
T.B.D.
V
VLCD = 11H
T.B.D.
1.65
T.B.D.
V
VLCD = 12H
T.B.D.
1.70
T.B.D.
V
VLCD = 13H
T.B.D.
1.75
T.B.D.
V
= 0.47 μF
2 VL1
−0.1
2 VL1
2 VL1
V
= 0.47 μF
3 VL1
−0.15
3 VL1
3 VL1
V
tVWAIT1
tVWAIT2
5
VDD > VL4
LCD output resistor
MIN.
= 0.47 μF
ms
500
ms
T.B.D.
ms
RODC
IO = ±5 μA
40
kΩ
ROCS
IO = ±1 μA
200
kΩ
Notes 1.
This is a capacitor that is connected between voltage pins used to drive the LCD.
C1: A capacitor connected between CAPH and CAPL
C2: A capacitor connected between VL1 and GND
C3: A capacitor connected between VL2 and GND
C4: A capacitor connected between VL3 and GND
C1 = C2 = C3 = C4 = 0.47 pF±30 %
2. This is the time required to wait from when the reference voltage is specified by using the VLCD register
(or when the internal voltage boosting method is selected [by setting the MDSET1 and MDSET0 bits of
the LCDM0 register to 01B] if the default value reference voltage is used) until voltage boosting starts
(VLCON = 1).
3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON
= 1).
4. The output resistor is a resistor connected between one of the VL1, VL2, VL3, VL4 and VSS pins, and either
of the SEG and COM pins.
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 62 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
Caution
2. ELECTRICAL SPECIFICATIONS (TARGET)
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
(2) 1/4 bias method
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
LCD output voltage variation range
VL1
Conditions
Note 1
C1 to C5
Note 2
= 0.47 μF
MIN.
TYP.
MAX.
Unit
VLCD = 02H
T.B.D.
0.90
T.B.D.
V
VLCD = 03H
T.B.D.
0.95
T.B.D.
V
VLCD = 04H
T.B.D.
1.00
T.B.D.
V
VLCD = 05H
T.B.D.
1.05
T.B.D.
V
VLCD = 06H
T.B.D.
1.10
T.B.D.
V
VLCD = 07H
T.B.D.
1.15
T.B.D.
V
VLCD = 08H
T.B.D.
1.20
T.B.D.
V
VLCD = 09H
T.B.D.
1.25
T.B.D.
V
VLCD = 0AH
T.B.D.
1.30
T.B.D.
V
VLCD = 0BH
T.B.D.
1.35
T.B.D.
V
VLCD = 0CH
T.B.D.
1.40
T.B.D.
V
VLCD = 0DH
T.B.D.
1.45
T.B.D.
V
VLCD = 0EH
T.B.D.
1.50
T.B.D.
V
VLCD = 0FH
T.B.D.
1.55
T.B.D.
V
VLCD = 10H
T.B.D.
1.60
T.B.D.
V
VLCD = 11H
T.B.D.
1.65
T.B.D.
V
VLCD = 12H
T.B.D.
1.70
T.B.D.
V
VLCD = 13H
Doubler output voltage
VL2
Tripler output voltage
VL3
Quadruply output voltage
Reference voltage setup time
Voltage boost wait time
VL4
Note 2
Note 3
T.B.D.
1.75
T.B.D.
V
C1 to C5
Note 1
= 0.47 μF
2 VL1−0.08
2 VL1
2 VL1
V
C1 to C5
Note 1
= 0.47 μF
3 VL1−0.12
3 VL1
3 VL1
V
C1 to C5
Note 1
= 0.47 μF
4 VL1−0.16
4 VL1
4 VL1
tVWAIT1
tVWAIT2
C1 to C5
Note 1
VDD > VL4
= 0.47 μF
V
5
ms
500
ms
T.B.D.
ms
LCD output resistor
Note 4
(Common)
RODC
IO = ±5 μA
40
kΩ
LCD output resistor
Note 4
(Segment)
ROCS
IO = ±1 μA
200
kΩ
Notes 1.
This is a capacitor that is connected between voltage pins used to drive the LCD.
C1: A capacitor connected between CAPH and CAPL
C2: A capacitor connected between VL1 and GND
C3: A capacitor connected between VL2 and GND
C4: A capacitor connected between VL3 and GND
C5: A capacitor connected between VL4 and GND
C1 = C2 = C3 = C4 = C5 = 0.47 pF±30 %
2. This is the time required to wait from when the reference voltage is specified by using the VLCD register
(or when the internal voltage boosting method is selected [by setting the MDSET1 and MDSET0 bits of
the LCDM0 register to 01B] if the default value reference voltage is used) until voltage boosting starts
(VLCON = 1).
3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON
= 1).
4. The output resistor is a resistor connected between one of the VL1, VL2, VL3, VL4 and VSS pins, and either
of the SEG and COM pins.
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 63 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
2.7.3
Capacitor split method
(1) 1/3 bias method
(TA = −40 to +85°C, 2.2 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
VL4
C1 to C4 = 0.47 μ F
VL2 voltage
VL2
C1 to C4 = 0.47 μ F
2/3 VL4
−0.1
2/3 VL4
2/3 VL4
+0.1
V
VL1 voltage
VL1
C1 to C4 = 0.47 μ F
1/3 VL4
−0.1
1/3 VL4
1/3 VL4
+0.1
V
VL4 voltage
Capacitor split wait time
Note 1
Note 3
Note 3
Note 3
tVWAIT
VDD
V
100
ms
LCD output resistor
(Common)
Note 2
RODC
IO = ±5 μA
40
kΩ
LCD output resistor
(Segment)
Note 2
ROCS
IO = ±1 μA
200
kΩ
Notes 1.
This is the wait time from when voltage bucking is started (VLCON = 1) until display is enabled (LCDON
= 1).
2. The output resistor is a resistor connected between one of the VL1, VL2, VL3, VL4 and VSS pins, and either
of the SEG and COM pins.
3.
This is a capacitor that is connected between voltage pins used to drive the LCD.
C1: A capacitor connected between CAPH and CAPL
C2: A capacitor connected between VL1 and GND
C3: A capacitor connected between VL2 and GND
C4: A capacitor connected between VL4 and GND
C1 = C2 = C3 = C4 = 0.47 pF±30 %
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 64 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
Caution
2. ELECTRICAL SPECIFICATIONS (TARGET)
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
2.8
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics
(TA = −40 to +85°C)
Parameter
Data retention supply voltage
Symbol
Conditions
MIN.
VDDDR
1.47
TYP.
Note
MAX.
Unit
5.5
V
Note The value depends on the POR detection voltage. When the voltage drops, the data is retained before a
POR reset is effected, but data is not retained when a POR reset is effected.
Operation mode
STOP mode
Data retention mode
VDD
VDDDR
STOP instruction execution
Standby release signal
(interrupt request)
2.9
Flash Memory Programming Characteristics
(TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
CPU/peripheral hardware clock
Symbol
Conditions
MIN.
fCLK
1.8 V ≤ VDD ≤ 5.5 V
Cerwr
1 erase + 1 write after Retained for 20 years
TYP.
1
MAX.
Unit
24
MHz
frequency
Number of code flash rewrites
1,000
Times
the erase is regarded (Self/serial
Number of data flash rewrites
Note
as 1 rewrite.
programming)
The retaining years
Retained for 1 years
are until next rewrite
(Self/serial
after the rewrite.
programming)
1,000,000
Note
Retained for 5 years
100,000
(Self/serial
programming)
Note
Note When using flash memory programmer and Renesas Electronics self programming library
Remark
When updating data multiple times, use the flash memory as one for updating data.
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 65 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
Caution
2. ELECTRICAL SPECIFICATIONS (TARGET)
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
2.10
Timing Specs for Switching Modes
Parameter
Symbol
How long from when a pin reset
tSUINIT
Conditions
MIN.
TYP.
POR and LVD reset must end before the pin
MAX.
Unit
100
ms
reset ends.
ends until the initial communication
settings are specified
How long from when the TOOL0
tSU
POR and LVD reset must end before the pin
10
μs
1
ms
reset ends.
pin is placed at the low level until a
pin reset ends
How long the TOOL0 pin must be
kept at the low level after a reset
tHD
POR and LVD reset must end before the pin
reset ends.
ends
<1>
<2>
<3>
<4>
RESET
tHD+
software
processing
time
TOOL0
tSU
tSUINIT
<1>
The low level is input to the TOOL0 pin.
<2>
The pins reset ends (POR and LVD reset must end before the pin reset ends.).
<3>
The TOOL0 pin is set to the high level.
<4>
Setting of the flash memory programming mode by UART reception and complete
the baud rate setting.
Remark tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within
100 ms from when the external and internal resets end.
tSU:
How long from when the TOOL0 pin is placed at the low level until a pin reset ends
tHD:
How long to keep the TOOL0 pin at the low level from when the external and internal resets end
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 66 of 73
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
RL78/L12
3.
3. PACKAGE DRAWINGS
PACKAGE
3.1
DRAWINGS
32-pin products
R5F10RB8AFP, R5F10RBAAFP, R5F10RBCAFP
32-PIN PLASTIC LQFP(7x7)
HD
2
D
17
16
24
25
detail of lead end
1
E
c
HE
θ
32
8
1
L
9
e
(UNIT:mm)
3
b
x
M
A
A2
ITEM
D
DIMENSIONS
7.00±0.10
E
7.00±0.10
HD
9.00±0.20
HE
9.00±0.20
A
1.70 MAX.
A1
0.10±0.10
A2
y
NOTE
1.Dimensions “ 1” and “ 2” do not include mold flash.
2.Dimension “ 3” does not include trim offset.
A1
1.40
b
0.37±0.05
c
0.145 ±0.055
L
0.50±0.20
θ
0° to 8°
e
0.80
x
0.20
y
0.10
P32GA-80-GBT
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 67 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
3.2
3. PACKAGE DRAWINGS
44-pin products
R5F10RF8AFP, R5F10RFAAFP, R5F10RFCAFP
44-PIN PLASTIC LQFP(10x10)
HD
D
detail of lead end
A3
23
22
33
34
c
θ
E
L
Lp
HE
L1
12
11
44
1
(UNIT:mm)
ZE
e
ZD
b
x
M
S
A
A2
ITEM
D
DIMENSIONS
10.00±0.20
E
10.00±0.20
HD
12.00±0.20
HE
12.00±0.20
A
1.60 MAX.
A1
0.10±0.05
A2
1.40±0.05
A3
S
y
S
NOTE
Each lead centerline is located within 0.20 mm of
its true position at maximum material condition.
A1
0.37 +0.08
−0.07
c
0.145 +0.055
−0.045
L
0.50
Lp
0.60±0.15
L1
θ
1.00±0.20
3° +5°
−3°
e
0.80
x
0.20
y
0.10
ZD
1.00
ZE
R01DS0157EJ0001 Rev.0.01
2012.02.20
0.25
b
1.00
P44GB-80-UES-1
Page 68 of 73
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
RL78/L12
3.3
3. PACKAGE DRAWINGS
48-pin products
R5F10RG8AFB, R5F10RGAAFB, R5F10RGCAFB
48-PIN PLASTIC LQFP (FINE PITCH)(7x7)
HD
D
detail of lead end
36
25
37
A3
24
c
θ
E
L
Lp
HE
L1
13
48
12
1
(UNIT:mm)
ZE
e
ZD
b
x
M
S
A
A2
ITEM
D
DIMENSIONS
7.00±0.20
E
7.00±0.20
HD
9.00±0.20
HE
9.00±0.20
A
1.60 MAX.
A1
0.10±0.05
A2
1.40±0.05
A3
b
S
c
L
y
S
NOTE
Each lead centerline is located within 0.08 mm of
its true position at maximum material condition.
A1
Lp
0.60±0.15
L1
θ
1.00±0.20
3° +5°
−3°
e
0.50
x
0.08
y
0.08
ZD
0.75
ZE
R01DS0157EJ0001 Rev.0.01
2012.02.20
0.25
0.22±0.05
0.145 +0.055
−0.045
0.50
0.75
P48GA-50-8EU
Page 69 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
3.4
3. PACKAGE DRAWINGS
52-pin products
R5F10RJ8AFA, R5F10RJAAFA, R5F10RJCAFA
52-PIN PLASTIC LQFP (10x10)
HD
D
2
27
39
40
detail of lead end
26
c
1
E
HE
θ
52
L
14
1
13
e
(UNIT:mm)
3
b
x
M
A
A2
y
NOTE
ITEM
D
DIMENSIONS
10.00±0.10
E
10.00±0.10
HD
12.00±0.20
HE
12.00±0.20
A
1.70 MAX.
A1
0.10±0.05
A2
A1
1.40
b
0.32±0.05
c
0.145 ±0.055
L
0.50±0.15
1.Dimensions “ 1” and “ 2” do not include mold flash.
θ
0° to 8°
2.Dimension “ 3” does not include trim offset.
e
0.65
x
0.13
y
0.10
P52GB-65-GBS
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 70 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
3.5
3. PACKAGE DRAWINGS
64-pin products
R5F10RLAAFA, R5F10RLCAFA
64-PIN PLASTIC LQFP(12x12)
HD
D
detail of lead end
48
33
49
32
A3
c
θ
E
L
Lp
HE
L1
(UNIT:mm)
17
64
1
16
ZE
e
ZD
b
x
M
S
A
A2
S
y
S
NOTE
Each lead centerline is located within 0.13 mm of
its true position at maximum material condition.
R01DS0157EJ0001 Rev.0.01
2012.02.20
A1
ITEM
D
DIMENSIONS
12.00±0.20
E
12.00±0.20
HD
14.00±0.20
HE
14.00±0.20
A
1.60 MAX.
A1
0.10±0.05
A2
1.40±0.05
A3
0.25
b
0.32 +0.08
−0.07
c
0.145 +0.055
−0.045
L
0.50
Lp
0.60±0.15
L1
θ
1.00±0.20
3° +5°
−3°
e
0.65
x
0.13
y
0.10
ZD
ZE
1.125
1.125
P64GK-65-UET-1
Page 71 of 73
Preliminary document
Specifications in this document are tentative and subject to change.
Under development
RL78/L12
3. PACKAGE DRAWINGS
R5F10RLAAFB, R5F10RLCAFB
64-PIN PLASTIC LQFP(FINE PITCH)(10x10)
HD
D
detail of lead end
48
33
49
A3
32
c
θ
E
L
Lp
HE
L1
(UNIT:mm)
17
64
1
16
ZE
e
ZD
b
x
M
S
A
ITEM
D
DIMENSIONS
10.00±0.20
E
10.00±0.20
HD
12.00±0.20
HE
12.00±0.20
A
1.60 MAX.
A1
0.10±0.05
A2
1.40±0.05
A3
b
A2
c
S
y
S
NOTE
Each lead centerline is located within 0.08 mm of
its true position at maximum material condition.
R01DS0157EJ0001 Rev.0.01
2012.02.20
A1
L
0.25
0.22±0.05
0.145 +0.055
−0.045
0.50
Lp
0.60±0.15
L1
θ
1.00±0.20
3° +5°
−3°
e
0.50
x
0.08
y
0.08
ZD
1.25
ZE
1.25
P64GB-50-UEU-1
Page 72 of 73
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/L12
3. PACKAGE DRAWINGS
R5F10RLAANB, R5F10RLCANB
64-PIN PLASTIC WQFN(8x8)
D
DETAIL OF A
PART
E
S
A
A
S
y
S
D2
A
(UNIT:mm)
EXPOSED DIE PAD
1
ITEM
16
64
17
B
D
8.00 ± 0.05
E
8.00 ± 0.05
A
0.75 ± 0.05
b
0.20 ± 0.05
e
0.40
Lp
E2
32
49
33
48
Lp
e
b
x
R01DS0157EJ0001 Rev.0.01
2012.02.20
M
ITEM
EXPOSED
DIE PAD
VARIATIONS
DIMENSIONS
0.40 ± 0.10
x
0.05
y
0.05
P64K8-40-9B5
D2
E2
MIN NOM MAX MIN NOM MAX
A 6.45 6.50 6.55 6.45 6.50 6.55
S AB
Page 73 of 73
Revision History
Rev.
0.01
Date
Feb 20, 2012
RL78/L12 Data Sheet
Description
Summary
Page
-
First Edition issued
All trademarks and registered trademarks are the property of their respective owners.
C-1
NOTES FOR CMOS DEVICES
(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a
reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise
from entering the device when the input level is fixed, and also in the transition period when the input level
passes through the area between VIL (MAX) and VIH (MIN).
(2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If
an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc.,
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be
connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling
related to unused pins must be judged separately for each device and according to related specifications
governing the device.
(3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause
destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it when it has occurred.
Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended
to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work benches and floors should be grounded. The operator should be grounded using a wrist
strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken
for PW boards with mounted semiconductor devices.
(4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS
device. Immediately after the power source is turned ON, devices with reset functions have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A
device is not initialized until the reset signal is received. A reset operation must be executed immediately
after power-on for devices with reset functions.
(5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal
operation and external interface, as a rule, switch on the external power supply after switching on the internal
power supply. When switching the power supply off, as a rule, switch off the external power supply and then
the internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements
due to the passage of an abnormal current. The correct power on/off sequence must be judged separately
for each device and according to related specifications governing the device.
(6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply
while the device is not powered. The current injection that results from input of such a signal or I/O pull-up
power supply may cause malfunction and the abnormal current that passes in the device at this time may
cause degradation of internal elements. Input of signals during the power off state must be judged
separately for each device and according to related specifications governing the device.
Notice
1.
All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas
Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to
be disclosed by Renesas Electronics such as that disclosed through our website.
2.
Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or
technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
3.
You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
4.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
5.
When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and
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assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
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which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the
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The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc.
"Standard":
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools;
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"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically
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"Specific":
Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical
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You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
9.
Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or system manufactured by you.
10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics
products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes
no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.
11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1)
"Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2)
"Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
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Colophon 1.1