Preliminary Datasheet Specifications in this document are tentative and subject to change. RL78/G1A R01DS0151EJ0001 Rev.0.01 2011.12.26 RENESAS MCU Combines Multi-channel 12-Bit A/D Converter, True Low Power Platform (as low as 66 µA/MHz, and 0.57 µA for RTC + LVD), 1.6 V to 3.6 V operation, 16 to 64 Kbyte Flash, 41 DMIPS at 32 MHz 1. 1.1 OUTLINE Features Ultra-Low Power Technology • 1.6 V to 3.6 V operation from a single supply • Stop (RAM retained): 0.23 µA, (LVD enabled): 0.31 µA • Halt (RTC + LVD): 0.57 µA • Snooze: T.B.D. • Operating: 66 µA/MHz 16-bit RL78 CPU Core • Delivers 41 DMIPS at maximum operating frequency of 32 MHz • Instruction Execution: 86% of instructions can be executed in 1 to 2 clock cycles • CISC Architecture (Harvard) with 3-stage pipeline • Multiply Signed & Unsigned: 16 x 16 to 32-bit result in 1 clock cycle • MAC: 16 x 16 to 32-bit result in 2 clock cycles • 16-bit barrel shifter for shift & rotate in 1 clock cycle • 1-wire on-chip debug function Code Flash Memory • Density: 16 KB to 64 KB • Block size: 1 KB • On-chip single voltage flash memory with protection from block erase/writing • Self-programming with secure boot swap function and flash shield window function Data Flash Memory • Data Flash with background operation • Data flash size: 4 KB • Erase Cycles: 1 Million (typ.) • Erase/programming voltage: 1.8 V to 3.6 V RAM • 2 KB to 4 KB size options • Supports operands or instructions • Back-up retention in all modes High-speed On-chip Oscillator • 32 MHz with +/− 1% accuracy over voltage (1.8 V to 3.6 V) and temperature (−20 °C to +85 °C) • Pre-configured settings: 32 MHz, 24 MHz, 16 MHz, 12 MHz, 8 MHz, 4 MHz & 1 MHz Reset and Supply Management • Power-on reset (POR) monitor/generator • Low voltage detection (LVD) with 12 setting options (Interrupt and/or reset function) R01DS0151EJ0001 Rev.0.01 2011.12.26 Data Memory Access (DMA) Controller • Up to 2 fully programmable channels • Transfer unit: 8- or 16-bit Multiple Communication Interfaces • Up to 6 x I2C master 2 • Up to 1 x I C multi-master • Up to 6 x CSI/SPI (7-, 8-bit) • Up to 3 x UART (7-, 8-, 9-bit) • Up to 1 x LIN Extended-Function Timers • Multi-function 16-bit timers: Up to 8 channels • Real-time clock (RTC): 1 channel (full calendar and alarm function with watch correction function) • Interval Timer: 12-bit, 1 channel • 15 kHz watchdog timer: 1 channel (window function) Rich Analog • ADC: Up to 28 channels, 12-bit resolution, 3.375 µs conversion time • Supports 1.6 V • Internal voltage reference (1.45 V) • On-chip temperature sensor Safety Features (IEC or UL 60730 compliance) • Flash memory CRC calculation • RAM parity error check • RAM write protection • SFR write protection • Illegal memory access detection • Clock stop/ frequency detection • ADC self-test General Purpose I/O • 3.6 V tolerant, high-current (up to 20 mA per pin) • Open-Drain, Internal Pull-up support Operating Ambient Temperature • Standard: −40 °C to +85 °C Package Type and Pin Count From 3 mm x 3 mm to 10 mm x 10 mm QFP: 48, 64 QFN: 32, 48 LGA: 25 BGA: 64 Page 1 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 1. OUTLINE { ROM, RAM capacities Flash Data ROM flash 64 4 KB 4 KB RL78/G1A 25 pins 32 pins 48 pins 64 pins R5F10E8E R5F10EBE R5F10EGE R5F10ELE Note KB 48 RAM 4 KB 3 KB R5F10E8D R5F10EBD R5F10EGD R5F10ELD 4 KB 2 KB R5F10E8C R5F10EBC R5F10EGC R5F10ELC 4 KB 2 KB R5F10E8A R5F10EBA R5F10EGA − KB 32 KB 16 KB Note This is about 3 KB when the self-programming function and data flash function are used. R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 2 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 1.2 1. OUTLINE Ordering Information • Flash memory version (lead-free product) Pin count 25 pins Package 25-pin plastic FLGA (3 × 3) Data flash Mounted Part Number R5F10E8AALA, R5F10E8CALA, R5F10E8DALA, R5F10E8EALA 32 pins 32-pin plastic WQFN (fine pitch) Mounted (5 × 5) 48 pins 48-pin plastic LQFP (fine pitch) Mounted (7 × 7) 48-pin plastic WQFN (7 × 7) R5F10EBAANA, R5F10EBCANA, R5F10EBDANA, R5F10EBEANA R5F10EGAAFB, R5F10EGCAFB, R5F10EGDAFB, R5F10EGEAFB Mounted R5F10EGAANA, R5F10EGCANA, R5F10EGDANA, R5F10EGEANA 64 pins 64-pin plastic LQFP (fine pitch) Mounted R5F10ELCAFB, R5F10ELDAFB, R5F10ELEAFB Mounted R5F10ELCABG, R5F10ELDABG, R5F10ELEABG (10 × 10) 64-pin plastic FBGA (4 × 4) R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 3 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 1.3 1.3.1 1. OUTLINE Pin Configuration (Top View) 25-pin products • 25-pin plastic FLGA (3 × 3) Bottom View Top View 5 4 3 2 1 A B C D E E P40/TOOL0 B RESET 5 4 P122/X2/ EXCLK P137/INTP0 P121/X1 VDD 3 REGC VSS P60/SCLA0 P61/SDAA0 1 A C B B A D E P03/ANI16/ RxD1/TO00/ (KR1) P23/ANI3/ (KR3) AVSS P02/ANI17/ TxD1/TI00/ (KR0) P22/ANI2/ (KR2) AVDD P21/ANI1/ AVREFM P11/ANI20/ SI00/SDA00/ RxD0/ TOOLRxD P51/ANI25/ SO11/INTP2 P10/ANI18/ SCK00/SCL00 P12/ANI21/ SO00/TxD0/ TOOLTxD P20/ANI0/ AVREFP P30/ANI27/ SCK11/SCL11/ INTP3 2 C INDEX MARK INDEX MARK A D P31/ANI29/TI03/ TO03/PCLBUZ0 /INTP4 C D 5 4 P50/ANI26/ SI11/SDA11 INTP1 3 2 1 E Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 4 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 1.3.2 1. OUTLINE 32-pin products AVSS AVDD P10/ANI18/SCK00/SCL00/(KR0) P11/ANI20/SI00/SDA00/RxD0/TOOLRxD/(KR1) P12/ANI21/SO00/TxD0/TOOLTxD/(KR2) P13/ANI22/SO20/TxD2/(KR3) P14/ANI23/SI20/SDA20/RxD2/(KR4) P15/ANI24/SCK20/SCL20/PCLBUZ1/(KR5) • 32-pin plastic WQFN (fine pitch) (5 × 5) exposed die pad 24 23 22 21 20 19 18 17 25 16 26 15 27 14 28 13 29 12 30 11 31 10 32 9 1 2 3 4 5 6 7 8 P51/SO11/INTP2 P50/ANI26/SI11/SDA11/INTP1 P30/ANI27/SCK11/SCL11/INTP3 P70/ANI28/KR0 P31/ANI29/TI03/TO03/PCLBUZ0/INTP4 P62 P61/SDAA0 P60/SCLA0 P40/TOOL0 RESET P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD P24/ANI4/(KR5) P23/ANI3/(KR4) P22/ANI2/(KR3) P21/ANI1/AVREFM P20/ANI0/AVREFP P03/ANI16/RxD1/TO00/(KR2) P02/ANI17/TxD1/TI00/(KR1) P120/ANI19/(KR0) Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 5 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 1.3.3 1. OUTLINE 48-pin products P140/PCLBUZ0/INTP6 P02/ANI17/TxD1/TI00/(KR0) P03/ANI16/RxD1/TO00/(KR1) P130 P20/ANI0/AVREFP P21/ANI1/AVREFM P22/ANI2/(KR2) P23/ANI3/(KR3) P24/ANI4/(KR4) P25/ANI5/(KR5) P26/ANI6 P27/ANI7 • 48-pin plastic LQFP (fine pitch) (7 × 7) 36 35 34 33 32 31 30 29 28 27 26 25 24 37 23 38 22 39 21 40 20 41 19 42 18 43 17 44 16 45 15 46 14 47 13 48 1 2 3 4 5 6 7 8 9 10 11 12 AVSS AVDD P150/ANI8 P10/ANI18/SCK00/SCL00/(KR0) P11/ANI20/SI00/SDA00/RxD0/TOOLRxD/(KR1) P12/ANI21/SO00/TxD0/TOOLTxD/(KR2) P13/ANI22/SO20/TxD2/(KR3) P14/ANI23/SI20/SDA20/RxD2/(KR4) P15/ANI24/SCK20/SCL20/PCLBUZ1/(KR5) P16/TI01/TO01/INTP5 P51/ANI25/SO11/INTP2 P50/ANI26/SI11/SDA11/INTP1 P60/SCLA0 P61/SDAA0 P62 P63 P31/ANI29/TI03/TO03/INTP4 P75/SCK01/SCL01/INTP9/KR5 P74/SI01/SDA01/INTP8/KR4 P73/SO01/KR3 P72/SO21/KR2 P71/SI21/SDA21/KR1 P70/ANI28/SCK21/SCL21/KR0 P30/ANI27/SCK11/SCL11/INTP3/RTC1HZ P120/ANI19 P41/ANI30/TI07/TO07 P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 6 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 1. OUTLINE P140/PCLBUZ0/INTP6 P02/ANI17/TxD1/TI00/(KR0) P03/ANI16/RxD1/TO00/(KR1) P130 P20/ANI0/AVREFP P21/ANI1/AVREFM P22/ANI2/(KR2) P23/ANI3/(KR3) P24/ANI4/(KR4) P25/ANI5/(KR5) P26/ANI6 P27/ANI7 • 48-pin plastic WQFN (7 × 7) 36 35 34 33 32 31 30 29 28 27 26 25 24 37 23 38 22 39 21 40 20 41 19 42 18 43 17 44 16 45 15 46 14 47 13 48 1 2 3 4 5 6 7 8 9 10 11 12 AVSS AVDD P150/ANI8 P10/ANI18/SCK00/SCL00/(KR0) P11/ANI20/SI00/SDA00/RxD0/TOOLRxD/(KR1) P12/ANI21/SO00/TxD0/TOOLTxD/(KR2) P13/ANI22/SO20/TxD2/(KR3) P14/ANI23/SI20/SDA20/RxD2/(KR4) P15/ANI24/SCK20/SCL20/PCLBUZ1/(KR5) P16/TI01/TO01/INTP5 P51/ANI25/SO11/INTP2 P50/ANI26/SI11/SDA11/INTP1 P60/SCLA0 P61/SDAA0 P62 P63 P31/ANI29/TI03/TO03/INTP4 P75/SCK01/SCL01/INTP9/KR5 P74/SI01/SDA01/INTP8/KR4 P73/SO01/KR3 P72/SO21/KR2 P71/SI21/SDA21/KR1 P70/ANI28/SCK21/SCL21/KR0 P30/ANI27/SCK11/SCL11/INTP3/RTC1HZ P120/ANI19 P41/ANI30/TI07/TO07 P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 7 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 1.3.4 1. OUTLINE 64-pin products AVSS AVDD P150/ANI8 P151/ANI9/(KR6) P152/ANI10/(KR7) P153/ANI11/(KR8) P154/ANI12/(KR9) P10/ANI18/SCK00/SCL00/(KR0) P11/ANI20/SI00/SDA00/RxD0/TOOLRxD/(KR1) P12/ANI21/SO00/TxD0/TOOLTxD/(KR2) P13/ANI22/SO20/TxD2/(KR3) P14/ANI23/SI20/SDA20/RxD2/(KR4) P15/ANI24/SCK20/SCL20/(KR5) P16/TI01/TO01/INTP5 P51/ANI25/SO11/INTP2 P50/ANI26/SI11/SDA11/INTP1 • 64-pin plastic LQFP (fine pitch) (10 × 10) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P27/ANI7 P26/ANI6/(KR9) P25/ANI5/(KR8) P24/ANI4/(KR7) P23/ANI3/(KR6) P22/ANI2/(KR5) P21/ANI1/AVREFM P20/ANI0/AVREFP P130 P04/SCK10/SCL10/(KR4) P03/ANI16/SI10/SDA10/RxD1/(KR3) P02/ANI17/SO10/TxD1/(KR2) P01/TO00/(KR1) P00/TI00/(KR0) P141/PCLBUZ1/INTP7 P140/PCLBUZ0/INTP6 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 6 7 8 9 10 11 12 13 14 15 16 P120/ANI19 P43 P42/TI04/TO04 P41/ANI30/TI07/TO07 P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS EVSS0 VDD EVDD0 1 2 3 4 5 P30/ANI27/SCK11/SCL11/INTP3/RTC1HZ P05/TI05/TO05/KR8 P06/TI06/TO06/KR9 P70/ANI28/SCK21/SCL21/KR0 P71/SI21/SDA21/KR1 P72/SO21/KR2 P73/SO01/KR3 P74/SI01/SDA01/INTP8/KR4 P75/SCK01/SCL01/INTP9/KR5 P76/INTP10/KR6 P77/INTP11/KR7 P31/ANI29/TI03/TO03/INTP4 P63 P62 P61/SDAA0 P60/SCLA0 Cautions 1. Make EVSS0 pin the same potential as VSS pin. 2. Make VDD pin the potential that is higher than EVDD0 pin. 3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the VDD and EVDD0 pins and connect the VSS and EVSS0pins to separate ground lines. 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 8 of 76 Preliminary document Specifications in this document are tentative and subject to change. Under development RL78/G1A 1. OUTLINE • 64-pin plastic FBGA (4 × 4) Top View Bottom View 8 7 6 5 4 3 2 1 A B C D E F G H H G F E D C B A Index mark Pin No. Name Pin No. Name Pin No. Name Pin No. Name A1 P05/TI05/TO05/KR8 C1 P51/ANI25/SO11 /INTP2 E1 P153/ANI11/(KR8) G1 AVDD A2 P30/ANI27/SCK11 /SCL11/INTP3 /RTC1HZ C2 P71/SI21/SDA21/KR1 E2 P154/ANI12/(KR9) G2 P25/ANI5/(KR8) A3 P70/ANI28/SCK21 /SCL21/KR0 C3 P74/SI01/SDA01 /INTP8/KR4 E3 P10/ANI18/SCK00 /SCL00/(KR0) G3 P24/ANI4/(KR7) A4 P75/SCK01/SCL01 /INTP9/KR5 C4 P16/TI01/TO01/INTP5 E4 P11/ANI20/SI00 /SDA00/RxD0 /TOOLRxD/(KR1) G4 P22/ANI2/(KR5) A5 P77/INTP11/KR7 C5 P15/ANI24/SCK20 /SCL20/(KR5) E5 P03/ANI16/SI10 /SDA10/RxD1/(KR3) G5 P130 A6 P61/SDAA0 C6 P63 E6 P41/ANI30/TI07/TO07 G6 P02/ANI17/SO10/TxD1 /(KR2) A7 P60/SCLA0 C7 VSS E7 RESET G7 P00/TI00/(KR0) A8 EVDD0 C8 P121/X1 E8 P137/INTP0 G8 P124/XT2/EXCLKS B1 P50/ANI26 /SI11 /SDA11/INTP1 D1 P13/ANI22/SO20 /TxD2/(KR3) F1 P150/ANI8 H1 AVSS B2 P72/SO21/KR2 D2 P06/TI06/TO06/KR9 F2 P151/ANI9/(KR6) H2 P27/ANI7 B3 P73/SO01/KR3 D3 P12/ANI21/SO00 F3 /TxD0/TOOLTxD/(KR2) P152/ANI10/(KR7) H3 P26/ANI6/(KR9) B4 P76/INTP10/KR6 D4 P14/ANI23/SI20/ SDA20/RxD2/(KR4) F4 P21/ANI1/AVREFM H4 P23/ANI3/(KR6) B5 P31/ANI29/TI03/TO03 D5 /INTP4 P42/TI04/TO04 F5 P04/SCK10/SCL10 /(KR4) H5 P20/ANI0/AVREFP B6 P62 D6 P40/TOOL0 F6 P43 H6 P141/PCLBUZ1/INTP7 B7 VDD D7 REGC F7 P01/TO00/(KR1) H7 P140/PCLBUZ0/INTP6 B8 EVSS0 D8 P122/X2/EXCLK F8 P123/XT1 H8 P120/ANI19 Cautions 1. 2. 3. Remarks 1. 2. Make EVSS0 pin the same potential as VSS pin. Make VDD pin the potential that is higher than EVDD0 pin. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). For pin identification, see 1.4 Pin Identification. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the VDD and EVDD0 pins and connect the VSS and EVSS0 pins to separate ground lines. 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 9 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 1.4 1. OUTLINE Pin Identification ANI0 to ANI12, PCLBUZ0, PCLBUZ1: Programmable clock output/buzzer ANI16 to ANI30: Analog input AVDD: Analog power supply REGC: Regulator capacitance AVSS: Analog ground RESET: Reset AVREFM: A/D converter reference RTC1HZ: Real-time clock correction clock output potential (− side) input AVREFP: (1 Hz) output A/D converter reference RxD0 to RxD2: potential (+ side) input SCK00, SCK01, SCK10, EVDD0: Power supply for port SCK11, SCK20, SCK21: Serial clock input/output EVSS0: Ground for port SCLA0, SCL00, SCL01, EXCLK: External clock input (main SCL10, SCL11, SCL20, system clock) SCL21: External clock input (sub SDAA0, SDA00, SDA01, system clock) SDA10, SDA11, SDA20, EXCLKS: Receive data Serial clock input/output INTP0 to INTP11: External interrupt input SDA21: KR0 to KR9: Key return SI00, SI01, SI10, SI11, P00 to P06: Port 0 SI20, SI21: P10 to P16: Port 1 SO00, SO01, SO10, P20 to P27: Port 2 SO11, SO20, SO21: P30, P31: Port 3 TI00, TI01, TI03 to TI07: Timer input P40 to P43: Port 4 TO00, TO01, P50, P51: Port 5 TO03 to TO07: Timer output P60 to P63: Port 6 TOOL0: Data input/output for tool P70 to P77: Port 7 TOOLRxD, TOOLTxD: Data input/output for external device P120 to P124: Port 12 TxD0 to TxD2: Transmit data P130, P137: Port 13 VDD: Power supply P140, P141: Port 14 VSS: Ground P150 to P154: Port 15 X1, X2: Crystal oscillator (main system clock) XT1, XT2: Crystal oscillator (subsystem clock) R01DS0151EJ0001 Rev.0.01 2011.12.26 Serial data input/output Serial data input Serial data output Page 10 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 1.5 1. OUTLINE Block Diagram 1.5.1 25-pin products TI00/P02 TO00/P03 TIMER ARRAY UNIT (8ch) PORT 0 2 P02, P03 ch0 PORT 1 3 P10 to P12 PORT 2 4 P20 to P23 PORT 3 2 P30, P31 ch1 ch2 TI03/TO03/P31 KR0/P02 KR1/P03 KR2/P22 KR3/P23 KEY RETURN ch3 PORT 4 P40 ch4 ch5 ch6 INTERVAL TIMER ch7 PORT 5 2 P50, P51 PORT 6 2 P60, P61 PORT 12 2 P121, P122 PORT 13 WINDOW WATCHDOG TIMER LOW-SPEED ON-CHIP OSCILLATOR RL78 CPU CORE CODE FLASH MEMORY (KEY RETURN) P137 (KR0/P02, KR1/P03, KR2/P22, KR3/P23) (4) ANI0/P20 to ANI3/P23 4 DATA FLASH MEMORY ANI16/P03, ANI17/P02, ANI18/P10, ANI20/P11, ANI21/P12, ANI25/P51, ANI26/P50, ANI27/P30, ANI29/P31 9 A/D CONVERTER REAL-TIME CLOCK SERIAL ARRAY UNIT0 (4ch) RxD0/P11 TxD0/P12 UART0 RxD1/P03 TxD1/P02 UART1 SCK00/P10 SI00/P11 SO00/P12 CSI00 SCK11/P30 SI11/P50 SO11/P51 CSI11 SCL00/P10 SDA00/P11 IIC00 AVREFP/P20 AVREFM/P21 RAM POWER ON RESET/ VOLTAGE DETECTOR VDD AVDD VSS TOOLRxD/P11, AVSS TOOLTxD/P12 RESET CONTROL TOOL0/P40 ON-CHIP DEBUG SERIAL INTERFACE IICA0 SDAA0/P61 SCLA0/P60 IIC11 BCD ADJUSTMENT RESET X1/P121 ON-CHIP PCLBUZ0/P31 CLOCK OUTPUT CONTROL DIRECT MEMORY ACCESS CONTROL SYSTEM CONTROL HIGH-SPEED BUZZER OUTPUT SCL11/P30 SDA11/P50 POR/LVD CONTROL X2/EXCLK/P122 OSCILLATOR VOLTAGE REGULATOR REGC MULTIPLIER& DIVIDER, MULITIPLYACCUMULATOR INTP0/P137 INTP1/P50 INTERRUPT CONTROL INTP2/P51 2 Remark INTP3/P30, INTP4/P31 Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 11 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 1.5.2 1. OUTLINE 32-pin products TI00/P02 TO00/P03 TIMER ARRAY UNIT (8ch) PORT 0 2 P02, P03 ch0 PORT 1 6 P10 to P15 PORT 2 5 P20 to P24 PORT 3 2 P30, P31 ch1 ch2 TI03/TO03/P31 ch3 PORT 4 P40 ch4 PORT 5 2 P50, P51 ch6 PORT 6 3 P60 to P62 ch7 PORT 7 ch5 INTERVAL TIMER RxD2/P14 WINDOW WATCHDOG TIMER PORT 12 P70 P120 P121, P122 2 PORT 13 LOW-SPEED ON-CHIP OSCILLATOR CODE FLASH MEMORY RL78 CPU CORE REAL-TIME CLOCK UART0 RxD1/P03 TxD1/P02 UART1 A/D CONVERTER SCK00/P10 SI00/P11 SO00/P12 CSI00 POWER ON RESET/ VOLTAGE DETECTOR RAM CSI11 SCL00/P10 SDA00/P11 IIC00 SCL11/P30 SDA11/P50 IIC11 VSS TOOLRxD/P11, TOOLTxD/P12 SERIAL ARRAY UNIT1 (2ch) SCL20/P15 SDA20/P14 Remark TOOL0/P40 SDAA0/P61 SERIAL INTERFACE IICA0 SCLA0/P60 BUZZER OUTPUT 2 SCK20/P15 SI20/P14 SO20/P13 POR/LVD CONTROL ON-CHIP DEBUG CLOCK OUTPUT CONTROL RxD2/P14 TxD2/P13 13 LINSEL MULTIPLIER& DIVIDER, MULITIPLYACCUMULATOR CSI20 DIRECT MEMORY ACCESS CONTROL IIC20 BCD ADJUSTMENT UART2 KR0/P70 (KR0/P10 to KR5/P15) (KR0/P120, KR1/P02, KR2/P03, KR3/P22 to KR5/P24) ANI0/P20 to ANI4/P24 ANI16/P03, ANI17/P02, ANI18/P10, ANI19/P120 to ANI24/P15, ANI26/P50, ANI27/P30, ANI28/P70, ANI29/P31 AVREFP/P20 AVREFM/P21 RESET CONTROL VDD SCK11/P30 SI11/P50 SO11/P51 1(6) 5 DATA FLASH MEMORY SERIAL ARRAY UNIT0 (4ch) RxD0/P11 TxD0/P12 KEY RETURN P137 PCLBUZ0/P31, PCLBUZ1/P15 SYSTEM CONTROL RESET X1/P121 HIGH-SPEED ON-CHIP OSCILLATOR X2/EXCLK/P122 VOLTAGE REGULATOR REGC RxD2/P14 INTP0/P137 INTERRUPT CONTROL 2 INTP1/P50, INTP2/P51 2 INTP3/P30, INTP4/P31 Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 12 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 1.5.3 1. OUTLINE 48-pin products TIMER ARRAY UNIT (8ch) PORT 0 2 P02, P03 TI00/P02 TO00/P03 ch0 PORT 1 7 P10 to P16 TI01/TO01/P16 ch1 PORT 2 8 P20 to P27 PORT 3 2 P30, P31 PORT 4 2 P40, P41 PORT 5 2 P50, P51 PORT 6 4 P60 to P63 PORT 7 6 P70 to P75 4 P121 to P124 ch2 TI03/TO03/P31 ch3 ch4 ch5 INTERVAL TIMER ch6 TI07/TO07/P41 RxD2/P14 ch7 WINDOW WATCHDOG TIMER PORT 12 LOW-SPEED ON-CHIP OSCILLATOR RTC1HZ/P30 REAL-TIME CLOCK RL78 CPU CORE SERIAL ARRAY UNIT0 (4ch) RxD0/P11 TxD0/P12 UART0 RxD1/P03 TxD1/P02 UART1 SCK00/P10 SI00/P11 SO00/P12 SCK01/P75 SI01/P74 SO01/P73 CODE FLASH MEMORY IIC00 SCL01/P75 SDA01/P74 IIC01 SCL11/P30 SDA11/P50 IIC11 PORT 14 P140 PORT 15 P150 9 ANI0/P20 to ANI7/P27, ANI8/P150 15 KEY RETURN POWER ON RESET/ VOLTAGE DETECTOR VDD VSS TOOLRxD/P11, TOOLTxD/P12 6(6) RESET CONTROL TOOL0/P40 ON-CHIP DEBUG SDAA0/P61 SERIAL INTERFACE IICA0 SYSTEM CONTROL RESET X1/P121 X2/EXCLK/P122 SCLA0/P60 RxD2/P14 TxD2/P13 2 UART2 LINSEL SCK20/P15 SI20/P14 SO20/P13 SCK21/P70 SI21/P71 SO21/P72 CSI20 CSI21 SCL20/P15 SDA20/P14 IIC20 SCL21/P70 SDA21/P71 IIC21 Remark ON-CHIP CLOCK OUTPUT CONTROL XT2/EXCLKS/P124 PCLBUZ0/P140, PCLBUZ1/P15 VOLTAGE REGULATOR MULTIPLIER& DIVIDER, MULITIPLYACCUMULATOR DIRECT MEMORY ACCESS CONTROL XT1/P123 OSCILLATOR BUZZER OUTPUT KR0/P70 to KR5/P75 (KR0/P10 to KR5/P15) (KR0/P02, KR1/P03 to KR5/P25) POR/LVD CONTROL HIGH-SPEED SERIAL ARRAY UNIT1 (2ch) ANI16/P03, ANI17/P02, ANI18/P10, ANI19/P120, ANI20/P11 to ANI24/P15, ANI25/P51, ANI26/P50, ANI27/P30, ANI28/P70, ANI29/P31, ANI30/P41 AVREFP/P20 AVREFM/P21 CSI01 SCL00/P10 SDA00/P11 P130 P137 A/D CONVERTER RAM CSI11 PORT 13 DATA FLASH MEMORY CSI00 SCK11/P30 SI11/P50 SO11/P51 P120 REGC RxD2/P14 INTP0/P137 INTERRUPT CONTROL 2 INTP1/P50, INTP2/P51 2 INTP3/P30, INTP4/P31 INTP5/P16 INTP6/P140 BCD ADJUSTMENT 2 INTP8/P74, INTP9/P75 Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 13 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 1.5.4 1. OUTLINE 64-pin products TIMER ARRAY UNIT (8ch) PORT 0 7 P00 to P06 TI00/P00 TO00/P01 ch0 PORT 1 7 P10 to P16 TI01/TO01/P16 ch1 PORT 2 8 P20 to P27 PORT 3 2 P30, P31 PORT 4 4 P40 to P43 PORT 5 2 P50, P51 PORT 6 4 P60 to P63 PORT 7 8 P70 to P77 4 P121 to P124 ch2 TI03/TO03/P31 ch3 TI04/TO04/P42 ch4 TI05/TO05/P05 ch5 TI06/TO06/P06 ch6 TI07/TO07/P41 RxD2/P14 ch7 INTERVAL TIMER PORT 12 WINDOW WATCHDOG TIMER P130 P137 PORT 13 LOW-SPEED ON-CHIP OSCILLATOR RTC1HZ/P30 P120 REAL-TIME CLOCK PORT 14 2 P140, P141 PORT 15 5 P150 to P154 13 SERIAL ARRAY UNIT0 (4ch) RxD0/P11 TxD0/P12 UART0 RxD1/P03 TxD1/P02 UART1 SCK00/P10 SI00/P11 SO00/P12 SCK01/P75 SI01/P74 SO01/P73 A/D CONVERTER DATA FLASH MEMORY KEY RETURN CSI00 POWER ON RESET/ VOLTAGE DETECTOR CSI01 SCK10/P04 SI10/P03 SO10/P02 CSI10 SCK11/P30 SI11/P50 SO11/P51 CSI11 SCL00/P10 SDA00/P11 IIC00 SCL01/P75 SDA01/P74 IIC01 IIC10 SCL11/P30 SDA11/P50 IIC11 RAM RESET CONTROL UART2 LINSEL VDD, VSS, TOOLRxD/P11, EVDD0 EVSS0 TOOLTxD/P12 SYSTEM CONTROL RESET X1/P121 X2/EXCLK/P122 HIGH-SPEED SDAA0/P61 SERIAL INTERFACE IICA0 XT1/P123 OSCILLATOR XT2/EXCLKS/P124 SCLA0/P60 VOLTAGE REGULATOR CLOCK OUTPUT CONTROL MULTIPLIER& DIVIDER, MULITIPLYACCUMULATOR CSI20 DIRECT MEMORY ACCESS CONTROL REGC PCLBUZ0/P140, PCLBUZ1/P141 RxD2/P14 INTP0/P137 2 INTP1/P50, INTP2/P51 2 INTP3/P30, INTP4/P31 INTERRUPT CONTROL INTP5/P16 2 INTP6/P140, INTP7/P141 2 INTP8/P74, INTP9/P75 2 INTP10/P76, INTP11/P77 CSI21 SCL20/P15 SDA20/P14 IIC20 SCL21/P70 SDA21/P71 IIC21 Remark TOOL0/P40 ON-CHIP DEBUG 2 SCK20/P15 SI20/P14 SO20/P13 SCK21/P70 SI21/P71 SO21/P72 POR/LVD CONTROL BUZZER OUTPUT SERIAL ARRAY UNIT1 (2ch) TxD2/P13 KR0/P70 to KR7/P77, KR8/P05, KR9/P06 10 (10) (KR0/P00 to KR4/P04, KR5/P22 to KR9/P26) (KR0/P10 to KR5/P15, KR6/P151 to KR9/P154) ON-CHIP SCL10/P04 SDA10/P03 RxD2/P14 15 CODE FLASH MEMORY RL78 CPU CORE ANI0/P20 to ANI7/P27, ANI8/P150 to ANI12/P154 ANI16/P03, ANI17/P02, ANI18/P10, ANI19/P120, ANI20/P11 to ANI24/P15, ANI25//P51, ANI26/P50, ANI27/P30, ANI28/P70, ANI29/P31, ANI30/P41 AVREFP/P20 AVREFM/P21 BCD ADJUSTMENT Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 14 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 1.6 1. OUTLINE Outline of Functions (1/2) Item 25-pin 32-pin 48-pin 64-pin R5F10E8x R5F10EBx R5F10EGx R5F10ELx Code flash memory (KB) 16 to 64 16 to 64 16 to 64 32 to 64 Data flash memory (KB) 4 4 4 4 Note1 RAM (KB) 2 to 4 2 to 4 Note1 2 to 4 Note1 2 to 4 Note1 Memory space 1 MB Main system High-speed system clock clock X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) 1 to 20 MHz: VDD = 2.7 to 3.6 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD = 1.6 to 1.8 V High-speed on-chip oscillator High-speed operation: 1 to 32 MHz (VDD = 2.7 to 3.6 V), High-speed operation: 1 to 16 MHz (VDD = 2.4 to 3.6 V), Low-speed operation: 1 to 8 MHz (VDD = 1.8 to 3.6 V), Low-voltage operation: 1 to 4 MHz (VDD = 1.6 to 3.6 V) − Subsystem clock XT1 (crystal) oscillation, external subsystem clock input (EXCLKS) 32.768 kHz (TYP.): VDD = 1.6 to 3.6 V Low-speed on-chip oscillator 15 kHz (TYP.): VDD = 1.6 to 3.6 V General-purpose register 8 bits × 32 registers (8 bits × 8 registers × 4 banks) Minimum instruction execution time 0.03125 μs (High-speed on-chip oscillator: fIH = 32 MHz operation) 0.05 μs (High-speed system clock: fMX = 20 MHz operation) 30.5 μs (Subsystem clock: fSUB = 32.768 kHz operation) − • • • • Instruction set I/O port Timer Data transfer (8/16 bits) Adder and subtractor/logical operation (8/16 bits) Multiplication (8 bits × 8 bits) Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc. Total 19 26 42 56 CMOS I/O 14 20 32 46 CMOS input 3 3 5 5 CMOS output − − 1 1 N-ch open-drain I/O (6 V tolerance) 2 3 4 4 16-bit timer 8 channels Watchdog timer 1 channel Real-time clock (RTC) − 1 channel Interval timer (IT) Timer output RTC output Notes 1. 1 channel 2 channels (PWM outputs: 1 Note 2 ) − 4 channels Note 2 ) (PWM outputs: 3 7 channels Note 2 (PWM outputs: 6 ) 1 • 1 Hz (subsystem clock: fSUB = 32.768 kHz or ) In the case of the 4 KB, this is about 3 KB when the self-programming function and data flash function are used. 2. The number of outputs varies, depending on the setting. R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 15 of 76 Preliminary document Specifications in this document are tentative and subject to change. Under development RL78/G1A 1. OUTLINE (2/2) Item 25-pin 32-pin 48-pin 64-pin R5F10E8x R5F10EBx R5F10EGx R5F10ELx 1 2 2 2 Clock output/buzzer output • 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, • 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz 2.5 MHz, 5 MHz, 10 MHz (Main system clock: fMAIN = 20 MHz operation) (Main system clock: fMAIN = 20 MHz operation) • 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz (Subsystem clock: fSUB = 32.768 kHz operation) 8/12-bit resolution A/D converter 13 channels 18 channels Serial interface [25-pin products] 24 channels • CSI: 1 channel/UART: 1 channel/simplified I C: 1 channel • CSI: 1 channel/UART: 1 channel/simplified I C: 1 channel 28 channels 2 2 [32-pin products] • CSI: 1 channel/UART: 1 channel/simplified I C: 1 channel • CSI: 1 channel/UART: 1 channel/simplified I C: 1 channel • CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I C: 1 channel 2 2 2 [48-pin products] • 2 CSI: 2 channels/UART: 1 channel/simplified I C: 2 channels • CSI: 1 channel/UART: 1 channel/simplified I C: 1 channel • CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I C: 2 channels 2 2 [64-pin products] 2 I C bus • CSI: 2 channels/UART: 1 channel/simplified I C: 2 channels • CSI: 2 channels/UART: 1 channel/simplified I C: 2 channels • CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I C: 2 channels 2 2 2 1 channel 1 channel 1 channel Multiplier and • 16 bits × 16 bits = 32 bits (Unsigned or signed) divider/multiply-accumulator • 32 bits ÷ 32 bits = 32 bits (Unsigned) 1 channel • 16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed) DMA controller 2 channels Vectored Internal 24 interrupt sources External 6 Key interrupt 0 ch (4 ch) • Reset Power-on-reset circuit 27 6 Note 1 1 ch (6 ch) Note 1 27 27 10 13 6 ch 10 ch Reset by RESET pin • Internal reset by watchdog timer • Internal reset by power-on-reset • Internal reset by voltage detector • Internal reset by illegal instruction execution • Internal reset by RAM parity error • Internal reset by illegal-memory access • Power-on-reset: Note 2 1.51 ±0.03 V • Power-down-reset: 1.50 ±0.03 V Voltage detector 1.63 V to 3.06 V (12 stages) On-chip debug function Provided Power supply voltage VDD = 1.6 to 3.6 V Operating ambient temperature TA = −40 to +85 °C Notes 1. 2. Can be used by the Peripheral I/O redirection register (PIOR). The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator. R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 16 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. 2. ELECTRICAL SPECIFICATIONS ELECTRICAL SPECIFICATIONS Cautions 1. These specifications show target values, which may change after device evaluation. 2. The RL78/G1A has an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. 3. The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 17 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. 2.1 Absolute Maximum Ratings Absolute Maximum Ratings (TA = 25°C) (1/2) Parameter Supply voltage Symbols Conditions VDD Ratings Unit −0.5 to +6.5 V EVDD0 EVDD0 ≤ VDD −0.5 to +6.5 V AVDD AVDD0 ≤ VDD −0.5 to +4.6 V VSS −0.5 to +0.3 V EVSS0 −0.5 to +0.3 V AVSS −0.5 to +0.3 V REGC pin input voltage VIREGC −0.3 to +2.8 REGC V and −0.3 to VDD +0.3 Input voltage VI1 −0.3 to EVDD0 +0.3 P00 to P06, P10 to P16, P30, P31, P40 to P43, and −0.3 to VDD +0.3 P50, P51, P70 to P77, P120, P140, P141 VI2 VI3 VI4 Output voltage VO1 Note 1 −0.3 to +6.5 P60 to P63 (N-ch open-drain) −0.3 to VDD +0.3 P121 to P124, P137, EXCLK, EXCLKS, RESET V Note 2 V Note 2 P20 to P27, P150 to P154 −0.3 to AVDD +0.3 P00 to P06, P10 to P16, P30, P31, P40 to P43, −0.3 to EVDD0 +0.3 Note 3 Note 2 V V V P50, P51, P60 to P63, P70 to P77, P120, P130, P140, P141 VO2 Analog input voltage VAI1 VAI2 Notes 1. −0.3 to EVDD0 +0.3 ANI0 to ANI12 −0.3 to AVDD +0.3 maximum ratinwg of the REGC pin. Must be 6.5 V or lower. 3. Must be 4.6 V or lower. Note 2 ANI16 to ANI30 Connect the REGC pin to Vss via a capacitor (0.47 to 1 μ F). 2. −0.3 to VDD +0.3 P20 to P27, P150 to P154 Note 2 Note 2 V V V This value regulates the absolute Do not use this pin with voltage applied to it. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 18 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. Absolute Maximum Ratings (TA = 25°C) (2/2) Parameter Output current, high Symbols IOH1 Conditions Per pin P00 to P06, P10 to P16, Ratings Unit −40 mA −70 mA −100 mA −0.1 mA −1.3 mA 40 mA 70 mA 100 mA 0.4 mA 6.4 mA −40 to +85 °C −65 to +150 °C P30, P31, P40 to P43, P50, P51, P70 to P77, P120, P130, P140, P141 Total of all pins P00 to P04, P40 to P43, P120, −170 mA P130, P140, P141 P05, P06, P10 to P16, P30, P31, P50, P51, P70 to P77, IOH2 Per pin P20 to P27, P150 to P154 Total of all pins Output current, low IOL1 Per pin P00 to P06, P10 to P16, P30, P31, P40 to P43, P50, P51, P60 to P63, P70 to P77, P120, P130, P140, P141 Total of all pins P00 to P04, P40 to P43, P120, 170 mA P130, P140, P141 P05, P06, P10 to P16, P30, P31, P50, P51, P60 to P63, P70 to P77 IOL2 Per pin P20 to P27, P150 to P154 Total of all pins Operating ambient TA temperature Storage temperature In normal operation mode In flash memory programming mode Tstg Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 19 of 76 Preliminary document Specifications in this document are tentative and subject to change. Under development RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. 2.2 2.2.1 Oscillator Characteristics Main system clock oscillator characteristics (TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Recommended Resonator Parameter Conditions MIN. TYP. MAX. Unit Circuit Ceramic resonator VSS X1 C1 X2 Rd X1 clock oscillation Note frequency (fX) 1.0 20.0 MHz 1.8 V ≤ VDD < 2.7 V 1.0 8.0 MHz 1.6 V ≤ VDD < 1.8 V 1.0 4.0 MHz 2.7 V ≤ VDD ≤ 3.6 V 1.0 20.0 MHz 1.8 V ≤ VDD < 2.7 V 1.0 8.0 MHz 1.6 V ≤ VDD < 1.8 V 1.0 4.0 MHz C2 X1 clock oscillation Crystal resonator VSS X1 C1 2.7 V ≤ VDD ≤ 3.6 V X2 Rd Note frequency (fX) C2 Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Cautions 1. When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with the other signal lines. • Do not route the wiring near a signal line through which a high fluctuating current flows. • Always make the ground point of the oscillator capacitor the same potential as VSS. • Do not ground the capacitor to a ground pattern through which a high current flows. • Do not fetch signals from the oscillator. 2. Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 20 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. 2.2.2 On-chip oscillator characteristics (TA = −20 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Oscillators Parameters High-speed on-chip oscillator clock frequency fIH Conditions 1.8 V ≤ VDD ≤ 3.6 V MIN. TYP. MAX. Unit 32 MHz selected 31.68 32.00 32.32 MHz 24 MHz selected 23.76 24.00 24.24 MHz 16 MHz selected 15.84 16.00 16.16 MHz 12 MHz selected 11.88 12.00 12.12 MHz 8 MHz selected 7.92 8.00 8.08 MHz 4 MHz selected 3.96 4.00 4.04 MHz 1 MHz selected 0.99 1.00 1.01 MHz 32 MHz selected 30.40 32.00 33.60 MHz 24 MHz selected 22.80 24.00 25.20 MHz 16 MHz selected 15.20 16.00 16.80 MHz 12 MHz selected 11.40 12.00 12.60 MHz 8 MHz selected 7.60 8.00 8.40 MHz 4 MHz selected 3.80 4.00 4.20 MHz 1 MHz selected 0.95 1.00 1.05 MHz 12.75 15 17.25 kHz MIN. TYP. MAX. Unit 32 MHz selected 31.52 32.00 32.48 MHz 24 MHz selected 23.64 24.00 24.36 MHz 16 MHz selected 15.76 16.00 16.24 MHz 12 MHz selected 11.82 12.00 12.18 MHz 8 MHz selected 7.88 8.00 8.12 MHz 4 MHz selected 3.94 4.00 4.06 MHz 1 MHz selected 0.985 1.00 1.015 MHz 32 MHz selected 30.24 32.00 33.76 MHz 24 MHz selected 22.68 24.00 25.32 MHz 16 MHz selected 15.12 16.00 16.88 MHz 12 MHz selected 11.34 12.00 12.66 MHz 8 MHz selected 7.56 8.00 8.44 MHz 4 MHz selected 3.78 4.00 4.22 MHz 1 MHz selected 0.945 1.00 1.055 MHz 12.75 15 17.25 kHz Note 1.6 V ≤ VDD < 1.8 V Low-speed on-chip oscillator fIL clock frequency (TA = −40 to −20°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Oscillators Parameters High-speed on-chip oscillator clock frequency fIH Conditions 1.8 V ≤ VDD ≤ 3.6 V Note 1.6 V ≤ VDD < 1.8 V Low-speed on-chip oscillator fIL clock frequency Note This only indicates the oscillator characteristics. Refer to AC Characteristics for instruction execution time. R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 21 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. 2.2.3 Subsystem clock oscillator characteristics (TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Recommended Resonator Items Conditions MIN. TYP. MAX. Unit 32 32.768 35 kHz Circuit Crystal resonator XT1 clock oscillation VSS XT2 XT1 Note frequency (fXT) Rd C4 Note C3 Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Cautions 1. When using the XT1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. 2. • Keep the wiring length as short as possible. • Do not cross the wiring with the other signal lines. • Do not route the wiring near a signal line through which a high fluctuating current flows. • Always make the ground point of the oscillator capacitor the same potential as VSS. • Do not ground the capacitor to a ground pattern through which a high current flows. • Do not fetch signals from the oscillator. The XT1 oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the X1 oscillator. Particular care is therefore required with the wiring method when the XT1 clock is used. R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 22 of 76 Preliminary document Specifications in this document are tentative and subject to change. Under development RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. 2.3 DC Characteristics 2.3.1 Pin characteristics (TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Items Symbol Output current, Note 1 high IOH1 Conditions Notes 1. TYP. MAX. Unit −10.0 mA Per pin for P00 to P06, P10 to P16, P30, P31, P40 to P43, P50, P51, P70 to P77, P120, P130, P140, P141 1.6 V ≤ EVDD0 ≤ 3.6 V Total of P00 to P04, P40 to P43, P120, P130, P140, P141 Note 3 (When duty = 70% ) 2.7 V ≤ EVDD0 ≤ 3.6 V −10.0 mA 1.8 V ≤ EVDD0 < 2.7 V −5.0 mA 1.6 V ≤ EVDD0 < 1.8 V −2.5 mA 2.7 V ≤ EVDD0 ≤ 3.6 V −19.0 mA 1.8 V ≤ EVDD0 < 2.7 V −10.0 mA 1.6 V ≤ EVDD0 < 1.8 V −5.0 mA Total of all pins Note 3 ) (When duty = 70% 1.6 V ≤ EVDD0 ≤ 3.6 V −29.0 mA Per pin for P20 to P27, P150 to P154 1.6 V ≤ AVDD ≤ 3.6 V Total of all pins Note 3 ) (When duty = 70% 1.6 V ≤ AVDD ≤ 3.6 V Total of P05, P06, P10 to P16, P30, P31, P50, P51, P70 to P77, Note 3 (When duty = 70% ) IOH2 MIN. Note 2 −0.1 Note 2 −1.3 mA mA Value of current at which the device operation is guaranteed even if the current flows from the EVDD0, VDD pins to an output pin. 2. 3. However, do not exceed the total current value. Specification under conditions where the duty factor is 70%. The output current value that has changed the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). • Total output current of pins = (IOH × 0.7)/(n × 0.01) <Example> Where n = 50% and IOH = −10.0 mA Total output current of pins = (−10.0 × 0.7)/(50 × 0.01) = −14.0 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Cautions 1. P00, P02 to P04, P10 to P15, P43, P50, P71, and P74 do not output high level in N-ch open-drain mode. 2. Always use AVDD pin with the same potential as the VDD pin. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 23 of 76 Preliminary document Specifications in this document are tentative and subject to change. Under development RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (TA = −40 to +85°C, 1.6 V ≤ AVDD ≤ 3.6 V, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Items Symbol Output current, Note 1 low IOL1 Conditions MIN. TYP. Per pin for P00 to P06, P10 to P16, P30, P31, P40 to P43, P50, P51, P70 to P77, P120, P130, P140, P141 20.0 Per pin for P60 to P63 15.0 Note 2 Total of P05, P06, P10 to P16, P30, P31, P50, P51, P60 to P63, P70 to P77 Note 3 ) (When duty = 70% mA 15.0 mA 1.8 V ≤ EVDD0 < 2.7 V 9.0 mA 1.6 V ≤ EVDD0 < 1.8 V 4.5 mA 2.7 V ≤ EVDD0 ≤ 3.6 V 35.0 mA 1.8 V ≤ EVDD0 < 2.7 V 20.0 mA 1.6 V ≤ EVDD0 < 1.8 V 10.0 mA 50.0 mA Per pin for P20 to P27, P150 to P154 Total of all pins Note 3 ) (When duty = 70% mA 2.7 V ≤ EVDD0 ≤ 3.6 V Total of all pins Note 3 ) (When duty = 70% Notes 1. Unit Note 2 Total of P00 to P04, P40 to P43, P120, P130, P140, P141 Note 3 (When duty = 70% ) IOL2 MAX. 0.4 1.6 V ≤ AVDD ≤ 3.6 V Note 2 5.2 mA mA Value of current at which the device operation is guaranteed even if the current flows from an output pin to the EVSS0 and VSS pin. 2. 3. However, do not exceed the total current value. Specification under conditions where the duty factor is 70%. The output current value that has changed the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). • Total output current of pins = (IOL × 0.7)/(n × 0.01) <Example> Where n = 50% and IOL = 10.0 mA Total output current of pins = (10.0 × 0.7)/(50 × 0.01) = 14.0 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Caution Always use AVDD pin with the same potential as the VDD pin. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 24 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (TA = −40 to +85°C, 1.6 V ≤ AVDD ≤ 3.6 V, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Items Input voltage, Symbol VIH1 Conditions P00 to P06, P10 to P16, P30, P31, MIN. Normal input buffer TYP. MAX. Unit 0.8EVDD0 EVDD0 V 2.0 EVDD0 V 1.5 EVDD0 V P40 to P43, P50, P51, P70 to P77, high P120, P140, P141 VIH2 P01, P03, P04, P10, P11, TTL input buffer P13 to P16, P43 3.3 V ≤ EVDD0 < 3.6 V TTL input buffer 1.6 V ≤ EVDD0 < 3.3 V Input voltage, VIH3 P20 to P27, P150 to P154 0.7AVDD AVDD V VIH4 P60 to P63 0.7EVDD0 6.0 V VIH5 P121 to P124, P137, EXCLK, EXCLKS, RESET VIL1 P00 to P06, P10 to P16, P30, P31, 0.8VDD VDD V Normal input buffer 0 0.2EVDD0 V P01, P03, P04, P10, P11, TTL input buffer 0 0.5 V P13 to P16, P43 3.3 V ≤ EVDD0 < 3.6 V 0 0.32 V P40 to P43, P50, P51, P70 to P77, low P120, P140, P141 VIL2 TTL input buffer 1.6 V ≤ EVDD0 < 3.3 V VIL3 P20 to P27, P150 to P154 0 0.3AVDD V VIL4 P60 to P63 0 0.3EVDD0 V VIL5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0 0.2VDD V Cautions 1. The maximum value of VIH of pins P00, P02 to P04, P10 to P15, P43, P50, P71, and P74 is EVDD0, even in the N-ch open-drain mode. 2. Always use AVDD pin with the same potential as the VDD pin. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 25 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (TA = −40 to +85°C, 1.6 V ≤ AVDD ≤ 3.6 V, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Items Symbol Output voltage, VOH1 high Conditions MIN. P00 to P06, P10 to P16, P30, P31, 2.7 V ≤ EVDD0 ≤ 3.6 V, EVDD0 − P40 to P43, P50, P51, P70 to P77, IOH1 = −2.0 mA P120, P130, P140, P141 1.8 V ≤ EVDD0 ≤ 3.6 V, EVDD0 − IOH1 = −1.5 mA TYP. MAX. V 0.6 V 0.5 1.6 V ≤ EVDD0 < 3.6 V, EVDD0 − IOH1 = −1.0 mA VOH2 P20 to P27, P150 to P154 Output voltage, VOL1 low V 0.5 1.6 V ≤ AVDD ≤ 3.6 V, AVDD − IOH2 = −100 μ A P00 to P06, P10 to P16, P30, P31, 2.7 V ≤ EVDD0 ≤ 3.6 V, P40 to P43, P50, P51, P70 to P77, IOL1 = 3.0 mA P120, P130, P140, P141 2.7 V ≤ EVDD0 ≤ 3.6 V, Unit V 0.5 0.6 V 0.4 V 0.4 V 0.4 V 0.4 V 0.4 V 0.4 V 0.4 V IOL1 = 1.5 mA 1.8 V ≤ EVDD0 ≤ 3.6 V, IOL1 = 0.6 mA 1.6 V ≤ EVDD0 < 1.8 V, IOL1 = 0.3 mA VOL2 P20 to P27, P150 to P154 1.6 V ≤ AVDD ≤ 3.6 V, IOL2 = 400 μ A VOL3 P60 to P63 2.7 V ≤ EVDD0 ≤ 3.6 V, IOL3 = 3.0 mA 1.8 V ≤ EVDD0 ≤ 3.6 V, IOL3 = 2.0 mA 1.6 V ≤ EVDD0 < 1.8 V, IOL3 = 1.0 mA Caution 1. P00, P02 to P04, P10 to P15, P43, P50, P71, and P74 do not output high level in N-ch open-drain mode. 2. Remark Always use AVDD pin with the same potential as the VDD pin. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 26 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (TA = −40 to +85°C, 1.6 V ≤ AVDD ≤ 3.6 V, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Items Symbol Input leakage ILIH1 Conditions P00 to P06, P10 to P16, P30, MIN. TYP. MAX. Unit VI = EVDD0 1 μA VI = VDD 1 μA 1 μA 10 μA P31, P40 to P43, P50, P51, current, high P60 to P63, P70 to P77, P120, P140, P141 ILIH2 P20 to P27, P137, P150 to P154, RESET ILIH3 P121 to P124 VI = VDD In input port or (X1, X2, XT1, XT2, EXCLK, external clock EXCLKS) input In resonator connection Input leakage ILIH4 P20 to P27, P150 to P154 VI = AVDD 1 μA ILIL1 P00 to P06, P10 to P16, VI = EVSS0 −1 μA VI = VSS −1 μA −1 μA −10 μA P30, P31, P40 to P43, current, low P50, P51, P60 to P67, P70 to P77, P120, P140, P141 ILIL2 P20 to P27, P137, P150 to P154, RESET ILIL3 P121 to P124 VI = VSS In input port or (X1, X2, XT1, XT2, EXCLK, external clock EXCLKS) input In resonator connection On-chip pull-up ILIL4 P20 to P27, P150 to P154 VI = AVSS RU P00 to P06, P10 to P16, P30, VI = EVSS0, In input port 10 20 −1 μA 100 kΩ P31, P40 to P43, P50, P51, resistance P70 to P77, P120, P140, P141 Caution Always use AVDD pin with the same potential as the VDD pin. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 27 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. 2.3.2 Supply current characteristics (TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Symbol Supply current IDD1 Note 1 Conditions Operating mode High-speed fIH = 32 MHz Note 5 operation Note 3 (1/2) MIN. TYP. MAX. Unit Basic operation VDD = 3.0 V 2.1 mA Normal operation VDD = 3.0 V 4.6 7.0 mA fIH = 24 MHz Note 3 Normal operation VDD = 3.0 V 3.7 5.5 mA fIH = 16 MHz Note 3 Normal operation VDD = 3.0 V 2.7 4.0 mA 1.2 1.8 mA fIH = 8 MHz Low-speed Note 5 operation Note 3 Normal operation VDD = 3.0 V VDD = 2.0 V 1.2 1.8 mA Low-voltage fIH = 4 MHz Note 5 operation Note 3 Normal operation VDD = 3.0 V 1.2 1.7 mA VDD = 2.0 V 1.2 1.7 mA Note 2 Normal operation Square wave input 3.0 4.6 mA Resonator connection 3.2 4.8 mA Note 2 Normal operation Square wave input 1.9 2.7 mA Resonator connection High-speed fMX = 20 MHz Note 5 operation VDD = 3.0 V , fMX = 10 MHz , VDD = 3.0 V Note 2 Low-speed fMX = 8 MHz Note 5 operation VDD = 3.0 V , Note 2 fMX = 8 MHz , VDD = 2.0 V Subsystem clock operation fSUB = 32.768 kHz Note 4 1.9 2.7 mA Normal operation Square wave input 1.1 1.7 mA Resonator connection 1.1 1.7 mA Normal operation Square wave input 1.1 1.7 mA Resonator connection 1.1 1.7 mA Normal operation Square wave input 4.1 μA Resonator connection 4.2 μA Normal operation Square wave input 4.1 4.9 μA Resonator connection 4.2 5.0 μA Normal operation Square wave input 4.2 5.5 μA Resonator connection 4.3 5.6 μA Normal operation Square wave input 4.2 6.3 μA Resonator connection 4.3 6.4 μA Square wave input 4.8 7.7 μA Resonator connection 4.9 7.8 μA TA = −40°C fSUB = 32.768 kHz Note 4 TA = +25°C fSUB = 32.768 kHz Note 4 TA = +50°C fSUB = 32.768 kHz Note 4 TA = +70°C fSUB = 32.768 kHz Note 4 Normal operation TA = +85°C (Notes and Remarks are listed on the next page.) R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 28 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the peripheral operation current (except for background operation (BGO)). However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors. 2. When high-speed on-chip oscillator and subsystem clock are stopped. 3. When high-speed system clock and subsystem clock are stopped. 4. When high-speed on-chip oscillator and high-speed system clock are stopped. When real-time counter and watchdog timer is stopped. When AMPHS1 = 1 (Ultra-low power consumption oscillation). 5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. High speed operation: VDD = 2.7 V to 3.6 V@1 MHz to 32 MHz, VDD = 2.4 V to 3.6 V@1 MHz to 16 MHz Low speed operation: VDD = 1.8 V to 3.6 V@1 MHz to 8 MHz Low voltage operation: VDD = 1.6 V to 3.6 V@1 MHz to 4 MHz Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fIH: High-speed on-chip oscillator clock frequency 3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 4. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 29 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Symbol Conditions Supply IDD2 HALT High-speed current Note 2 mode operation Low-speed fIH = 24 MHz Note 4 fIH = 16 MHz Note 4 fIH = 8 MHz Note 4 fIH = 4 MHz Note 4 Note 3 fMX = 20 MHz , VDD = 3.0 V Note 3 , VDD = 3.0 V Low-speed Note 3 fMX = 8 MHz , VDD = 3.0 V fMX = 8 MHz , VDD = 2.0 V 0.54 1.63 mA VDD = 3.0 V 0.44 1.28 mA VDD = 3.0 V 0.40 1.00 mA VDD = 3.0 V 260 530 μA VDD = 2.0 V 260 530 μA VDD = 3.0 V 420 640 μA VDD = 2.0 V 420 640 μA Square wave input 0.28 1.00 mA Resonator connection 0.45 1.17 mA Square wave input 0.19 0.60 mA Resonator connection 0.26 0.67 mA Square wave input 95 330 μA Resonator connection 145 380 μA Square wave input 95 330 μA 380 μA Resonator connection 145 Note 5 Square wave input 0.25 Resonator connection 0.44 fSUB = 32.768 kHz Note 5 Square wave input 0.30 0.57 μA TA = +25°C Resonator connection 0.49 0.76 μA fSUB = 32.768 kHz Square wave input 0.33 1.17 μA TA = +50°C Resonator connection 0.52 1.36 μA fSUB = 32.768 kHz Square wave input 0.36 1.97 μA TA = +70°C Resonator connection 0.55 2.16 μA fSUB = 32.768 kHz Square wave input 0.97 3.37 μA TA = +85°C Resonator connection 1.16 3.56 μA Subsystem fSUB = 32.768 kHz clock TA = −40°C operation Note 5 Note 5 Note 5 Note 6 VDD = 3.0 V Note 7 Note 3 IDD3 Unit Note 7 fMX = 10 MHz operation MAX. Note 7 High-speed operation fIH = 32 MHz TYP. Note 7 Low-voltage operation MIN. Note 4 Note 7 Note 1 operation (2/2) μA μA μA STOP TA = −40°C 0.18 mode TA = +25°C 0.23 0.50 μA TA = +50°C 0.26 1.10 μA TA = +70°C 0.29 1.90 μA TA = +85°C 0.90 3.30 μA (Notes and Remarks are listed on the next page.) R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 30 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors. 2. During HALT instruction execution by flash memory. 3. When high-speed on-chip oscillator and subsystem clock are stopped. 4. When high-speed system clock and subsystem clock are stopped. 5. When operating real-time clock (RTC) and setting ultra-low current consumption (AMPHS1 = 1). When high-speed on-chip oscillator and high-speed system clock are stopped. When watchdog timer is stopped. The values below the MAX. column include the leakage current. 6. When high-speed on-chip oscillator, high-speed system clock, and subsystem clock are stopped. When watchdog timer is stopped. The values below the MAX. column include the leakage current. 7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. High speed operation: VDD = 2.7 V to 3.6 V@1 MHz to 32 MHz, VDD = 2.4 V to 3.6 V@1 MHz to 16 MHz Low speed operation: VDD = 1.8 V to 3.6 V@1 MHz to 8 MHz Low voltage operation: VDD = 1.6 V to 3.6 V@1 MHz to 4 MHz Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fIH: High-speed on-chip oscillator clock frequency 3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 4. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25°C R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 31 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter RTC operating Symbol Conditions TYP. MAX. Unit μA IRTC IWDT Notes 2, 3 fIL = 15 kHz 0.22 IADC Note 4 Reference power supply is other ANI0 to ANI12 than the internal reference voltage, ANI16 to ANI30 AVDD = 3.6 V 460 1090 μA 400 950 μA 400 950 μA fSUB = 32.768 kHz current Watchdog timer MIN. Notes 1, 2 Real-time clock operation 0.02 Interval timer operation 0.02 μA operating current A/D converter operating current Reference power supply is the internal reference voltage, AVDD = 3.6 V Temperature sensor operating current ITMPS LVD operating ILVI ANI0 to ANI12, ANI16 to ANI30 Note 5 75 μA 0.08 μA current BGO operating IBGO Note 6 2.50 12.20 mA current Notes 1. Current flowing only to the real-time clock (excluding the operating current of the XT1 oscillator). The TYP. value of the current value of the RL78/G1A is the sum of the TYP. values of either IDD1 or IDD2, and IRTC, when the real-time clock operates in operation mode or HALT mode. The IDD1 and IDD2 MAX. values also include the real-time clock operating current. However, IDD2 subsystem clock operation includes the operational current of the real-time clock. 2. When high speed on-chip oscillator and high-speed system clock are stopped. 3. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator). The current value of the RL78/G1A is the sum of IDD1, IDD2 or IDD3 and IWDT when fCLK = fSUB when the watchdog timer operates in STOP mode. 4. Current flowing only to the A/D converter. The current value of the RL78/G1A is the sum of IDD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode. 5. Current flowing only to the LVD circuit. The current value of the RL78/G1A is the sum of IDD1, IDD2 or IDD3 and ILVI when the LVD circuit operates in the Operating, HALT or STOP mode. 6. Current flowing only to the BGO. The current value of the RL78/G1A is the sum of IDD1 or IDD2 and IBGO when the BGO operates in an operation mode. Remarks 1. fIL: Low-speed on-chip oscillator clock frequency 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 3. fCLK: CPU/peripheral hardware clock frequency 4. Temperature condition of the TYP. value is TA = 25°C R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 32 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. 2.4 AC Characteristics 2.4.1 Basic operation (TA = −40 to +85°C, 1.6 V ≤ AVDD ≤ 3.6 V, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Items Instruction cycle (minimum instruction execution time) Symbol TCY MAX. Unit High-speed 2.7 V ≤ VDD ≤ 3.6 V 0.03125 main mode 2.4 V ≤ VDD < 2.7 V 0.0625 Conditions 1 μs 1 μs Low voltage 1.6 V ≤ VDD ≤ 3.6 V main mode 0.25 1 μs Low-speed 1.8 V ≤ VDD ≤ 3.6 V main mode 0.125 1 μs 1.8 V ≤ VDD ≤ 3.6 V 28.5 31.3 μs 1 μs 1 μs 1 μs 0.125 1 μs 2.7 V ≤ VDD ≤ 3.6 V 1.0 20.0 MHz 1.8 V ≤ VDD < 2.7 V 1.0 8.0 MHz 1.6 V ≤ VDD < 1.8 V 1.0 4.0 MHz 32 35 kHz Main system clock (fMAIN) operation Subsystem clock (fSUB) MIN. TYP. 30.5 operation High-speed 2.7 V ≤ VDD ≤ 3.6 V 0.03125 In the self programming main mode 2.4 V ≤ VDD < 2.7 V 0.0625 mode Low voltage 1.8 V ≤ VDD ≤ 3.6 V 0.25 main mode Low-speed 1.8 V ≤ VDD ≤ 3.6 V main mode External main system clock frequency fEX fEXS External main system clock input high-level width, low-level width tEXH, tEXL 2.7 V ≤ VDD ≤ 3.6 V 24 ns 1.8 V ≤ VDD < 2.7 V 60 ns 1.6 V ≤ VDD < 1.8 V tEXHS, tEXLS TI00, TI01, TI03 to TI07 input high-level width, low-level width tTIH, tTIL TO00, TO01, TO03 to TO07 output frequency fTO PCLBUZ0, PCLBUZ1 output frequency Interrupt input high-level width, low-level width fPCL tINTH, tINTL Key interrupt input low-level width tKR 120 ns 13.7 μs Note 1/fMCK+10 ns 2.7 V ≤ EVDD0 ≤ 3.6 V 8 MHz 1.8 V ≤ EVDD0 < 2.7 V 4 MHz 1.6 V ≤ EVDD0 < 1.8 V 2 MHz Low voltage main mode 1.6 V ≤ EVDD0 ≤ 3.6 V 2 MHz Low-speed main mode 1.8 V ≤ EVDD0 ≤ 3.6 V 4 MHz 1.6 V ≤ EVDD0 < 1.8 V 2 MHz High-speed main mode 2.7 V ≤ EVDD0 ≤ 3.6 V 8 MHz 1.8 V ≤ EVDD0 < 2.7 V 4 MHz 1.6 V ≤ EVDD0 < 1.8 V 2 MHz Low voltage main mode 1.8 V ≤ EVDD0 ≤ 3.6 V 4 MHz 1.6 V ≤ EVDD0 < 1.8 V 2 MHz Low-speed main mode 1.8 V ≤ EVDD0 ≤ 3.6 V 4 MHz 1.6 V ≤ EVDD0 < 1.8 V 2 MHz INTP0 1.6 V ≤ VDD ≤ 3.6 V High-speed main mode 1 μs INTP1 to INTP11 1.6 V ≤ EVDD0 ≤ 3.6 V 1 μs KR0 to KR9 1.8 V ≤ EVDD0 ≤ 3.6 V, 250 ns 1 μs 10 μs 1.8 V ≤ AVDD ≤ 3.6 V 1.6 V ≤ EVDD0 < 1.8 V, 1.6 V ≤ AVDD < 1.8 V RESET low-level width tRSL (Note, Caution and Remark are listed on the next page.) R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 33 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. Note The following conditions are required for low voltage interface when EVDD0<VDD 1.8 V ≤ EVDD0 < 2.7 V : MIN. 125 ns 1.6 V ≤ EVDD0 < 1.8 V : MIN. 250 ns Caution Always use AVDD pin with the same potential as the VDD pin. Remark fMCK: Timer array unit operation clock frequency (Operation clock to be set by the CKS0n bit of timer mode register 0n (TMR0n). n: Channel number (n = 0 to 7)) R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 34 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. 2.5 2.5.1 Peripheral Functions Characteristics Serial array unit (1) During communication at same potential (UART mode) (dedicated baud rate generator output) (TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Transfer rate Symbol Conditions MIN. TYP. Note 1 MAX. fMCK/6 Theoretical value of the Note 2 5.3 Unit bps Mbps maximum transfer rate fCLK = 32 MHz, fMCK = fCLK UART mode connection diagram (during communication at same potential) Rx TxDq User's device RL78/G1A Tx RxDq UART mode bit width (during communication at same potential) (reference) 1/Transfer rate High-/Low-bit width Baud rate error tolerance TxDq RxDq Notes 1. Transfer rate in the SNOOZE mode is max. 9600 bps, min. 4800 bps. 2. The following conditions are required for low voltage interface when EVDD0 < VDD. 2.4 V ≤ EVDD0 < 2.7 V : MAX. 2.6 Mbps 1.8 V ≤ EVDD0 < 2.4 V : MAX. 1.3 Mbps 1.6 V ≤ EVDD0 < 1.8 V : MAX. 0.6 Mbps Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. 2. q: UART number (q = 0 to 2), g: PIM and POM number (g = 0, 1) fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10, 11)) R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 35 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (2) During communication at same potential (CSI mode) (master mode (fMCK/2), SCKp... internal clock output) (TA = −40 to +85°C, 2.7 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Symbol Conditions SCKp cycle time tKCY1 2.7 V ≤ EVDD0 ≤ 3.6 V SCKp high-/low-level width tKH1, 2.7 V ≤ EVDD0 ≤ 3.6 V MIN. 83.3 TYP. MAX. Unit Note 1 ns tKCY1/2 − 10 ns tKL1 SIp setup time (to SCKp↑) Note 2 SIp hold time (from SCKp↑) Note 3 Delay time from SCKp↓ to SOp output tSIK1 2.7 V ≤ EVDD0 ≤ 3.6 V tKSI1 2.7 V ≤ EVDD0 ≤ 3.6 V tKSO1 33 Note 5 ns 10 Note 6 C = 20 pF ns 10 ns Note 4 Notes 1. The value must also be 2/fCLK or more. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 5. Using the fMCK within 24 MHz. 6. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. 2. This specification is valid only when CSI00’s peripheral I/O redirect function is not used. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM numbers (g = 1) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 36 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (3) During communication at same potential (CSI mode) (master mode (fMCK/4), SCKp... internal clock output) (TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Symbol SCKp cycle time tKCY1 Conditions 2.7 V ≤ EVDD0 ≤ 3.6 V 2.4 V ≤ EVDD0 ≤ 3.6 V 1.8 V ≤ EVDD0 ≤ 3.6 V 1.6 V ≤ EVDD0 ≤ 3.6 V SCKp high-/low-level width MIN. TYP. MAX. Unit 125 Note 1 ns 250 Note 1 ns 500 Note 1 ns 1000 Note 1 ns tKH1, 2.7 V ≤ EVDD0 ≤ 3.6 V tKCY1/2 − 18 ns tKL1 2.4 V ≤ EVDD0 ≤ 3.6 V tKCY1/2 − 38 ns 1.8 V ≤ EVDD0 ≤ 3.6 V tKCY1/2 − 50 ns 1.6 V ≤ EVDD0 ≤ 3.6 V tKCY1/2 − ns 100 SIp setup time (to SCKp↑) Note 2 SIp hold time (from SCKp↑) Note 3 Delay time from SCKp↓ to SOp output tSIK1 2.7 V ≤ EVDD0 ≤ 3.6 V 38 ns 2.4 V ≤ EVDD0 ≤ 3.6 V 75 ns 1.8 V ≤ EVDD0 ≤ 3.6 V 150 ns 1.6 V ≤ EVDD0 ≤ 3.6 V 300 ns 19 ns tKSI1 tKSO1 Note 5 C = 30 pF 25 ns Note 4 Notes 1. The value must also be 4/fCLK or more. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 5. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. 2. This specification is valid only when CSI00’s peripheral I/O redirect function is not used. p: CSI number (p = 00, 01, 10, 11, 20, 21), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2), g: PIM and POM numbers (g = 0, 1) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10, 11)) R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 37 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter SCKp cycle time Note 5 SCKp high-/low-level width Symbol tKCY2 tKH2, Conditions MIN. TYP. MAX. Unit 2.7 V ≤ EVDD0 < 3.6 V 16 MHz < fMCK 8/fMCK ns fMCK ≤ 16 MHz 6/fMCK ns 1.8 V ≤ EVDD0 < 2.7 V 16 MHz < fMCK 8/fMCK ns fMCK ≤ 16 MHz 6/fMCK ns 1.6 V ≤ EVDD0 < 1.8 V 6/fMCK ns 1.6 V ≤ EVDD0≤ 3.6 V tKCY2/2 ns 2.7 V ≤ EVDD0 ≤ 3.6 V 50 ns 1.8 V ≤ EVDD0 < 2.7 V 80 ns 1.6 V ≤ EVDD0 < 1.8 V 160 ns 2.7 V ≤ EVDD0 ≤ 3.6 V 1/fMCK+31 ns 1.8 V ≤ EVDD0 < 2.7 V 1/fMCK+31 ns 1.6 V ≤ EVDD0 < 1.8 V 1/fMCK+ ns tKL2 SIp setup time (to SCKp↑) tSIK2 Note 1 SIp hold time (from SCKp↑) tKSI2 Note 2 250 Delay time from SCKp↓ to SOp output tKSO2 C = 30 pF Note 3 Note 4 2.7 V ≤ EVDD0 < 3.6 V 2/fMCK+44 ns 2.4 V ≤ EVDD0 < 2.7 V 2/fMCK+75 ns 1.8 V ≤ EVDD0 < 2.4 V 2/fMCK+110 ns 1.6 V ≤ EVDD0 < 1.8 V 2/fMCK+220 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SOp output lines. 5. Transfer rate in the SNOOZE mode : MAX. 1 Mbps Caution Select the TTL input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. p: CSI number (p = 00, 01, 10, 11, 20, 21), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2), g: PIM number (g = 0, 1) 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10, 11)) R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 38 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. CSI mode connection diagram (during communication at same potential) SCK SCKp RL78/G1A SIp SO SOp SI User's device CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY1, 2 tKL1, 2 tKH1, 2 SCKp tSIK1, 2 SIp tKSI1, 2 Input data tKSO1, 2 Output data SOp CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY1, 2 tKH1, 2 tKL1, 2 SCKp tSIK1, 2 SIp tKSI1, 2 Input data tKSO1, 2 SOp Remarks 1. 2. Output data p: CSI number (p = 00, 01, 10, 11, 20, 21) m: Unit number, n: Channel number (mn = 00 to 03, 10, 11) R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 39 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. 2 (5) During communication at same potential (simplified I C mode) (TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter SCLr clock frequency Symbol fSCL Conditions MIN. 2.7 V ≤ EVDD0 ≤ 3.6 V, MAX. Unit 1000 kHz 400 kHz 300 kHz 250 kHz Cb = 50 pF, Rb = 2.7 kΩ 1.8 V ≤ EVDD0 ≤ 3.6 V, Cb = 100 pF, Rb = 3 kΩ 1.8 V ≤ EVDD0 < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 1.6 V ≤ EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 kΩ Hold time when SCLr = “L” tLOW 2.7 V ≤ EVDD0 ≤ 3.6 V, 475 ns 1150 ns 1550 ns 1850 ns 475 ns 1150 ns 1550 ns 1850 ns 1/fMCK + 85 ns Cb = 50 pF, Rb = 2.7 kΩ 1.8 V ≤ EVDD0 ≤ 3.6 V, Cb = 100 pF, Rb = 3 kΩ 1.8 V ≤ EVDD0 < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 1.6 V ≤ EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 kΩ Hold time when SCLr = “H” tHIGH 2.7 V ≤ EVDD0 ≤ 3.6 V, Cb = 50 pF, Rb = 2.7 kΩ 1.8 V ≤ EVDD0 ≤ 3.6 V, Cb = 100 pF, Rb = 3 kΩ 1.8 V ≤ EVDD0 < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 1.6 V ≤ EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 kΩ Data setup time (reception) tSU:DAT 2.7 V ≤ EVDD0 ≤ 3.6 V, Note Cb = 50 pF, Rb = 2.7 kΩ 1.8 V ≤ EVDD ≤ 3.6 V, 1/fMCK + 145 ns Note Cb = 100 pF, Rb = 3 kΩ 1.8 V ≤ EVDD0 < 2.7 V, 1/fMCK + 230 ns Note Cb = 100 pF, Rb = 5 kΩ 1.6 V ≤ EVDD0 < 1.8 V, 1/fMCK + 290 ns Note Cb = 100 pF, Rb = 5 kΩ Data hold time (transmission) tHD:DAT 2.7 V ≤ EVDD0 ≤ 3.6 V, 0 305 ns 0 355 ns 0 405 ns 0 405 ns Cb = 50 pF, Rb = 2.7 kΩ 1.8 V ≤ EVDD0 ≤ 3.6 V, Cb = 100 pF, Rb = 3 kΩ 1.8 V ≤ EVDD0 < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 1.6 V ≤ EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 kΩ Note Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H". (Caution and Remarks are listed on the next page.) R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 40 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. 2 Simplified I C mode mode connection diagram (during communication at same potential) VDD Rb SDA SDAr User's device RL78/G1A SCL SCLr 2 Simplified I C mode serial transfer timing (during communication at same potential) 1/fSCL tLOW tHIGH SCLr SDAr tHD:DAT Caution tSU:DAT Select the TTL input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin and the normal output mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register h (POMh). Remarks 1. Rb[Ω]:Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance 2. r: IIC number (r = 00, 01, 10, 11, 20, 21), g: PIM number (g = 0, 1), h: POM number (h = 0, 1) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10, 11) R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 41 of 76 Preliminary document Specifications in this document are tentative and subject to change. Under development RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (6) Communication at different potential (2.5 V) (UART mode) (dedicated baud rate generator output) (1/2) (TA = −40 to +85°C, 1.8 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Symbol Conditions MIN. reception 2.7 V ≤ EVDD0 < 3.6 V, Transfer rate 2.3 V ≤ Vb ≤ 2.7 V TYP. MAX. fMCK/6 Theoretical value of the Unit Note 1 bps 5.3 Mbps fMCK/6 bps maximum transfer rate fCLK = 32 MHz, fMCK = fCLK 1.8 V ≤ EVDD0 < 3.3 V, Notes 1 to 3 1.6 V ≤ Vb ≤ 2.0 V Theoretical value of the 1.3 Mbps maximum transfer rate fCLK = 8 MHz, fMCK = fCLK Notes 1. Transfer rate in the SNOOZE mode : MAX. 9600 bps, MIN. 4800 bps 2. Use it with EVDD0≥Vb. 3. The following conditions are required for low voltage interface when EVDD0 < VDD. 2.4 V ≤ EVDD0 < 2.7 V : MAX. 2.6 Mbps 1.8 V ≤ EVDD0 < 2.4 V : MAX. 1.3 Mbps 1.6 V ≤ EVDD0 < 1.8 V : MAX. 0.6 Mbps Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. Vb[V]: Communication line voltage 2. q: UART number (q = 0 to 2), g: PIM and POM number (g = 0, 1) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10, 11) 4. VIH and VIL below are observation points for the AC characteristics of the serial array unit when communicating at different potentials in UART mode. 2.7 V ≤ EVDD0 < 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V: VIH = 2.0 V, VIL = 0.5 V 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V: VIH = 1.5 V, VIL = 0.32 V 5. UART2 cannnot communicate at different potential when bit 1 (PIOR1) of peripheral I/O redirection register (PIOR) is 1. R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 42 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (6) Communication at different potential (2.5 V) (UART mode) (dedicated baud rate generator output) (2/2) (TA = −40 to +85°C, 1.8 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Transfer rate Symbol Conditions MIN. TYP. transmission 2.7 V ≤ EVDD0 < 3.6 V, MAX. Unit Notes bps 1, 2 2.3 V ≤ Vb ≤ 2.7 V Theoretical value of the 1.2 Note 5 Mbps maximum transfer rate Cb = 50 pF, Rb = 2.7 kΩ, Vb = 2.3 V 1.8 V ≤ EVDD0 < 3.3 V, Notes 1.6 V ≤ Vb ≤ 2.0 V 1, 4, 5 Theoretical value of the maximum transfer rate bps 0.43 Mbps Note 6 Cb = 50 pF, Rb = 5.5 kΩ, Vb = 1.6 V Notes 1. 2. Transfer rate in the SNOOZE mode : MAX. 9600 bps, MIN. 4800 bps The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.7 V ≤ EVDD0 < 3.6 V and 2.3 V ≤ Vb ≤ 2.7 V 1 Maximum transfer rate = {−Cb × Rb × ln (1 − Baud rate error (theoretical value) = 2.0 Vb )} × 3 [bps] 1 2.0 − {−Cb × Rb × ln (1 − Vb )} Transfer rate × 2 1 ( Transfer rate ) × Number of transferred bits × 100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. 3. This value as an example is calculated when the conditions described in the “Conditions” column are met. Refer to Note 2 above to calculate the maximum transfer rate under conditions of the customer. 4. Use it with EVDD0 ≥ Vb. 5. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 1.8 V ≤ EVDD0 < 3.3 V and 1.6 V ≤ Vb ≤ 2.0 V 1 Maximum transfer rate = {−Cb × Rb × ln (1 − Baud rate error (theoretical value) = 1.5 Vb )} × 3 [bps] 1.5 1 − {−Cb × Rb × ln (1 − Vb )} Transfer rate × 2 1 ( Transfer rate ) × Number of transferred bits × 100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. 6. This value as an example is calculated when the conditions described in the “Conditions” column are met. Refer to Note 7 above to calculate the maximum transfer rate under conditions of the customer. R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 43 of 76 Preliminary document Specifications in this document are tentative and subject to change. Under development RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. Rb[Ω]:Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage 2. q: UART number (q = 0 to 2), g: PIM and POM number (g = 0, 1) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10, 11)) 4. VIH and VIL below are observation points for the AC characteristics of the serial array unit when communicating at different potentials in UART mode. 2.7 V ≤ EVDD0 < 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V: VIH = 2.0 V, VIL = 0.5 V 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V: VIH = 1.5 V, VIL = 0.32 V 5. UART2 cannot communicate at different potential when bit 1 (PIOR1) of peripheral I/O redirection register (PIOR) is 1. UART mode connection diagram (during communication at different potential) Vb Rb TxDq Rx User's device RL78/G1A RxDq R01DS0151EJ0001 Rev.0.01 2011.12.26 Tx Page 44 of 76 Preliminary document Specifications in this document are tentative and subject to change. Under development RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. UART mode bit width (during communication at different potential) (reference) 1/Transfer rate Low-bit width High-bit width Baud rate error tolerance TxDq 1/Transfer rate High-/Low-bit width Baud rate error tolerance RxDq Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. UART2 cannot communicate at different potentia when bit 1 (PIOR1) of peripheral I/O redirection register (PIOR) is 1. 2. Rb[Ω]:Communication line (TxDq) pull-up resistance, Vb[V]: Communication line voltage 3. q: UART number (q = 0 to 2), g: PIM and POM number (g = 0, 1) R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 45 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (7) Communication at different potential (2.5 V) (fMCK/2) (CSI mode) (master mode, SCKp... internal clock output) (TA = −40 to +85°C, 2.7 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter SCKp cycle time Symbol tKCY1 Conditions 2.7 V ≤ EVDD0 < 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V, MIN. 300 TYP. MAX. Note 1 Unit ns Cb = 20 pF, Rb = 2.7 kΩ SCKp high-level width tKH1 2.7 V ≤ EVDD0 < 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ SCKp low-level width tKL1 tKCY1/2 − ns 120 2.7 V ≤ EVDD0 < 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V, tKCY1/2 − 10 ns Cb = 20 pF, Rb = 2.7 kΩ SIp setup time (to SCKp↑) tSIK1 (from SCKp↑) tKSI1 10 ns tKSO1 2.7 V ≤ EVDD0 < 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V, 130 ns Note 2 Cb = 20 pF, Rb = 2.7 kΩ tSIK1 2.7 V ≤ EVDD0 < 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V, 33 ns 10 ns Note 3 Cb = 20 pF, Rb = 2.7 kΩ SIp hold time (from SCKp↓) tKSI1 2.7 V ≤ EVDD0 < 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V, Note 3 Delay time from SCKp↑ to Notes 1. 2.7 V ≤ EVDD0 < 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ SIp setup time SOp output ns Note 2 Delay time from SCKp↓ to (to SCKp↓) 121 Cb = 20 pF, Rb = 2.7 kΩ SIp hold time SOp output 2.7 V ≤ EVDD0 < 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V, Note 2 Cb = 20 pF, Rb = 2.7 kΩ tKSO1 2.7 V ≤ EVDD0 < 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V, 10 ns Note 3 Cb = 20 pF, Rb = 2.7 kΩ The value must also be 2/fCLK or more. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. 3. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. (Caution and Remark are listed on the next page.) R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 46 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. CSI mode connection diagram (during communication at different potential) Vb <Master> Vb Rb Rb SCKp SCK SIp SO SOp SI RL78/G1A User's device Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM number (g = 1) 3. VIH and VIL below are observation points for the AC characteristics of the serial array unit when communicating at different potentials in CSI mode. 2.7 V ≤ EVDD0 < 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V: VIH = 2.0 V, VIL = 0.5 V 4. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00) R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 47 of 76 Preliminary document Specifications in this document are tentative and subject to change. Under development RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (8) Communication at different potential (2.5 V) (fMCK/4) (CSI mode) (master mode, SCKp... internal clock output) (1/2) (TA = −40 to +85°C, 1.8 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter SCKp cycle time Symbol tKCY1 Conditions 2.7 V ≤ EVDD0 < 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V, MIN. 500 TYP. MAX. Unit Note ns Cb = 30 pF, Rb = 2.7 kΩ 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, 1150 Note ns Cb = 30 pF, Rb = 5.5 kΩ SCKp high-level width tKH1 2.7 V ≤ EVDD0 < 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 30 pF, Rb = 5.5 kΩ SCKp low-level width tKL1 tKCY1/2 − ns 170 tKCY1/2 − ns 458 2.7 V ≤ EVDD0 < 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V, tKCY1/2 − 18 ns Cb = 30 pF, Rb = 2.7 kΩ 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, tKCY1/2 − 50 ns Cb = 30 pF, Rb = 5.5 kΩ Note The value must also be 4/fCLK or more. Cautions 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). 2. Use it with EVDD0 ≥ Vb. Remarks 1. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00, 01, 10, 20), m: Unit number , n: Channel number (mn = 00, 01, 02, 10), g: PIM and POM number (g = 0, 1) 3. VIH and VIL below are observation points for the AC characteristics of the serial array unit when communicating at different potentials in CSI mode. 2.7 V ≤ EVDD0 < 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V: VIH = 2.0 V, VIL = 0.5 V 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V: VIH = 1.5 V, VIL = 0.32 V 4. CSI01, CSI11 and CSI21 cannot communicate at different potential. Use other CSI for communication at different potential. R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 48 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (8) Communication at different potential (2.5 V) (fMCK/4) (CSI mode) (master mode, SCKp... internal clock output) (2/2) (TA = −40 to +85°C, 1.8 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter SIp setup time Note 1 (to SCKp↑) Symbol tSIK1 Conditions MIN. 2.7 V ≤ EVDD0 < 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V, 177 TYP. MAX. Unit ns 479 ns 19 ns 19 ns Cb = 30 pF, Rb = 2.7 kΩ 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 30 pF, Rb = 5.5 kΩ SIp hold time Note 1 (from SCKp↑) tKSI1 2.7 V ≤ EVDD0 < 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 30 pF, Rb = 5.5 kΩ Delay time from SCKp↓ to Note 1 SOp output tKSO1 2.7 V ≤ EVDD0 < 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V, 195 ns 483 ns Cb = 30 pF, Rb = 2.7 kΩ 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 30 pF, Rb = 5.5 kΩ SIp setup time Note 2 (to SCKp↓) tSIK1 2.7 V ≤ EVDD0 < 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V, 44 ns 110 ns 19 ns 19 ns Cb = 30 pF, Rb = 2.7 kΩ 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 30 pF, Rb = 5.5 kΩ SIp hold time Note 2 (from SCKp↓) tKSI1 2.7 V ≤ EVDD0 < 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 30 pF, Rb = 5.5 kΩ Delay time from SCKp↑ to Note 2 SOp output tKSO1 2.7 V ≤ EVDD0 < 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V, 25 ns 25 ns Cb = 30 pF, Rb = 2.7 kΩ 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 30 pF, Rb = 5.5 kΩ Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. 2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. (Cautions and Remarks are listed on the next page.) R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 49 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. CSI mode connection diagram (during communication at different potential) Vb <Master> Rb Vb Rb SCKp RL78/G1A SCK SIp SO SOp SI User's device Cautions 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). 2. Use it with EVDD0 ≥ Vb. Remarks 1. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00, 01, 10, 20), m: Unit number , n: Channel number (mn = 00, 01, 02, 10), g: PIM and POM number (g = 0, 1) 3. VIH and VIL below are observation points for the AC characteristics of the serial array unit when communicating at different potentials in CSI mode. 2.7 V ≤ EVDD0 < 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V: VIH = 2.0 V, VIL = 0.5 V 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V: VIH = 1.5 V, VIL = 0.32 V 4. CSI01, CSI11 and CSI21 cannot communicate at different potential. Use other CSI for communication at different potential. R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 50 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY1 tKL1 tKH1 SCKp tSIK1 SIp tKSI1 Input data tKSO1 SOp Output data CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY1 tKL1 tKH1 SCKp tSIK1 SIp tKSI1 Input data tKSO1 SOp Output data Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. p: CSI number (p = 00, 01, 10, 20), m: Unit number, n: Channel number (m = 00, 01, 02, 10), g: PIM and POM number (g = 0, 1) 2. CSI01, CSI11 and CSI21 cannot communicate at different potential. Use other CSI for communication at different potential. R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 51 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (9) Communication at different potential (2.5 V) (CSI mode) (slave mode, SCKp... external clock input) (TA = −40 to +85°C, 1.8 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter SCKp cycle time Note 1 Symbol tKCY2 Conditions MIN. tKH2, width tKL2 MAX. Unit 2.7 V ≤ EVDD0 < 3.6 V, 24 MHz < fMCK 20/fMCK ns 2.3 V ≤ Vb ≤ 2.7 V 20 MHz < fMCK ≤ 24 MHz 16/fMCK ns 16 MHz < fMCK ≤ 20 MHz 14/fMCK ns 8 MHz < fMCK ≤ 16 MHz 12/fMCK ns 4 MHz < fMCK ≤ 8 MHz 8/fMCK ns fMCK ≤ 4 MHz 6/fMCK ns 1.8 V ≤ EVDD0 < 3.3 V, 24 MHz < fMCK 48/fMCK ns 1.6 V ≤ Vb ≤ 2.0 V 20 MHz < fMCK ≤ 24 MHz 36/fMCK ns 16 MHz < fMCK ≤ 20 MHz 32/fMCK ns 8 MHz < fMCK ≤ 16 MHz 26/fMCK ns 4 MHz < fMCK ≤ 8 MHz 16/fMCK ns Note 2 fMCK ≤ 4 MHz SCKp high-/low-level TYP. 2.7 V ≤ EVDD0 < 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V 10/fMCK ns tKCY2/2 − ns 18 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2 tKCY2/2 − ns 50 SIp setup time (to SCKp↑) tSIK2 Note 3 SIp hold time (from SCKp↑) 60 ns 1.8 V ≤ EVDD0 < 3.3 V 97 ns 1/fMCK + 31 ns tKSI2 Note 4 Delay time from SCKp↓ to SOp output 2.7 V ≤ EVDD0 ≤ 3.6 V tKSO2 2.7 V ≤ EVDD0 < 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V, 2/fMCK + Note 5 Cb = 30 pF, Rb = 2.7 kΩ 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V ns 214 Note 2 , Cb = 30 pF, Rb = 5.5 kΩ 2/fMCK + ns 573 Notes 1. Transfer rate in the SNOOZE mode : MAX. 1 Mbps 2. Use it with EVDD0 ≥ Vb. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 5. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. (Caution and Remarks are listed on the next page.) R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 52 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. CSI mode connection diagram (during communication at different potential) Vb <Slave> Rb SCKp RL78/G1A SCK SIp SO SOp SI User's device Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. Rb[Ω]:Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00, 01, 10, 20), m: Unit number (m = 0, 1), n: Channel number (n = 00, 01, 02, 10), g: PIM and POM number (g = 0, 1) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01, 02, 10)) 4. VIH and VIL below are observation points for the AC characteristics of the serial array unit when communicating at different potentials in CSI mode. 2.7 V ≤ EVDD0 < 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V: VIH = 2.0 V, VIL = 0.5 V 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V: VIH = 1.5 V, VIL = 0.32 V 5. CSI01, CSI11 and CSI21 cannot communicate at different potential. Use other CSI for communication at different potential. R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 53 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY2 tKL2 tKH2 SCKp tSIK2 SIp tKSI2 Input data tKSO2 Output data SOp CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY2 tKL2 tKH2 SCKp tSIK2 SIp tKSI2 Input data tKSO2 SOp Output data Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. p: CSI number (p = 00, 01, 10, 20), m: Unit number, n: Channel number (mn = 00, 01, 02, 10), g: PIM and POM number (g = 0, 1) 2. CSI01, CSI11 and CSI21 cannot communicate at different potential. Use other CSI for communication at different potential. R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 54 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. 2 (10) Communication at different potential (2.5 V) (simplified I C mode) (1/2) (TA = −40 to +85°C, 1.8 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter SCLr clock frequency Symbol fSCL Conditions MIN. 2.7 V ≤ EVDD0 ≤ 3.6 V, MAX. Unit 1000 kHz 400 kHz 300 kHz 2.3 V ≤ Vb ≤ 2.7 V, Cb = 50 pF, Rb = 2.7 kΩ 2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 100 pF, Rb = 2.7 kΩ 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 1 , Cb = 100 pF, Rb = 5.5 kΩ Hold time when SCLr = “L” tLOW 2.7 V ≤ EVDD0 ≤ 3.6 V, 475 ns 1150 ns 1550 ns 200 ns 600 ns 610 ns 2.3 V ≤ Vb ≤ 2.7 V, Cb = 50 pF, Rb = 2.7 kΩ 2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 100 pF, Rb = 2.7 kΩ 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 1 , Cb = 100 pF, Rb = 5.5 kΩ Hold time when SCLr = “H” tHIGH 2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 50 pF, Rb = 2.7 kΩ 2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 100 pF, Rb = 2.7 kΩ 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 1 , Cb = 100 pF, Rb = 5.5 kΩ (Notes, Caution and Remarks are listed on the next page.) R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 55 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. 2 (10) Communication at different potential (2.5 V) (simplified I C mode) (2/2) (TA = −40 to +85°C, 1.8 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Data setup time (reception) Data hold time (transmission) Symbol tSU:DAT tHD:DAT Conditions 2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 50 pF, Rb = 2.7 kΩ MIN. MAX. 1/fMCK + 135 Unit ns Note 2 1/fMCK + 190 2.7 V ≤ EVDD0 ≤ 3.6 V, Note 2 2.3 V ≤ Vb ≤ 2.7 V, Cb = 100 pF, Rb = 2.7 kΩ ns 1/fMCK + 190 1.8 V ≤ EVDD0 < 3.3 V, Note 2 Notes 1 , 1.6 V ≤ Vb ≤ 2.0 V Cb = 100 pF, Rb = 5.5 kΩ ns 2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 50 pF, Rb = 2.7 kΩ 0 305 ns 2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 100 pF, Rb = 2.7 kΩ 0 355 ns 1.8 V ≤ EVDD0 < 3.3 V, Note 1 , 1.6 V ≤ Vb ≤ 2.0 V Cb = 100 pF, Rb = 5.5 kΩ 0 405 ns Notes 1. Use it with EVDD0 ≥ Vb. 2. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H". Caution Select the TTL input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin and the N-ch open drain output (VDD tolerance) mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register g (POMg). (Remarks is listed on the next page.) R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 56 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. 2 Simplified I C mode connection diagram (during communication at different potential) Vb Rb Vb Rb SDA SDAr User's device RL78/G1A SCL SCLr 2 Simplified I C mode serial transfer timing (during communication at different potential) 1/fSCL tLOW tHIGH SCLr SDAr tHD:DAT tSU:DAT Caution Select the TTL input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin and the N-ch open drain output (VDD tolerance) mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. Rb[Ω]:Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance, Vb[V]: Communication line voltage 2. r: IIC number (r = 00, 01, 10, 20), g: PIM, POM number (g = 0, 1) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01, 02, 10) 4. VIH and VIL below are observation points for the AC characteristics of the serial array unit when 2 communicating at different potentials in simplified I C mode mode. 2.7 V ≤ EVDD0 < 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V: VIH = 2.0 V, VIL = 0.5 V 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V: VIH = 1.5 V, VIL = 0.32 V R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 57 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. 2.5.2 Serial interface IICA (TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Symbol Standard Conditions Fast Mode Fast Mode MIN. SCLA0 clock frequency fSCL MAX. MIN. MAX. MIN. MAX. 0 1000 Fast mode plus: 2.7 V ≤ EVDD0 ≤ 3.6 V fCLK ≥ 10 MHz Fast mode: 1.8 V ≤ EVDD0 ≤ 3.6 V Unit Plus Mode 0 400 kHz kHz fCLK ≥ 3.5 MHz Normal mode: 1.6 V ≤ EVDD0 ≤ 3.6 V 0 100 kHz fCLK ≥ 1 MHz tSU:STA 4.7 0.6 0.26 μs tHD:STA 4.0 0.6 0.26 μs Hold time when SCLA0 = “L” tLOW 4.7 1.3 0.5 μs Hold time when SCLA0 = “H” tHIGH 4.0 0.6 0.26 μs tSU:DAT 250 100 50 ns Data hold time (transmission) tHD:DAT 0 0 μs Setup time of stop condition tSU:STO 4.0 0.6 0.26 μs Bus-free time tBUF 4.7 1.3 0.5 μs Setup time of restart condition Hold time Note 1 Data setup time (reception) Note 2 Notes 1. 2. Remark 3.45 0 0.9 The first clock pulse is generated after this period when the start/restart condition is detected. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Standard mode: Cb = 400 pF, Rb = 2.7 kΩ Fast mode: Cb = 320 pF, Rb = 1.1 kΩ Fast mode plus: Cb = 120 pF, Rb = 1.1 kΩ IICA serial transfer timing tLOW SCL0 tHD:DAT tHD:STA tHIGH tSU:STA tHD:STA tSU:STO tSU:DAT SDA0 tLOW Stop condition Start condition R01DS0151EJ0001 Rev.0.01 2011.12.26 Restart condition Stop condition Page 58 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. 2.5.3 On-chip debug (UART) (TA = −40 to +85°C, 1.8 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Transfer rate R01DS0151EJ0001 Rev.0.01 2011.12.26 Symbol Conditions MIN. 115.2 k TYP. MAX. Unit 1M bps Page 59 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. 2.6 2.6.1 Analog Characteristics A/D converter characteristics (1) When AVREF (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), AVREF (−) = AVREFM/ANI1 (ADREFM = 1), target ANI pin : ANI0 to ANI12 (supply ANI pin to AVDD) (TA = −40 to +85°C, 1.6 V ≤ VDD ≤ 3.6 V, 1.6 V ≤ AVDD ≤ 3.6 V, VSS = 0 V, AVSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (−) = AVREFM = 0 V) Parameter Symbol Resolution Conditions 2.4 V ≤ AVDD ≤ 3.6 V RES 1.8 V ≤ AVDD ≤ 3.6 V MIN. 8 1.6 V ≤ AVDD ≤ 3.6 V Note 3 Overall error AINL Conversion time tCONV Notes 3, 4 Zero-scale error Full-scale error EZS Notes 3, 4 Integral linearity error EFS Note 3 Differential linearity error ILE Note 3 Reference voltage (+) DLE AVREF(+) TYP. 8 MAX. Unit 12 bit 10 8 Note 1 Note 2 12-bit resolution 2.4 V ≤ AVDD ≤ 3.6 V ±6.0 10-bit resolution 1.8 V ≤ AVDD ≤ 3.6 V ±3.5 8-bit resolution 1.6 V ≤ AVDD ≤ 3.6 V ±1.75 ADTYP = 0, 12-bit resolution 2.4 V ≤ VDD ≤ 3.6 V 3.375 ADTYP = 0, Note 1 10-bit resolution 1.8 V ≤ VDD ≤ 3.6 V 6.75 ADTYP = 0, Note 2 8-bit resolution 1.6 V ≤ VDD ≤ 3.6 V 13.5 ADTYP = 1, 8-bit resolution 2.4 V ≤ VDD ≤ 3.6 V 2.5625 1.8 V ≤ VDD ≤ 3.6 V 5.125 1.6 V ≤ VDD ≤ 3.6 V 10.25 LSB μs 12-bit resolution 2.4 V ≤ VDD ≤ 3.6 V 10-bit resolution 1.8 V ≤ VDD ≤ 3.6 V ±2.5 8-bit resolution 1.6 V ≤ VDD ≤ 3.6 V ±1.25 12-bit resolution 2.4 V ≤ VDD ≤ 3.6 V ±4.0 10-bit resolution 1.8 V ≤ VDD ≤ 3.6 V ±2.5 8-bit resolution 1.6 V ≤ VDD ≤ 3.6 V ±1.25 12-bit resolution 2.4 V ≤ VDD ≤ 3.6 V T.B.D. 10-bit resolution 1.8 V ≤ VDD ≤ 3.6 V T.B.D. 8-bit resolution 1.6 V ≤ VDD ≤ 3.6 V T.B.D. 12-bit resolution 2.4 V ≤ VDD ≤ 3.6 V T.B.D. 10-bit resolution 1.8 V ≤ VDD ≤ 3.6 V T.B.D. 8-bit resolution 1.6 V ≤ VDD ≤ 3.6 V = AVREFP 2.4 V ≤ VDD ≤ 3.6 V 2.4 AVDD 1.8 V ≤ VDD ≤ 3.6 V 1.8 AVDD 1.6 AVDD 1.6 V ≤ VDD ≤ 3.6 V = AVREFM ±4.0 %FSR %FSR LSB LSB T.B.D. V −0.5 0.3 V 0 AVREFP V Reference voltage (−) AVREF(-) Analog input voltage VAIN VBGR 2.4 V ≤ VDD ≤ 3.6 V 1.45 1.5 V Consumption current IADC AVDD = 3.6 V 460 1090 μA VREF current IAVREF AVREFP = 3.6 V 14 25 μA 1.38 Notes 1. Cannot be used for lower 2 bit of ADCR register 2. Cannot be used for lower 4 bit of ADCR register 3. Excludes quantization error (±1/2 LSB). 4. This value is indicated as a ratio (%FSR) to the full-scale value. Caution Always use AVDD pin with the same potential as the VDD pin. R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 60 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (2) When AVREF (+) = AVDD (ADREFP1 = 0, ADREFP0 = 0), AVREF (−) = AVSS (ADREFM = 0), target ANI pin : ANI0 to ANI12 (supply ANI pin to AVDD) (TA = −40 to +85°C, 1.6 V ≤ VDD ≤ 3.6 V, 1.6 V ≤ AVDD ≤ 3.6 V, VSS = 0 V, AVSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (−) = AVREFM = 0 V) Parameter Symbol Resolution Conditions 2.4 V ≤ AVDD ≤ 3.6 V RES 1.8 V ≤ AVDD ≤ 3.6 V MIN. 8 8 1.6 V ≤ AVDD ≤ 3.6 V Note 3 Overall error AINL Conversion time tCONV TYP. MAX. Unit 12 bit 10 8 Note 1 Note 2 12-bit resolution 2.4 V ≤ AVDD ≤ 3.6 V ±9.0 10-bit resolution 1.8 V ≤ AVDD ≤ 3.6 V ±5.0 8-bit resolution 1.6 V ≤ AVDD ≤ 3.6 V ±2.5 ADTYP = 0, 2.4 V ≤ VDD ≤ 3.6 V 3.375 1.8 V ≤ VDD ≤ 3.6 V 6.75 1.6 V ≤ VDD ≤ 3.6 V 13.5 ADTYP = 1, 2.4 V ≤ VDD ≤ 3.6 V 2.5625 8-bit resolution 1.8 V ≤ VDD ≤ 3.6 V 5.125 1.6 V ≤ VDD ≤ 3.6 V 10.25 LSB μs 12-bit resolution ADTYP = 0, 10-bit resolution Note 1 ADTYP = 0, 8-bit resolution Notes 3, 4 Zero-scale error Full-scale error EZS Notes 3, 4 Integral linearity error EFS Note 3 Differential linearity error ILE Note 3 DLE Note 2 12-bit resolution 2.4 V ≤ VDD ≤ 3.6 V ±7.0 10-bit resolution 1.8 V ≤ VDD ≤ 3.6 V ±3.75 8-bit resolution 1.6 V ≤ VDD ≤ 3.6 V ±2.0 %FSR 12-bit resolution 2.4 V ≤ VDD ≤ 3.6 V ±7.0 10-bit resolution 1.8 V ≤ VDD ≤ 3.6 V ±3.75 8-bit resolution 1.6 V ≤ VDD ≤ 3.6 V ±2.0 12-bit resolution 2.4 V ≤ VDD ≤ 3.6 V T.B.D. 10-bit resolution 1.8 V ≤ VDD ≤ 3.6 V T.B.D. 8-bit resolution 1.6 V ≤ VDD ≤ 3.6 V T.B.D. 12-bit resolution 2.4 V ≤ VDD ≤ 3.6 V T.B.D. 10-bit resolution 1.8 V ≤ VDD ≤ 3.6 V T.B.D. 8-bit resolution 1.6 V ≤ VDD ≤ 3.6 V %FSR LSB LSB T.B.D. Reference voltage (+) AVREFP = AVDD 1.6 3.6 V Reference voltage (−) AVREFM = AVSS −0.5 0.3 V Analog input voltage VAIN 0 AVREFP V 1.45 1.5 V VBGR 2.4 V ≤ VDD ≤ 3.6 V Consumption current IADC AVDD = 3.6 V 460 1090 μA VREF current IAVREF AVREFP = 3.6 V 14 25 μA 1.38 Notes 1. Cannot be used for lower 2 bit of ADCR register 2. Cannot be used for lower 4 bit of ADCR register 3. Excludes quantization error (±1/2 LSB). 4. This value is indicated as a ratio (%FSR) to the full-scale value. Caution Always use AVDD pin with the same potential as the VDD pin. R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 61 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (3) When AVREF (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), AVREF (−) = AVREFM/ANI1 (ADREFM = 1), target ANI pin : ANI16 to ANI30 (supply ANI pin to EVDD0) (TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, 1.6 V ≤ AVDD ≤ 3.6 V, VSS = EVSS0 = 0 V, AVSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (−) = AVREFM = 0 V) Parameter Symbol Resolution Conditions 2.4 V ≤ AVDD ≤ 3.6 V RES 1.8 V ≤ AVDD ≤ 3.6 V MIN. 8 8 1.6 V ≤ AVDD ≤ 3.6 V Note 3 Overall error AINL Conversion time tCONV Notes 3, 4 Zero-scale error Full-scale error EZS Notes 3, 4 Integral linearity error EFS Note 3 Differential linearity error ILE Note 3 Reference voltage (+) DLE AVREF(+) MAX. Unit 12 bit 10 8 Note 1 Note 2 12-bit resolution 2.4 V ≤ AVDD ≤ 3.6 V ±9.0 10-bit resolution 1.8 V ≤ AVDD ≤ 3.6 V ±5.0 8-bit resolution 1.6 V ≤ AVDD ≤ 3.6 V ±2.5 ADTYP = 0, 12-bit resolution 2.4 V ≤ VDD ≤ 3.6 V 4.125 ADTYP = 0, Note 1 10-bit resolution 1.8 V ≤ VDD ≤ 3.6 V 9.5 ADTYP = 0, Note 2 8-bit resolution 1.6 V ≤ VDD ≤ 3.6 V 57.5 ADTYP = 1, 8-bit resolution 2.4 V ≤ VDD ≤ 3.6 V 3.3125 1.8 V ≤ VDD ≤ 3.6 V 7.875 1.6 V ≤ VDD ≤ 3.6 V 54.25 LSB μs 12-bit resolution 2.4 V ≤ VDD ≤ 3.6 V ±7.0 10-bit resolution 1.8 V ≤ VDD ≤ 3.6 V ±3.75 8-bit resolution 1.6 V ≤ VDD ≤ 3.6 V ±2.0 12-bit resolution 2.4 V ≤ VDD ≤ 3.6 V ±7.0 10-bit resolution 1.8 V ≤ VDD ≤ 3.6 V ±3.75 %FSR %FSR 8-bit resolution 1.6 V ≤ VDD ≤ 3.6 V ±2.0 12-bit resolution 2.4 V ≤ VDD ≤ 3.6 V T.B.D. 10-bit resolution 1.8 V ≤ VDD ≤ 3.6 V T.B.D. 8-bit resolution 1.6 V ≤ VDD ≤ 3.6 V T.B.D. 12-bit resolution 2.4 V ≤ VDD ≤ 3.6 V T.B.D. 10-bit resolution 1.8 V ≤ VDD ≤ 3.6 V T.B.D. 8-bit resolution 1.6 V ≤ VDD ≤ 3.6 V = AVREFP 2.4 V ≤ VDD ≤ 3.6 V 2.4 AVDD 1.8 V ≤ VDD ≤ 3.6 V 1.8 AVDD 1.6 V ≤ VDD ≤ 3.6 V Reference voltage (−) AVREF((-) Analog input voltage VAIN VBGR 2.4 V ≤ VDD ≤ 3.6 V Consumption current IADC AVDD = 3.6 V VREF current IAVREF AVREFP = 3.6 V = AVREFM Notes 1. 2. 3. 4. Cannot be used for lower 2 bit of ADCR register Cannot be used for lower 4 bit of ADCR register Excludes quantization error (±1/2 LSB). This value is indicated as a ratio (%FSR) to the full-scale value. Caution Always use AVDD pin with the same potential as the VDD pin. R01DS0151EJ0001 Rev.0.01 2011.12.26 TYP. LSB LSB T.B.D. V 1.6 AVDD −0.5 0.3 V 0 AVREFP V 1.45 1.5 V 400 950 μA 14 25 μA 1.38 Page 62 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (4) When AVREF (+) = AVDD (ADREFP1 = 0, ADREFP0 = 0), AVREF (−) = AVSS (ADREFM = 0), target ANI pin : ANI16 to ANI30 (supply ANI pin to EVDD0) (TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD0 ≤ 3.6 V, 1.6 V ≤ AVDD ≤ 3.6 V, VSS = EVSS0 = 0 V, AVSS = 0 V, Reference voltage (+) = AVDD, Reference voltage (−) = AVSS = 0 V) Parameter Symbol Resolution Conditions 2.4 V ≤ AVDD ≤ 3.6 V RES 1.8 V ≤ AVDD ≤ 3.6 V MIN. 8 8 1.6 V ≤ AVDD ≤ 3.6 V Note 3 Overall error AINL Conversion time tCONV TYP. MAX. Unit 12 bit 10 8 Note 1 Note 2 12-bit resolution 2.4 V ≤ AVDD ≤ 3.6 V ±14.0 10-bit resolution 1.8 V ≤ AVDD ≤ 3.6 V ±7.5 8-bit resolution 1.6 V ≤ AVDD ≤ 3.6 V ±3.75 ADTYP = 0, 2.4 V ≤ VDD ≤ 3.6 V 4.125 1.8 V ≤ VDD ≤ 3.6 V 9.5 1.6 V ≤ VDD ≤ 3.6 V 57.5 ADTYP = 1, 2.4 V ≤ VDD ≤ 3.6 V 3.3125 8-bit resolution 1.8 V ≤ VDD ≤ 3.6 V 7.875 1.6 V ≤ VDD ≤ 3.6 V 54.25 LSB μs 12-bit resolution ADTYP = 0, 10-bit resolution Note 1 ADTYP = 0, 8-bit resolution Notes 3, 4 Zero-scale error Full-scale error EZS Notes 3, 4 Integral linearity error EFS Note 3 Differential linearity error ILE Note 3 DLE Note 2 μs 12-bit resolution 2.4 V ≤ VDD ≤ 3.6 V ±9.0 10-bit resolution 1.8 V ≤ VDD ≤ 3.6 V ±5.0 8-bit resolution 1.6 V ≤ VDD ≤ 3.6 V ±2.5 12-bit resolution 2.4 V ≤ VDD ≤ 3.6 V ±9.0 10-bit resolution 1.8 V ≤ VDD ≤ 3.6 V ±5.0 8-bit resolution 1.6 V ≤ VDD ≤ 3.6 V ±2.5 12-bit resolution 2.4 V ≤ VDD ≤ 3.6 V T.B.D. 10-bit resolution 1.8 V ≤ VDD ≤ 3.6 V T.B.D. 8-bit resolution 1.6 V ≤ VDD ≤ 3.6 V T.B.D. 12-bit resolution 2.4 V ≤ VDD ≤ 3.6 V T.B.D. 10-bit resolution 1.8 V ≤ VDD ≤ 3.6 V T.B.D. 8-bit resolution 1.6 V ≤ VDD ≤ 3.6 V %FSR %FSR LSB LSB T.B.D. Reference voltage (+) AVREF(+) = AVDD 1.6 3.6 V Reference voltage (−) AVREF(-) = AVSS −0.5 0.3 V Analog input voltage VAIN 0 AVREFP V 1.45 1.5 V VBGR 2.4 V ≤ VDD ≤ 3.6 V Consumption current IADC AVDD = 3.6 V 400 950 μA VREF current IAVREF AVREFP = 3.6 V 14 25 μA Notes 1. 2. 3. 4. Cannot be used for lower 2 bit of ADCR register Cannot be used for lower 4 bit of ADCR register Excludes quantization error (±1/2 LSB). This value is indicated as a ratio (%FSR) to the full-scale value. Caution Always use AVDD pin with the same potential as the VDD pin. R01DS0151EJ0001 Rev.0.01 2011.12.26 1.38 Page 63 of 76 Preliminary document Specifications in this document are tentative and subject to change. Under development RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (5) When AVREF (+) = Internal reference voltage (1.45 V) (ADREFP1 = 1, ADREFP0 = 0), AVREF (−) = AVSS (ADREFM = 0), target ANI pin : ANI0 to ANI12, ANI16 to ANI30 (TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, 1.6 V ≤ AVDD ≤ 3.6 V, VSS = EVSS0 = 0 V, AVSS0 = 0 V, Reference voltage (+) = Internal reference voltage, Reference voltage (−) = AVSS = 0 V) Parameter Symbol Resolution Conditions MIN. RES Conversion time TYP. MAX. Unit 8 bit μs tCONV 8-bit resolution EZS 8-bit resolution ±2.5 %FSR ILE 8-bit resolution T.B.D. LSB DLE 8-bit resolution T.B.D. LSB Reference voltage (+) AVREF(+) = Internal reference voltage 1.38 1.5 V Reference voltage (−) AVREF(-) = AVSS −0.5 0.3 V Analog input voltage VAIN 0 AVREFP V Notes 1, 2 Zero-scale error Integral linearity error Note 1 Differential linearity error Note 1 VBGR Consumption current IADC VREF current IAVREF Notes 1. 2. Caution AVDD = 3.6 V 16 1.45 Conversion prohibit V 400 μA 75 950 μA Excludes quantization error (±1/2 LSB). This value is indicated as a ratio (%FSR) to the full-scale value. Always use AVDD pin with the same potential as the VDD pin. R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 64 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. 2.6.2 Temperature sensor characteristics (TA = −40 to +85°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Symbol Conditions Temperature sensor output voltage VTMPS25 Setting ADS register = 80H, TA = +25°C Reference output voltage VCONST Setting ADS register = 81H Temperature coefficient FVTMPS Temperature sensor that depends on the MIN. TYP. MAX. 1.05 1.38 1.45 Unit V 1.5 −3.6 V mV/C temperature Operation stabilization wait time 2.6.3 tAMP 2 μs POR circuit characteristics (TA = −40 to +85°C, VSS = 0 V) Parameter Detection voltage Minimum pulse width Detection delay time R01DS0151EJ0001 Rev.0.01 2011.12.26 Symbol Conditions MIN. TYP. MAX. Unit VPOR Power supply rise time 1.48 1.51 1.54 V VPDR Power supply fall time 1.47 1.50 1.53 V TPW μs 300 350 μs Page 65 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. 2.6.4 LVD circuit characteristics LVD Detection Voltage of Reset Mode and Interrupt Mode (TA = −40 to +85°C, VPDR ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Detection Supply voltage level Symbol VLVD2 voltage VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 TYP. MAX. Unit Power supply rise time 3.07 3.13 3.19 V Power supply fall time 3.00 3.06 3.12 V Power supply rise time 2.96 3.02 3.08 V Power supply fall time 2.90 2.96 3.02 V Power supply rise time 2.86 2.92 2.97 V Power supply fall time 2.80 2.86 2.91 V Power supply rise time 2.76 2.81 2.87 V Power supply fall time 2.70 2.75 2.81 V Power supply rise time 2.66 2.71 2.76 V Power supply fall time 2.60 2.65 2.70 V Power supply rise time 2.56 2.61 2.66 V 2.50 2.55 2.60 V Power supply rise time 2.45 2.50 2.55 V Power supply fall time 2.40 2.45 2.50 V Power supply rise time 2.05 2.09 2.13 V Power supply fall time 2.00 2.04 2.08 V Power supply rise time 1.94 1.98 2.02 V Power supply fall time 1.90 1.94 1.98 V VLVD11 Power supply rise time 1.84 1.88 1.91 V Power supply fall time 1.80 1.84 1.87 V VLVD12 Power supply rise time 1.74 1.77 1.81 V Power supply fall time 1.70 1.73 1.77 V Power supply rise time 1.64 1.67 1.70 V Power supply fall time 1.60 1.63 1.66 V VLVD9 VLVD10 VLVD13 tLW Detection delay time Remark MIN. Power supply fall time VLVD8 Minimum pulse width Conditions μs 300 300 μs VLVD(n − 1) > VLVDn: n = 3 to 13 R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 66 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. LVD Detection Voltage of Interrupt & Reset Mode (TA = −40 to +85°C, VPDR ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Symbol Interrupt and reset VLVD13 mode VLVD12 VLVD11 VLVD4 VLVD11 VLVD10 VLVD9 VLVD2 VLVD8 VLVD7 VLVD6 VLVD5 VLVD4 VLVD3 R01DS0151EJ0001 Rev.0.01 2011.12.26 Conditions VPOC0, VPOC1, VPOC2 = 0, 0, 0, falling reset voltage: 1.6 V LVIS0, LVIS1 = 1, 0 Rising release reset voltage (+0.1 V) Falling interrupt voltage MIN. TYP. MAX. Unit 1.60 1.63 1.66 V 1.74 1.77 1.81 V 1.70 1.73 1.77 V LVIS0, LVIS1 = 0, 1 Rising release reset voltage 1.84 1.88 1.91 V (+0.2 V) 1.80 1.84 1.87 V LVIS0, LVIS1 = 0, 0 Rising release reset voltage 2.86 2.92 2.97 V (+1.2 V) 2.80 2.86 2.91 V 1.80 1.84 1.87 V LVIS0, LVIS1 = 1, 0 Rising release reset voltage 1.94 1.98 2.02 V (+0.1 V) 1.90 1.94 1.98 V Falling interrupt voltage Falling interrupt voltage VPOC0, VPOC1, VPOC2 = 0, 0, 1, falling reset voltage: 1.8 V Falling interrupt voltage LVIS0, LVIS1 = 0, 1 Rising release reset voltage (+0.2 V) Falling interrupt voltage 2.05 2.09 2.13 V 2.00 2.04 2.08 V LVIS0, LVIS1 = 0, 0 Rising release reset voltage 3.07 3.13 3.19 V (+1.2 V) 3.00 3.06 3.12 V 2.40 2.45 2.50 V LVIS0, LVIS1 = 1, 0 Rising release reset voltage 2.56 2.61 2.66 V (+0.1 V) 2.50 2.55 2.60 V LVIS0, LVIS1 = 0, 1 Rising release reset voltage 2.66 2.71 2.76 V (+0.2 V) 2.60 2.65 2.70 V Falling interrupt voltage VPOC0, VPOC1, VPOC2 = 0, 1, 0, falling reset voltage: 2.4 V Falling interrupt voltage Falling interrupt voltage 2.70 2.75 2.81 V LVIS0, LVIS1 = 1, 0 Rising release reset voltage 2.86 2.92 2.97 V (+0.1 V) 2.80 2.86 2.91 V 2.96 3.02 3.08 V 2.90 2.96 3.02 V VPOC0, VPOC1, VPOC2 = 0, 1, 1, falling reset voltage: 2.7 V Falling interrupt voltage LVIS0, LVIS1 = 0, 1 Rising release reset voltage (+0.2 V) Falling interrupt voltage Page 67 of 76 Preliminary document Specifications in this document are tentative and subject to change. Under development RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. Supply Voltage Rise Time (TA = −40 to +85°C, VSS = 0 V) Parameter Symbol Maximum time to rise to tPUP1 Conditions MIN. When RESET input is not used TYP. MAX. Unit 3.2 ms Note 1.6 V (VDD (MIN.)) (VDD: 0 V → 1.6 V) Note Make sure to raise the power supply in a shorter time than this. Supply Voltage Rise Time Timing • When RESET pin input is not used Supply voltage (VDD) 1.6 V 0V Time POR internal signal tPUP1 R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 68 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. 2.7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = −40 to +85°C) Parameter Data retention supply voltage Symbol Conditions MIN. VDDDR 1.47 TYP. Note MAX. Unit 3.6 V Note The value depends on the POR detection voltage. When the voltage drops, the data is retained before a POR reset is effected, but data is not retained when a POR reset is effected. Operation mode STOP mode Data retention mode VDD VDDDR STOP instruction execution Standby release signal (interrupt request) 2.8 Flash Memory Programming Characteristics (TA = −40 to +85°C, 1.8 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter CPU/peripheral hardware clock Symbol Conditions MIN. fCLK 1.8 V ≤ VDD ≤ 3.6 V Cerwr 1 erase + 1 write after Retained for 20 years TYP. 1 MAX. Unit 32 MHz frequency Number of code flash rewrites 1,000 Times the erase is regarded (Self/serial Number of data flash rewrites Note as 1 rewrite. programming) The retaining years Retained for 1 years are until next rewrite (Self/serial after the rewrite. programming) 1,000,000 Note Retained for 5 years 100,000 (Self/serial programming) Note Note When using flash memory programmer and Renesas Electronics self programming library Remark When updating data multiple times, use the flash memory as one for updating data. R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 69 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 2. ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to 1.3.1 25-pin products to 1.3.4 64-pin products. 2.9 Timing Specs for Switching Modes (TA = −40 to +85°C, 1.8 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Symbol How long from when a pin reset tSUINIT Conditions MIN. TYP. POR and LVD reset must end before the pin MAX. Unit 100 ms reset ends. ends until the initial communication settings are specified How long from when the TOOL0 tSU POR and LVD reset must end before the pin 10 μs 1 ms reset ends. pin is placed at the low level until a pin reset ends How long the TOOL0 pin must be kept at the low level after a reset tHD POR and LVD reset must end before the pin reset ends. ends <1> <2> <3> <4> RESET tHD+ software processing time TOOL0 tSU tSUINIT <1> The low level is input to the TOOL0 pin. <2> The pins reset ends (POR and LVD reset must end before the pin reset ends.). <3> The TOOL0 pin is set to the high level. <4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting. Remark tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within 100 ms from when the external and internal resets end. tSU: How long from when the TOOL0 pin is placed at the low level until a pin reset ends tHD: How long to keep the TOOL0 pin at the low level from when the external and internal resets end R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 70 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 3. PACKAGE DRAWINGS 3. PACKAGE 3.1 DRAWINGS 25-pin products R5F10E8AALA, R5F10E8CALA, R5F10E8DALA, R5F10E8EALA 25-PIN PLASTIC FLGA (3x3) 21x b w S A S AB M A ZD D x e ZE 5 4 B 3 2.27 E 2 C 1 E w S B INDEX MARK y1 S D C B A D 2.27 INDEX MARK A S y S DETAIL OF C PART DETAIL OF D PART (UNIT:mm) R0.17±0.05 0.43±0.05 R0.12±0.05 0.33±0.05 0.50±0.05 0.365±0.05 b (LAND PAD) 0.34±0.05 (APERTURE OF SOLDER RESIST) 0.365±0.05 R0.165±0.05 0.50±0.05 0.33±0.05 0.43±0.05 R0.215±0.05 ITEM D DIMENSIONS 3.00±0.10 E 3.00±0.10 w 0.20 e 0.50 A 0.69±0.07 b 0.24±0.05 x 0.05 y 0.08 y1 0.20 ZD 0.50 ZE 0.50 P25FC-50-2N2-1 2010 Renesas Electronics Corporation. All rights reserved. R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 71 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 3.2 3. PACKAGE DRAWINGS 32-pin products R5F10EBAANA, R5F10EBCANA, R5F10EBDANA, R5F10EBEANA 32-PIN PLASTIC WQFN(5x5) D DETAIL OF A PART E S A A S y S D2 A EXPOSED DIE PAD 1 (UNIT:mm) 8 ITEM 9 32 B D 5.00 ± 0.05 E 5.00 ± 0.05 A e 0.75 ± 0.05 + 0.25 − 0.05 0.07 0.50 Lp 0.40 ± 0.10 b E2 x 25 y 16 DIMENSIONS 0.05 0.05 P32K8-50-3B4-2 17 24 Lp e b x R01DS0151EJ0001 Rev.0.01 2011.12.26 M S AB ITEM EXPOSED DIE PAD VARIATIONS D2 E2 MIN NOM MAX MIN NOM MAX A 3.45 3.50 3.55 3.45 3.50 3.55 Page 72 of 76 Preliminary document Specifications in this document are tentative and subject to change. Under development RL78/G1A 3.3 3. PACKAGE DRAWINGS 48-pin products R5F10EGAAFB, R5F10EGCAFB, R5F10EGDAFB, R5F10EGEAFB 48-PIN PLASTIC LQFP (FINE PITCH)(7x7) HD D detail of lead end 36 25 37 A3 24 c θ E L Lp HE L1 13 48 12 1 (UNIT:mm) ZE e ZD b x M S A A2 ITEM D DIMENSIONS 7.00±0.20 E 7.00±0.20 HD 9.00±0.20 HE 9.00±0.20 A 1.60 MAX. A1 0.10±0.05 A2 1.40±0.05 A3 b S c L y S NOTE Each lead centerline is located within 0.08 mm of its true position at maximum material condition. A1 Lp 0.60±0.15 L1 θ 1.00±0.20 3° +5° −3° e 0.50 x 0.08 y 0.08 ZD 0.75 ZE R01DS0151EJ0001 Rev.0.01 2011.12.26 0.25 0.22±0.05 0.145 +0.055 −0.045 0.50 0.75 P48GA-50-8EU Page 73 of 76 Preliminary document Specifications in this document are tentative and subject to change. Under development RL78/G1A 3. PACKAGE DRAWINGS R5F10EGAANA, R5F10EGCANA, R5F10EGDANA, R5F10EGEANA 48-PIN PLASTIC WQFN(7x7) D DETAIL OF E S A PART A A S y S D2 A EXPOSED DIE PAD 1 (UNIT:mm ) 12 ITEM 13 48 B E2 D 7.00 ± 0.05 E 7.00 ± 0.05 A 0.75 ± 0.05 b + 0.25 − 0.05 0.07 e Lp x y 37 24 36 DIMENSIONS 0.50 0.40 ± 0.10 0.05 0.05 P48K8-50-5B4-3 25 Lp e b R01DS0151EJ0001 Rev.0.01 2011.12.26 x M S AB ITEM EXPOSED DIE PAD VARIATIONS D2 E2 MIN NOM MAX MIN NOM MAX A 5.45 5.50 5.55 5.45 5.50 5.55 Page 74 of 76 Preliminary document Specifications in this document are tentative and subject to change. Under development RL78/G1A 3.4 3. PACKAGE DRAWINGS 64-pin products R5F10ELCAFB, R5F10ELDAFB, R5F10ELEAFB 64-PIN PLASTIC LQFP(FINE PITCH)(10x10) HD D detail of lead end 48 33 49 A3 32 c θ E L Lp HE L1 (UNIT:mm) 17 64 1 16 ZE e ZD b x M S A ITEM D DIMENSIONS 10.00±0.20 E 10.00±0.20 HD 12.00±0.20 HE 12.00±0.20 A 1.60 MAX. A1 0.10±0.05 A2 1.40±0.05 A3 b A2 c S y S NOTE Each lead centerline is located within 0.08 mm of its true position at maximum material condition. R01DS0151EJ0001 Rev.0.01 2011.12.26 A1 L 0.25 0.22±0.05 0.145 +0.055 −0.045 0.50 Lp 0.60±0.15 L1 θ 1.00±0.20 3° +5° −3° e 0.50 x 0.08 y 0.08 ZD 1.25 ZE 1.25 P64GB-50-UEU-1 Page 75 of 76 Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/G1A 3. PACKAGE DRAWINGS R5F10ELCABG, R5F10ELDABG, R5F10ELEABG 64-PIN PLASTIC FBGA (4x4) w D S A ZE ZD A 8 7 6 B 5 4 E 3 2 1 H G F E D C B A INDEX MARK w S B INDEX MARK A y1 A2 S (UNIT:mm) S y e S b x M A1 S A B ITEM D DIMENSIONS E 4.00±0.10 w 0.15 4.00±0.10 A 0.89±0.10 A1 0.20± 0.05 A2 0.69 e 0.40 b 0.25 ± 0.05 x 0.05 y 0.08 y1 0.20 ZD 0.60 ZE 0.60 P64F1-40-AA2-1 2011 Renesas Electronics Corporation. All rights reserved. R01DS0151EJ0001 Rev.0.01 2011.12.26 Page 76 of 76 Revision History Rev. 0.01 Date Dec 26, 2011 RL78/G1A Data Sheet Description Summary Page - First Edition issued SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc. All trademarks and registered trademarks are the property of their respective owners. C-1 NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). (2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. (4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. (5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. (6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. 2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. 3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. 4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. 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Further, you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics. The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc. "Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. 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Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges. 9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics. 12. 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