TOKO TK75001DIMG/75001

TK75001
PWM CONTROLLER
FEATURES
APPLICATIONS
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Optimized for Off-Line Operation
Maximum Duty Ratio 44% (typ.)
Maximum Clock Frequency Above 1 MHz
Frequency Reduction for Improved Overcurrent
Protection
Low Standby Current for Current-Fed Start-Up
Current-Mode or Voltage-Mode Control
Internal User-Adjustable Slope Compensation
Functionally Integrated & Simplified 5-pin Design
Off-Line Power Supplies
Industrial Power Supplies
Telecom Power Supplies
Off-Line Battery Chargers
DESCRIPTION
The TK75001 is a simplified primary side controller
optimized for off-line switching power supplies. It is suitable
for both voltage-mode and current-mode control and has
advanced features not available in controllers with a higher
pin count. The key to full functionality in a 5-pin design is
that the current signal and the error signal are added
together and fed into the feedback pin. A sawtooth current
flowing out of the feedback pin provides a slope
compensation ramp (in current-mode applications) or a
PWM ramp (in voltage-mode applications), in proportion to
the resistance terminating that pin. If the sum of the current
sense signal, error signal and ramp signal exceeds the
Overcurrent Detector threshold indicating that the Current
Control Detector has lost control of the switch current, the
charging current of the timing capacitor will be reduced to
about 25% for the remainder of the clock period. The
reduced charging current causes no more than a one-third
reduction in switching frequency, effectively preventing
short-circuit current runaway.
TK75001
DRV
VCC
GND
NC
GND
NC
CT
FB
1
7500
Note: Pins 2 and 3 must be externally
connected for proper operation.
BLOCK DIAGRAM
VCC
ICT
UVLO
CT
BANDGAP
REFERENCE
ICHG
205 µA
The TK75001 is available in an 8-pin DIP package.
14.5 V
10.5 V
17.5 V
OSCILLATOR
IFR
146 µA
fCLK
IDS
2 mA
ORDERING INFORMATION
TOGGLE FF
R
FREQUENCY
REDUCTION
LATCH
Q
TK75001D
T
Q
S
Tape/Reel Code
SLOPE
COMPENSATION
PWM LATCH
S
Temperature Code
OVERCURRENT
DETECTOR
DRV
Q
R
1.35 V
TEMP. CODE (OPTIONAL)
TAPE/REEL CODE
I: -40 to +85 C
MG: Magazine
CURRENT
CONTROL
DETECTOR
FB
0.98 V
GND
January 1999 TOKO, Inc.
Page 1
TK75001
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (Low Impedance Source) ................ 16 V
Supply Voltage (ICC < 30 mA) ...................... Self Limiting
Power Dissipation (Note 1) ................................ 825 mW
Output Energy (Capacitive Load) .............................. 5 µJ
CT and FB Pins ........................................................ 16 V
Junction Temperature ........................................... 150 °C
Storage Temperature Range ................... -55 to +150 °C
Operating Temperature Range ...................-20 to +80 °C
Extended Temperature Range ................... -40 to +85 °C
Lead Soldering Temperature (10 s) ...................... 235 °C
TK75001 ELECTRICAL CHARACTERISTICS
Test Conditions: VCC = 13 V, CCC = 4.7 µF, CT = 800 pF, CDRV = 1000 pF, TA = Tj = Full Operating Temperature Range.
Typical numbers apply at TA = 25 °C, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
0.5
1.0
mA
14.5
19.0
mA
ICC(START)
Start-up Supply Current
Current Source to VCC Pin
ICC(ON)
Operating Supply Current
VCC(ON)
UVLO Voltage ON
VCC Sweeps Upward, (Note 3)
12.5
14.5
16.0
V
VCC(OFF)
UVLO Voltage OFF
VCC Sweeps Downward
9.0
10.5
12.0
V
VHYST
UVLO Hysteresis
2.8
4.0
VCC(CLAMP)
Internal Clamp Voltage
16.0
17.5
19.0
V
TA = Tj = 25 ° C
44
50
56
kHz
TA = Tj = Full Range (-20 to 80 ° C)
37
63
kHz
3.9
V
ICC = 25 mA, (Note 3)
V
OSCILLATOR SECTION (CT PIN)
fDRV
Frequency at DRV Pin
VCT(PK)
Peak Voltage
VCT(VL)
Valley Voltage
ICT(DIS)
Discharge Current
1.0
CT(MAX)
Maximum Timing Capacitance
4.7
2.5
3.2
1.1
1. 8
V
3.0
mA
nF
CURRENT DETECTOR, FEEDBACK AND FREQUENCY REDUCTION SECTIONS (FB PIN)
TA = Tj = 25 ° C
0.950
TA = Tj = Full Range (-20 to 80 ° C)
0.925
TA = Tj = 25 ° C
1.320
TA = Tj = Full Range (-20 to 80 ° C)
1.305
1.010
V
1.035
V
1.380
V
1.395
V
60
130
ns
80
180
ns
-245
-200
-155
µA
VCT = VCT(VL), TA = Tj = 25 ° C, (Note 2)
-65
-40
-15
µA
VCT = VCT(VL), TA = Tj = 25 ° C, (Note 2)
-200
-160
-120
µA
VCCD
Current Control Detector
Reference Voltage
VOCD
Overcurrent Detector
Reference Voltage
tFB,OC,PD
Propogation Delay to DRV Pin
VFB Steps from 0 to 2 V
tFB,CC,PD
Propogation Delay to DRV Pin
VFB Steps from 0 to 1.20 V, (Note 4)
iSC(PK)
Slope Compensation Peak
Current
VCT = VCT(PK), TA = Tj = 25 ° C, (Note 2)
iSC(VL)
Slope Compensation Valley
Current
iSC(PK-VL)
Slope Compensation Peak to
Valley
Page 2
0.980
1.350
January 1999 TOKO, Inc.
TK75001
TK75001 ELECTRICAL CHARACTERISTICS (CONT.)
Test Conditions: VCC = 13 V, CCC = 4.7 µF, CT = 800 pF, CDRV = 1000 pF, TA = Tj = Full Operating Temperature Range.
Typical numbers apply at TA = 25 °C, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
35
46
55
%
40
44
48
%
FREQUENCY REDUCER (OVERCURRENT PROTECTION TIMING)
fDRV(FR) / fDRV
Frequency Reduction
Ratio
VFB = 1.2 V, 1.6 V
OUTPUT SECTION (DRV PIN)
DDRV(MAX)
Maximim Duty Ratio
tDRV(RISE)
Rise Time
1000 pF load, VCC = 15 V
25
75
ns
tDRV(FALL)
Fall Time
1000 pF load, VCC = 15 V
25
75
ns
VDRV(HIGH)
Output Voltage HIGH
VDRV(LOW)
Note 1:
Note 2:
Note 3:
Note 4:
Output Voltage LOW
IDRV = -40 mA
10.1
11.0
V
IDRV = -100 mA
10.0
10.8
V
IDRV = 40 mA
0.1
0.25
V
IDRV = 100 mA
0.2
0.50
V
IDRV = 5 mA, VCC = 9 V
1.0
1.50
V
Power dissipation is 825 mW when mounted. Derate at 6.6 mW/°C for operation above 25 °C.
For temperature dependence refer to "Slope Compensation Peak Current vs. Temperature" graph.
The UVLO "on" voltage is guaranteed to be below the internal clamp voltage.
Guaranteed by design; not 100% tested.
January 1999 TOKO, Inc.
Page 3
TK75001
TEST CIRCUIT
DRV
VCC
GND
NC
CCC
4.7 µF
OSCILLOSCOPE
1 µF
1000 pF
GND
NC
CT
FB
OSCILLOSCOPE
20 k
CT
800 pF
TYPICAL PERFORMANCE CHARACTERISTICS
FREQUENCY AT DRV PIN VS.
TIMING CAPACITANCE
SUPPLY CURRENT
SUPPLY VOLTAGE
VS.
CURRENT CONTROL REFERENCE
VS. TEMPERATURE
106
TA = -40 °C
DEVICE ON
12
0.6
STANDBY
1.00
0.98
105
VCCD (V)
ICC (mA)
16
FREQUENCY (Hz)
20
TA = 85 °C
104
0.4
0.0
0.96
0.94
0.92
0
4
8
12
16
103
10
18
100
1000
0.90
10000
-40
0
40
80
120
VCC (V)
CT (pF)
TEMPERATURE (°C)
SLOPE COMPENSATION PEAK
CURRENT VS. TEMPERATURE
INPUT CURRENT VS.
FREQUENCY AT DRV
FREQUENCY REDUCTION RATIO VS.
TEMPERATURE
-140
ICC (mA)
iSC(PK) (µA)
30
-180
-220
26
CDRV = 1 nF
22
CDRV = 500 pF
18
CDRV = 0 nF
-260
-40
0
40
80
TEMPERATURE (°C)
Page 4
120
14
FREQ. REDUCTION RATIO (%)
54
-100
50
48
44
40
36
0
200
400
600
FREQUENCY (kHz)
800
-40
0
40
80
120
TEMPERATURE (°C)
January 1999 TOKO, Inc.
TK75001
TYPICAL PERFORMANCE CHARACTERISTICS (CONT.)
SLOPE COMPENSATION RAMP
RFB = 3 k to GND
CT = 800 pF
600
VFB (mV)
450
300
150
0
0
10
20
30
40
50
60
TIME (µs)
January 1999 TOKO, Inc.
Page 5
TK75001
THEORY OF OPERATION
The TK75001 is intended for use as a primary-side Pulse
Width Modulator (PWM) controller. The many features
integrated into a simple 5-pin design allow it to be easily
configured for voltage-mode or current-mode control, fixedfrequency or fixed-off-time operation, off-line bootstrapping, and direct drive of a power MOSFET. The
polarity of the feedback signal allows for simpler interface
with a TL431-derived error signal (see "Applications
Information" section).
terminated, the timing capacitor ramps up to a fixed
threshold at a fixed rate to fix the off-time.
The Undervoltage Lockout (UVLO) feature with hysteresis
minimizes the start-up current which allows a low-power
bootstrap technique to be used for the housekeeping
power. The duty ratio of the TK75001 is limited to less than
fifty percent by a toggle flip-flop, plus time required to
discharge the timing ramp.
The most noteworthy integrated feature in the TK75001 is
the way in which the feedback control pin is configured to
receive the error signal and the current signal for currentmode control. Rather than receiving both inputs into a
comparator, a single input receives both signals summed
together and compares them against a fixed internal
reference. This yields two desirable effects: 1) a currentlimit threshold is automatically established, and 2) the
required error-signal polarity is the inverse of that of a
standard two-input current-mode control system. Generally,
the signal summation requires no additional external
components and the required error-signal polarity is simpler
to achieve.
Two other functions are integrated into the feedback pin.
A current ramp, which can be used to establish either the
slope-compensation ramp for a current-mode control design
or the voltage-comparison ramp for a voltage-mode control
design, flows out of the feedback pin. By adjusting the
terminating resistance at the feedback pin, the desired
ramp magnitude is established. For overcurrent protection,
a second fixed-reference comparator monitors the feedback
pin. If the feedback pin voltage should reach the second
threshold, this indicates that cycle-by-cycle PWM control
is not sufficient for maintaining control of the current (i.e.,
the minimum duty-ratio is too large to achieve volt-second
balance in the magnetics). The overcurrent detection
comparator latches (for one cycle) a reduction in the
source current which feeds the timing capacitor. This has
the effect of reducing the switching frequency and thus,
effectively, the minimum duty ratio, which is just what is
needed to maintain control of the current.
The switching frequency is determined by an internal
current source charging an external timing capacitor. The
timing capacitor is ramped between internally-fixed
thresholds, valley to peak, and then quickly discharged. A
fixed off-time control technique can be readily implemented
by using a small transistor to keep the timing capacitor
discharged during the on-time. When the on-pulse is
Page 6
January 1999 TOKO, Inc.
TK75001
PIN DESCRIPTIONS
SUPPLY VOLTAGE PIN (VCC)
This pin is connected to the supply voltage. The IC is in a
low current (500 µA typ.) standby mode before the supply
voltage exceeds 14.5 V (typ.), which is the upper threshold
of the UVLO circuit. The IC switches back to standby mode
when the supply voltage drops below 10.5 V (typ.). An
internal clamp limits the peak supply voltage to about 17.5
V (typ.). The absolute maximum supply voltage from a low
impedance source is 16 V. The device is always guaranteed
to turn on before the internal clamp turns on.
GROUND PIN (GND)
This pin provides ground return for the IC.
DRIVE PIN (DRV)
This pin drives the external MOSFET with a totem pole
output stage capable of sinking or sourcing a peak current
of about 1 A. In standby mode, the drive pin can sink about
5 mA while keeping the drive pin pulled down to about 1 V.
The maximum duty cycle of the output signal is typically
44%.
current with a peak value of about 200 µA. The error signal
is needed for stabilizing the output voltage or current. The
switch current signal is needed in current-mode controlled
converters and in converters with cycle-by-cycle overload
protection. Also, the switch current signal is required for
detecting impending short-circuit current runaway, and for
initiating a frequency reduction for preventing the runaway.
The voltage ramp is needed for slope compensation in
current-mode controlled converters, or for pulse-width
modulation in voltage-mode controlled converters.
At higher clock frequencies, the bandwidth limitation of the
internally-generated sawtooth-shaped current source
becomes more apparent. The degree to which ramp
bandwidth is tolerable depends on performance
requirements at narrow pulse widths. A low impedance at
the feedback pin can effectively eliminate the internallygenerated ramp effects, and an external ramp can be
readily created to attain higher performance at high
frequencies, if desired.
TIMING CAPACITOR PIN (CT)
The external timing capacitor is connected to the CT pin.
That capacitor is the only component needed for setting
the clock frequency. The frequency measured at the CT pin
is twice the frequency measured at the DRV Pin. The
maximum recommended clock frequency of the device is
1.6 MHz. At normal operation, during the rising section of
the timing-capacitor voltage, a trimmed internal current of
205 µA flows out from the CT pin and charges the capacitor.
During the falling section of the timing-capacitor voltage an
internal current of about 1.8 mA discharges the capacitor.
If the voltage at the feedback(FB) pin exceeds 1.35 V (e.g.,
due to the turnoff delay during a short-circuit at the output
of a converter using the IC), the charging current is
reduced to about 59 µA, leading to a 2.17-fold reduction in
switching frequency. The frequency reduction is useful for
preventing short-circuit current runaway.
FEEDBACK PIN (FB)
The feedback pin receives the sum of three signals: the
error signal (from the external error amplifier), the switch
current signal and a voltage ramp generated across the
terminating resistance by an internal sawtooth-shaped
January 1999 TOKO, Inc.
Page 7
TK75001
DESIGN CONSIDERATIONS
SELECTING A START-UP RESISTOR
Figure 1 shows the typical application of the TK75001 in an
off-line flyback power supply (input full-wave bridge and
capacitor not shown). The IC starts when the voltage
across the capacitor CAUX reaches the UVLO on Voltage
VIN(ON) of the IC. The starting resistor RST can be designed
as follows:
RST(MAX) = (VIN(MIN) - VCC(ON,MAX) - 2 V) / ICC(START, MAX)
(1)
At 85 Vrms line voltage, and taking into account the
specified maximum values of the UVLO on voltage and the
start-up supply current ICC(START), the maximum allowed
value of the starting resistor is:
RST(MAX) = (85
2 - 16 - 2 ) / 1.0 mA = 102.2 kΩ
(2)
A practical choice for the starting resistor is R ST = 100 kΩ.
The worst-case dissipation of the resistor appears at high
line and at the minimum VCC voltage. At 265 Vrms line
voltage and 9 V VCC, the dissipation is 2.2 W, so a 3 W
resistor should be used. Note that 1.0 mA reflects the worst
case ICC(START) at the edge of UVLO release.
considering the component tolerances, ripple, and other
second-order effects. The upper limit for VAUX is the
minimum voltage of the built-in clamp (16 V). The lower
limit for VAUX is the maximum UVLO off voltage (12.0 V). It
is prudent to choose the mean value of those two voltages
(i.e., 14.0 V), as VAUX.
COMPENSATING FOR LEAKAGE INDUCTANCE
The leakage inductance of the flyback transformer causes
a voltage overshoot at turn-off of the MOSFET. The
magnitude and duration of the overshoot depends on the
leakage inductance, the peak current at turn-offs, and the
voltage-clamping circuit employed to limit the overshoot.
The overshoot tends to increase the auxiliary voltage. The
simplest solution to reduce that increase is to add a
resistor RAUX in series with the rectifier diode D3. The
optimal value of the resistor can be calculated from the
subcircuit shown in Figure 2.
The average current flowing in RAUX is equal to the current
IAUX drawn by the IC. The following equation can be written
from the equality:
IAUX = (1 / RAUX) x ([(V1 - VD3 - VAUX) x (T1 / T)] + [(V2 - VD3 - VAUX) x (T2 / T)])
(4)
The voltage V1 can be calculated as follows:
SELECTING THE TRANSFORMER TURNS RATIO
During steady-state operations, the auxiliary supply voltage
is generated by the auxiliary winding n3 and the rectifier
diode D3. In the flyback power supply, neglecting the effect
of the leakage inductance of the transformer, the number
of turns of the auxiliary winding can be calculated from the
following equation:
V1 = (VOUT + VD2) x (n1 / n2) + [VOVERSHOOT x ( n3 / n2)]
(5)
where VOVERSHOOT is the additional voltage appearing
across the MOSFET due to the leakage inductance.
The voltage V2 can be calculated as follows:
n3 = n2 [(VAUX + VD3) / (VOUT + VD2)]
V2 = (VOUT + VD2) x ( n3 / n2)
(3)
where VD2 and VD3 are the forward voltage drops of the
output rectifier diode and the auxiliary rectifier diode. The
voltage VAUX should be selected such that it stays between
the specified worst-case upper and lower limits of the IC,
Page 8
(6)
January 1999 TOKO, Inc.
TK75001
DESIGN CONSIDERATIONS (CONT.)
T1 is the time required for the leakage inductance of the
flyback transformer to completely discharge its stored
energy into the voltage clamp. T1 can be calculated as:
D2
VIN
D3
RST
+
+
VOUT
VAUX
n2
n3
T1 = (IPK x LLEAK ) / VOVERSHOOT
CAUX
(7)
0.98 V
VCC
STABILIZING
RAMP
CT
DRV
CT
SWITCH
CURRENT
SIGNAL
OC
FB
GND
where IPK is the peak current in the MOSFET at turn-off and
LLEAK is the inductance of the flyback transformer measured
at winding n1.
0
R1
T2 is the conduction time of the output diode D2 and T is the
switching period.
From Equation 4 the resistance RAUX or the voltage VAUX
can be calculated.
FEEDBACK
VOLTAGE
RS
TL431
(a)
(b)
FIGURE 1: TK75001 IN A FLYBACK POWER SUPPLY
(a) SCHEMATIC
(b) VOLTAGE AT FEEDBACK PIN
Example: calculate the value of RAUX with the following
typical values:
IAUX
VOUT = 12 V
LLEAK = 2 µH
IAUX = 18 mA
n1 = 31
VD2 = VD3 = 1 V
VOVERSHOOT = 20 V
T2 = 2 µs
n2 = 6
IPK = 1 A
VAUX = 13.5 V
T = 5 µs
n3 = 7
VAUX
RAUX
D3
V1
CAUX
VCC
n3
+
Vn3
_
V
T1 T2
T
CT
Equations 5, 6 and 7 yield V1 = 19.7 V, V2 = 15.2 V, and
T1 = 100 ns. Substituting those values into Equation 4 and
solving for RAUX yields:
DRV
FB
GND
RAUX = 20.6 Ω
Rounding the result to the nearest 5% standard value
gives RAUX = 20 Ω.
January 1999 TOKO, Inc.
FIGURE 2: SUBCIRCUIT FOR CALCULATING THE
VALUE OF RAUX
Page 9
TK75001
APPLICATION INFORMATION
SELF-BIASED POWER SUPPLY WITH CONSTANTFREQUENCY CURRENT-MODE CONTROL
sense resistor of the converter. In voltage-mode control,
that resistor is connected to ground.
Figure 3(a) shows the TK75001 IC in the typical application:
a flyback converter with self-bias and constant-frequency
current-mode control. Figure 3(b) shows the FB Pin voltage.
In the converter, the voltage-error amplifier (a TL431 shunt
regulator IC) is located at the output side and the error
signal is transmitted to the input side through the optocoupler OC. Three signals are added together at the FB
Pin: 1)the feedback voltage that develops across the
resistor R1, 2) the switch current signal, and 3) the stabilizing
ramp. In each cycle, the MOSFET switch is turned off when
the sum of those three signals reaches 0.98 V.
In voltage-mode control, overload protection can be realized
by adding a simple circuit to the control IC, as shown in the
figure. The PNP transistor Q1, turns on and pulls up the
feedback pin when the switch current times the resistance
of the sense RS reaches the threshold set by the resistive
divider R2 and R3 and the base-emitter voltage of Q1.
VIN
VAUX
+
OC
R2
VCC
0.98 V
CT
DRV
D2
VIN
D3
PWM
RAMP
OC
R3
FB
RST
GND
+
+
Q1
VOUT
VAUX
RS
FEEDBACK
VOLTAGE
n2
n3
0
CAUX
R1
0.98 V
VCC
DRV
CT
TL431
STABILIZING
RAMP
CT
OC
SWITCH
CURRENT
SIGNAL
FB
(a)
GND
FEEDBACK
VOLTAGE
RS
(b)
0
R1
TL431
(a)
(b)
FIGURE 3: TK75001 IN A SELF-BIASED FLYBACK
CONVERTER WITH CONSTANT-FREQUENCY
VOLTAGE-MODE CONTROL
(a) SCHEMATIC
(b) VOLTAGE AT FEEDBACK PIN
POWER SUPPLY WITH CONSTANT-FREQUENCY
VOLTAGE-MODE CONTROL AND CYCLE-BY-CYCLE
CURRENT LIMIT
Voltage-mode control is free from some of the
disadvantages (e.g., subharmonic instability and noise
sensitivity) of current-mode control. It is very easy to
implement that control method with the TK75001 IC.
Figure 4(a) shows the IC in a voltage-mode-controlled
flyback converter. Figure 4(b) shows the feedback pin
voltage. The only circuit difference between current-mode
control and voltage-mode control is in the connection of
the resistor R1, that terminates the feedback pin. In currentmode control, that resistor is connected to the currentPage 10
FIGURE 4: TK75001 IN A VOLTAGE-MODECONTROLLED CONVERTER WITH ADDITIONAL
CYCLE-BY-CYCLE CURRENT LIMIT
(a) SCHEMATIC
(b) VOLTAGE AT FEEDBACK PIN
POWER SUPPLY WITH CONSTANT OFF-TIME
CURRENT-MODE CONTROL
The advantages of constant off-time current-mode control
over constant-frequency current-mode control are: 1) there
is no need for a stabilizing ramp, 2) the converter is free
from subharmonic instability (i.e., there is no need for
slope compensation), and 3) the line voltage variation is
automatically canceled in buck-derived converters (e.g.,
the forward converter). Figure 5 shows the implementation
of that control method. As can be seen, a transistor Q1
must be added to the controller. Figure 6 shows the timingpin and feedback pin voltages for the TK75001. The
transistor Q1 keeps the timing pin at ground potential
during the on-time of the switch. Timing begins when the
drive output returns to low and Q1 is turned off. The off-time
for typical charge and discharge currents and peak and
valley voltages is:
tOFF = CT x 14 kΩ.
January 1999 TOKO, Inc.
TK75001
APPLICATION INFORMATION (CONT.)
TK75001 IN NON-ISOLATED APPLICATIONS
VIN
VAUX
+
VOUT
VCC
CT
Q1
VAUX
DRV
CT
Figure 7 shows a buck-boost converter with a negative
input voltage and a positive output voltage, controlled by
the TK75001. The Error Amplifier is a TL431 shunt regulator,
and a PNP transistor provides interface between the
TL431 and the control IC.
OC
FB
VOUT (+)
GND
RS
R1
TL431
VCC
CT
DRV
FB
TL431
GND
FIGURE 5: TK75001 IN A FORWARD CONVERTER
WITH CONSTANT OFF-TIME CURRENT-MODE
CONTROL
VIN (-)
FIGURE 7: NON-ISOLATED NEGATIVE-TO-POSITIVE
CONVERTER
3.2 V
CT
CT
1.1 V
0
0.98 V
FEEDBACK VOLTAGE LEVEL
FB
FB
FIGURE 6: TIMING PIN AND FEEDBACK PIN
VOLTAGES WITH CONSTANT OFF-TIME CURRENTMODE CONTROL
January 1999 TOKO, Inc.
Page 11
TK75001
APPLICATION INFORMATION (CONT.)
TK75001 OFF-LINE APPLICATION EXAMPLE
Figure 8 shows an off-line, universal input, 12 W power supply. The TK75001 is the controller IC for a flyback converter
with self-bias and constant-frequency, current-mode control. The TK75001 drives the MOSFET directly to switch the
flyback transformer. Feedback is accomplished by means of a TL431, configured as a secondary side error amplifier and
voltage reference, driving an opto-coupler for isolation.
RB155
1 mH
RM4
1.5 mH
0.2 A
+
1M
0.25 W
22 µF
400 V
2A
0.001 µF
400 V
24 k
0.5 W
FMMTA42
0.1 µF
400 V
FERRITE
BEAD
6CWF20F
1M
0.25 W
RM6-N67
AL250
16 Ω
KCO17L
100
0.5 W
FMMTA42
n3
n2
0.01 µF
85-265 VAC
47-440 Hz
620
BYV26CPH
+
+
+
n1
1N4148
FMMT2222A
330 pF
100 V
330 µF
16 V
+
82µF
25V
330 µF
16 V
12 V
1A
n1 = 31, AWG28
n2 = 6, triple insulated, AWG24
n3 = 7, AWG34
82 µF
25 V
470
VCC
CT
CNY17-2
TK75001
15
IRFRC20
4.75 k
1%
DRV
220 pF
FB
0.047 µF
1.8 k
470
220 pF
50 V
GND
220
4.7 k
0.01 µF
1.2
0.25 W
TL431
1.24 k
1%
FIGURE 8: OFF-LINE, UNIVERSAL INPUT, 12-WATT POWER SUPPLY
Page 12
January 1999 TOKO, Inc.
TK75001
PACKAGE OUTLINE
Marking Information
DIP-8
5
8
Marking
TK75001
Marking
75001
6.4
Lot Number
Country of Origin
4
1
+ 0.3
3.3
+ 0.3
0.5 min
3.8
3.3
9.5
0.25
+ 0.15
- 0.05
e1
7.62
0~
15
e
2.54
0.46
+ 0.15
- 0.05
0.25
M
Dimensions are shown in millimeters
Tolerance: x.x = 0.2 mm (unless otherwise specified)
Toko America, Inc. Headquarters
1250 Feehanville Drive, Mount Prospect, Illinois 60056
Tel: (847) 297-0070
Fax: (847) 699-7864
TOKO AMERICA REGIONAL OFFICES
Midwest Regional Office
Toko America, Inc.
1250 Feehanville Drive
Mount Prospect, IL 60056
Tel: (847) 297-0070
Fax: (847) 699-7864
Western Regional Office
Toko America, Inc.
2480 North First Street , Suite 260
San Jose, CA 95131
Tel: (408) 432-8281
Fax: (408) 943-9790
Eastern Regional Office
Toko America, Inc.
107 Mill Plain Road
Danbury, CT 06811
Tel: (203) 748-6871
Fax: (203) 797-1223
Semiconductor Technical Support
Toko Design Center
4755 Forge Road
Colorado Springs, CO 80907
Tel: (719) 528-2200
Fax: (719) 528-2375
Visit our Internet site at http://www.tokoam.com
The information furnished by TOKO, Inc. is believed to be accurate and reliable. However, TOKO reserves the right to make changes or improvements in the design, specification or manufacture of its
products without further notice. TOKO does not assume any liability arising from the application or use of any product or circuit described herein, nor for any infringements of patents or other rights of
third parties which may result from the use of its products. No license is granted by implication or otherwise under any patent or patent rights of TOKO, Inc.
January 1999 TOKO, Inc.
© 1999 Toko, Inc.
All Rights Reserved
Page 13
IC-120-TK75001
0798O0.0K
Printed in the USA