TK75050 SMART MOSFET DRIVER FEATURES ■ 20 ns Rise and Fall Times into 1000 pF ■ 550 µA Standby Current Consumption ■ Undervoltage Lockout Combined with First Pulse Wake-Up Feature * ■ Cycle-by-Cycle Current Limiting ■ Current Sense Voltage Spike Cancellation when Used with Gate Charge Recovery Circuit * ■ Thermal Overload Protection ■ TTL/CMOS Compatible Input APPLICATIONS ■ ■ ■ ■ Driving of Power MOSFETs and IGBTs Switch Mode Power Supplies Step Motor Drivers Solenoid Drivers DESCRIPTION The TK75050 is a non-inverting buffer to drive high power insulated gate transistors (e.g., MOSFETs and IGBTs). The output can source or sink 2 A into a 10,000 pF equivalent load. The IC features built-in cycle-by-cycle current limiting. Its Undervoltage Lockout (UVLO) circuit is combined with a First Pulse Wake-up Feature*. The chip has thermal overload protection. Using the IC in the Gate Charge Recovery* application, the switching spike developed across the current sense resistor practically becomes negligible. Due to its low standby current and first-pulse wake-up feature, the device can be used in selfbiased power supplies. The IC's high-speed cycle-bycycle current limiting capability eliminates the short circuit runaway problem which characterizes most currentcontrolled converters. The IC is well suited to provide supplementary overload protection in voltage-controlled converters, too. The TK75050 is available in the widely used 8-pin DIP package. TK75050 PGND/CS INPUT GND GND GND GND OUTPUT VCC 0 7505 BLOCK DIAGRAM *Toko proprietary feature: See "Application Information" section. UVLO VCC 11/10 V STARTUP R Q EN BIAS S ORDERING INFORMATION EN INPUT TK75050D Tape/Reel Code Temperature Code PACKAGE CODE EXTENDED TEMP. RANGE TAPE/REEL CODE D: DIP-8 I: -40 TO +85 C TL: Tape Left January 1999 TOKO, Inc. OUTPUT 1.6/1.0 V OVERLOAD R Q S PGND/CS GND CURRENT OVERLOAD T 155/80 °C 1.0/0.9 V THERMAL OVERLOAD Page 1 TK75050 ABSOLUTE MAXIMUM RATINGS Supply Voltage (Low Impedance Source) ................ 14 V Power Dissipation TK75050D (Note 1) .............. 825 mW Storage Temperature Range ................... -55 to +150 °C Operating Temperature Range ...................-20 to +70 °C Extended Temperature Range ................... -40 to +85 °C Junction Temperature .......................................... 150 °C Lead Soldering Temperature (10 s) ..................... 235 °C TK75050 ELECTRICAL CHARACTERISTICS Test conditions: VCC = 12 V, TA = Tj = Full Operating Temperature Range, DC Test Setup 1, unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 55 0 1000 µA POWER SUPPLY SECTION ICC(STBY) Supply Current (Standby), (Note 2) VIN = 0 V Before Wake-Up ICC(L) Supply Current (Output LOW) VIN = 0 V After Wake-Up 17 26 mA ICC(H) Supply Current (Output HIGH) VIN = 2.4 V After Wake-up 14 18 mA ICC(SD) Suppy Current (Output SHUTDOWN) Current or Thermal Overload 19 24 mA IPGND/CS PGND/CS Current (Output LOW) VIN = 0 V After Wake-up 4 10 mA UNDERVOLTAGE LOCKOUT SECTION VCC(ON) Suppy Voltage (UVLO HIGH Threshold) VCC Sweeps Upward 10.4 11.0 11.4 V VCC(OFF) Suppy Voltage (UVLO LOW Threshold) VCC Sweeps Downward 9.3 10.0 10.4 V 0.6 1.0 INPUT SECTION VIN(L) Input Voltage (LOW Threshold) VIN(H) Input Voltage (HIGH Threshold) IIN(L) Input Current (LOW) VIN = 0 V IIN(H) Input Current (HIGH) VIN = 2.4 V VIN(WU) Input Voltage (Wake-up Threshold) 1.6 -250 V 2.1 -100 V µA 10 25 µA 1.25 2.25 V ISINK = 50 mA 0.25 0.5 V ISINK = 1.0 A 3.0 3.8 V 0.5 OUTPUT SECTION VOUT(L) Output Voltage (LOW) VOUT(H) Output Voltage (HIGH) IOUT(MAX) Maximum Output Sink or Source Current, (Note 3) CL = 10,000 pF IOUT(STBY) Standby Output Pull-down Current VCC = 9 V Page 2 ISOURCE = 50 mA 9.7 10.5 V ISOURCE = 1.0 A 8.0 9.5 V 2.0 A VOUT = 8 V 1 2.5 mA VOUT = 2 V 0.3 0.7 mA January 1999 TOKO, Inc. TK75050 TK75050 ELECTRICAL CHARACTERISTICS (CONT.) Test conditions: VCC = 12 V, TA = Tj = Full Operating Temperature Range, DC Test Setup 1, unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS THERMAL OVERLOAD PROTECTION SECTION Tj(OFF) Junction Temperature, Thermal Overload Shutdown Threshold, (Note 3) Tj(ON) Junction Temperature, Turn Back to Temperature Sweeps Downward Normal Mode Threshold, (Note 3) in Thermal Shutdown Mode Temperature Sweeps Upward in Normal Mode 150 °C 80 °C CURRENT OVERLOAD PROTECTION SECTION VCL Current Sense Voltage, Current Limit Threshold VCS Sweeps Upward, TA = 25 ° C, DC Test Setup 2 VCL(HYST) Current Sense Voltage, Current Limit Hysteresis, (Note 3) DC Test Setup 2 100 0.8 0.95 1.1 V mV SWITCHING CHARACTERISTICS tDR Delay Time (RISE) CL = 1000 pF, AC Test Setup 3 20 45 ns tR Rise Time CL = 1000 pF, AC Test Setup 3 20 40 ns tDF Delay Time (FALL) CL = 1000 pF, AC Test Setup 3 20 45 ns tF Fall Time CL = 1000 pF, AC Test Setup 3 20 40 ns tD(COS) Delay Time, Current Overload Shutdown, (Note 3) CL = 1000 pF, ∆VCS = 200 mV, AC Test Setup 3 120 ns Note 1: Power dissipation is 825 mW when mounted. Derate at 6.6 mW/°C for operation above 25°C. Note 2: Conditions for "wake-up": either 1) VIN exceeds VIN(H), stays above VIN(L), and VCC passes VCC(ON) or 2) VCC exceeds VCC(ON), stays above VCC(OFF), and VIN exceeds VIN(H). Conditions for "standby": either 1) VCC never exceeds VCC(ON) or 2) VCC drops below VCC(OFF) or 3) VIN never exceeds VIN(H). Note 3: Guaranteed by design; not 100% tested. January 1999 TOKO, Inc. Page 3 TK75050 TEST CIRCUITS DC TEST SETUP 1 + DC TEST SETUP 2 + + ISINK 100 nF 10 µF VCC 10000 µF + + 10 µF - VCC 100 nF VCC SW2 IN VCC OUT IN PGND/CS + GND VIN PGND/CS + SW1 VIN - + GND VCS 10 - - ISOURCE Note: SW1 and SW2 are open by default. To avoid excessive dissipation, they are exclusively closed only for less than 100 ms to measure the appropriate output voltages VOUT(H) and VOUT(L) at specified currents ISOURCE and ISINK, respectively. AC TEST SETUP 3 + + +TRIG -TRIG VCC 100 nF 10 µF VCC ZOOM IN IN SYNCH VIN t CL 1000 pF GND Ch A PULSE GENERATOR 1.0 V 1.6 V OUT PGND/CS ZOOM IN 90 % 10 % 90 % 10 % Ch B TRIG tDF tDR t tF tR OSCILLOSCOPE AC TEST SETUP 4 + + VCC 100 nF 10 µF VCC VIN (t) f = 10 kHz D = 1:1 Level = TTL IN VOUT (t) OUT PGND/CS TRIG IN VIN (t) tD = 10 µs T = 100 µs CL 1000 pF GND VCS (t) VCS = ZOOM IN 50 mV 200 mV VCL = 1 V VCS ADJ Ch A +TRIG t OSCILLOSCOPE SYNCH OUT t +TRIG Ch B TRIG IN PULSE GENERATOR1 t VCS (t) tW = 10 µs ZOOM IN VOUT(H) 90 % Ch C 10 Ω f = 10 kHz D = 1:10 Level = ADJ. t VOUT (t) t VOUT(L) tD(COS) PULSE GENERATOR2 RS ≤ 50 Ω Page 4 January 1999 TOKO, Inc. TK75050 TYPICAL PERFORMANCE CHARACTERISTICS 700 20 18 16 ICC(H) 14 ICC(AVG) (mA) ICC(L) ICC(STBY) (µA) VCC = 12 V 500 VCC = 10 V 400 TA = 25 °C 16 14 TA = 125 °C 12 300 12 VCC = 5 V 10 0.01 200 10 -25 25 75 -25 125 25 75 125 0.1 1 10 100 TA (°C) TA (°C) FREQUENCY (kHz) SUPPLY CURRENT VS. SUPPLY VOLTAGE UVLO THRESHOLD VS. TEMPERATURE INPUT THRESHOLD VS. TEMPERATURE 11.5 TA = 25 °C NO LOAD CONNECTED 1000 2.0 UVLO THRESHOLD (V) VCC = 12 V 15 ACTIVE MODE 10 5 INPUT THRESHOLD (V) ICC (mA) VCC = 12 V NO LOAD CONNECTED 600 18 ICC (mA) 20 NO LOAD CONNECTED VCC = 12 V NO LOAD CONNECTED 20 AVERAGE SUPPLY CURRENT VS. FREQUENCY STANDBY CURRENT VS. TEMPERATURE SUPPLY CURRENT VS. TEMPERATURE VCC(ON) 11.0 10.5 VCC(OFF) 10.0 VIN(H) 1.6 1.2 VIN(L) SLEEP MODE 0 9.5 2 6 10 14 0.8 -25 25 75 125 -25 25 75 VCC (V) TA (°C) TA (°C) OUTPUT VOLTAGE VS. TEMPERATURE CURRENT LIMIT THRESHOLD VS. TEMPERATURE RISE AND FALL TIME VS. TEMPERATURE 10.8 1.2 28 VCC = 12 V NO LOAD CONNECTED VCC = 12 V CL = 1000 pF VCC = 12 V VIN = VIN(H) 10.6 125 10.4 TIME (ns) 1.0 VCL (V) VOUT (V) VOUT(H) 10.2 0.8 24 tF 20 VOUT(L) tR 0.2 0.0 0.6 -25 25 TA (°C) January 1999 TOKO, Inc. 75 125 15 -25 25 TA (°C) 75 125 -25 25 75 125 TA (°C) Page 5 TK75050 TYPICAL PERFORMANCE CHARACTERISTICS (CONT.) PROPOGATION DELAY VS. TEMPERATURE CURRENT OVERLOAD SHUTDOWN DELAY VS. TEMPERATURE 250 VCC = 12 V CL = 1000 pF 32 28 tDF 24 tDR 20 16 VCC = 12 V CL = 1000 pF 200 ∆VCS = 50 mV 150 100 ∆VCS = 200 mV ∆VCS = 100 mV 50 0 -25 25 TA (°C) Page 6 PROPOGATION DELAY (ns) PROPOGATION DELAY (ns) 36 75 125 -25 25 75 125 TA (°C) January 1999 TOKO, Inc. TK75050 PIN DESCRIPTION SUPPLY VOLTAGE PIN (VCC) This pin is connected to the supply voltage. Regardless of the state of the other pins, the IC is always in a low-current standby mode when the supply voltage is below the lower threshold of the undervoltage lockout circuit. The IC enters normal mode when two conditions are met simultaneously: 1) the supply voltage exceeds the upper threshold of the undervoltage lockout circuit, and 2) a "first" pulse arrives at the input. That first pulse "wakes up" the IC ( i.e., it enables the highspeed internal circuitry). The First Pulse Wake-Up is a proprietary feature of theTK75050. The feature is proprietary, but use is granted for use with the IC. That feature is indispensable in off-line self-biased powersupply applications where the start-up current is provided by a large-value resistor connected between the rectified line and the IC (see Figure 1). Without the First Pulse Wake-up, the starting current would be equal to the normal supply current, which is prohibitively large for a self-biased start. 1.3 V. The hysteresis ensures that noise riding on the input signal does not cause spurious response at the output. POWER GROUND/CURRENT SENSE PIN (PGND/CS) This pin has two distinct functions: 1) it provides a separate, fully floating return path for the turnoff drive current of the output stage and, thus, reduces the internal noise of the IC; 2) by connecting the pin to a current-sense resistor, the IC acts as a fast cycle-by-cycle current limiter. When the voltage between the power-ground pin (PGND/ CS) and the signal-ground pin (GND) exceeds the 0.95 V current-limit threshold, the drive signal is terminated for the remainder of the time while the input signal is high. Once the input signal returned to zero, the latch that stored the information about the presence of the overcurrent is reset, and the IC is ready to acquire another overcurrent event in the next cycle. GROUND PIN (GND) This pin provides ground return connection for the smallsignal portion of the IC. The return of the output stage is not connected here, but to the floating power GND pin. OUTPUT PIN This pin drives the external MOSFET using a totem pole output stage. The peak drive source or sink current is typically 2 A into a 10,000 pF equivalent load. The UVLO circuity ensures that the high-level output voltage will never be less than about 7 V. In standby mode, the output stage is equivalent to a pull-down resistor of about 3 kΩ value, eliminating the need for an external gate to source resistor. Normally, there is no need to add a Schottky diode between the output and ground. In applications, however, with heavy capacitive load located far from the IC or when the IC drives a transformer, the Schottky diode may become necessary. INPUT PIN The input pin receives the signal to be buffered. The incoming signal is processed by a comparator with a 600 mV hysteresis centered around a threshold of about January 1999 TOKO, Inc. Page 7 TK75050 APPLICATION INFORMATION START-UP Figure 1 shows the application of the TK75050 smart MOSFET driver in a self-biased power supply. granted for use with the TK75050. For a detailed description and application information of the Gate Charge Recovery technique, see the Toko application note "Application Considerations for a Smart Five-Pin MOSFET/IGBT Driver with High-Speed Current-Limit Capability." VIN + VAUX IN RF VCC VCC TK75050 CF OUT OUT + 0.95 V IN PWM CONTROLLER GND PGND/CS + VCS (t) VCS(t) CF IS CONNECTED TO GND RCS 0.95 V VCS(t) CF IS CONNECTED TO PGND/CS FIGURE 1: TK75050 IN A SELF-BIASED POWER SUPPLY Figure 2 shows the typical waveforms during start-up. (a) (b) FIGURE 3: CYCLE-BY-CYCLE CURRENT LIMIT WITH THE TK75050 (a) SCHEMATIC (b) WAVEFORMS PWM ENABLE BOOTSTRAP REGULATION BEGINS UVLO UPPER THRESHOLD MAIN OVERLOAD PROTECTION IN VOLTAGEMODE-CONTROLLED CONVERTERS UVLO LOWER THRESHOLD Figure 4 shows the TK75050 in a voltage-mode-controlled flyback converter. In this application example, the IC provides the main overload protection. VCC (t) VUVLO (t) VIN (t) UVLO CONDITION FIRST PULSE CONDITION VIN DRIVER “WAKES UP” + VIN (t) & VOUT (t) +12 V FIGURE 2: WAVEFORMS DURING START-UP FEEDBACK CYCLE-BY-CYCLE CURRENT LIMIT Figure 3(a) shows how to use the TK75050 as a highspeed cycle-by-cycle current limiter. Figure 3(b) shows the waveforms. Note that the preferred connection for the bottom terminal of the filter capacitor CF is to the PGND/CS pin and not to the GND pin. By connecting CF to the PGND/ CS pin, the capacitive feedthrough of the drive signal that would appear as a leading-edge spike in the current-sense waveform is completely eliminated. This technique, called "Gate Charge Recovery" is patented by Toko, Inc., but is Page 8 VOLTAGE-MODE PWM CONTROLLER FIGURE 4: TK75050 IN A VOLTAGE-MODECONTROLLED CONVERTER January 1999 TOKO, Inc. TK75050 APPLICATION INFORMATION (CONT.) VIN ADDITIONAL OVERLOAD PROTECTION IN PEAKCURRENT-CONTROLLED CONVERTERS Figure 5 shows the TK75050 in a current-mode-controlled forward converter, with optically isolated feedback. In this application the TK75050 helps to achieve a tightly controlled current-limit-characteristic. A tight current limit cannot usually be achieved with only current-mode control due to the presence of the stabilizing ramp. The lack of the stabilizing ensures that the knee current (i.e., the output current where the limiting begins) is only slightly lower than the short-circuit current. The difference between the knee current and the short-circuit current is about one-half of the ripple current in the filter inductor. If a stabilizing ramp were added to the current-sense signal, the difference would be significantly higher. VIN +12 V TK75050 - + + + FEEDBACK FIGURE 6: TK75050 IN A CONVERTER WITH AVERAGE CURRENT CONTROL + +12 V FLOATING DRIVE WITH OVERLOAD PROTECTION OC TK75050 CURRENT-MODE PWM CONTROLLER The TK75050 can be used as a driver and current limiter for a floating power switch. Figure 7 shows the IC in a buck converter with transformer-isolated drive. VIN FIGURE 5: TK75050 IN A PEAK-CURRENTCONTROLLED CONVERTER + TK75050 ADDITIONAL OVERLOAD PROTECTION IN AVERAGECURRENT-CONTROLLED CONVERTERS In converters with average current control the peak current information is lost and the response of the current-control loop slows down. The speed of the current-control loop may not be sufficient to provide effective protection against sudden overload or saturation of an inductor or transformer. Figure 6 shows an average-current-controlled boost converter where the TK75050 provides additional fast overload protection. January 1999 TOKO, Inc. FIGURE 7: TK75050 AS A FLOATING DRIVER IN A BUCK CONVERTER DEMO BOARD The purpose of the board is to demonstrate the high-speed current-limit capability of Toko's TK75050 smart MOSFET driver. In the board a 2-A/500 V MOSFET switch is turned on directly (i.e., without any series impedance) into a DCbus with up to 400 V, at a frequency of 30 kHz. By removing the short across a 3.3 µH inductor in series with the MOSFET, it is also possible to investigate the effect of the wiring inductance between the switch and the load. In Page 9 TK75050 APPLICATION INFORMATION (CONT.) addition to the short-circuit protection, the board also illustrates how to use the IC for driving and protecting a floating switch. CIRCUIT SCHEMATIC Figure 8 shows the circuit schematic. The operation is as follows: U1, a 5-pin PWM IC (TK75001) generates a 30 kHz square-wave signal, with about 15 V peak-to-peak magnitude and 44% duty ratio. That square-wave signal is connected to the primary winding of a pulse transformer T1 through a coupling capacitor C9 and a small series resistor R11. A voltagedoubler comprising C3, C4, D3 and D4 rectifies the transformed square wave appearing across the secondary winding of the transformer, generating a floating supply voltage of about 12 V for the MOSFET driver IC U2 (TK75050). A drive signal is derived for U2 from the voltage across the diode D4 with the help of the resistive divider R3 and R2. The output of U2 (pin 3) is connected to the gate of the MOSFET Q1 through a 150 ohm resistor R4 and a parallel diode D5. The current of the MOSFET switch is sensed by resistor R5. D6 and D7 protect the PGND/CS pin (pin 1) of U2 from excessive voltage; D8 and D9 prevent the voltages of pins 3 and 1 from swinging below ground by more than 0.3 V. The MOSFET Q1 is connected to a DC-bus through a small inductor L1. That inductor represents the inductance of a wire connection to a load, which is at a distance of approximately 1 meter from the MOSFET. By placing a short across jumper JP1, we can emulate the case when the free-wheeling diode in a buck or boost converter fails. If the inductor L1 is not shorted, a clamp comprising D10, C6 and R7 limits the drain voltage excursion of Q1 to about 60 V above the bus voltage. A test loop is provided for clamp-on type current probes to monitor the current in the MOSFET Q1. Test points TP1 through TP4 are available for measuring the dc bus voltage and the voltage across Q1. The DC-bus is generated by rectifying the line voltage with a bridge rectifier (in the case of 230 VRMS line) or with a voltage doubler (in the case of 115 VRMS line, when jumper JP2 is shorted). Alternatively, a DC source of not more than 400 V can be connected to the line terminals. Notes: (1) Leave JP2 open if you connect more than 250 V dc voltage to the line terminals, otherwise the excess voltage across C7 or C8 can lead to failure of the capacitor. (2) Never operate the circuit from 230 VRMS line with the jumper JP2 shorted. In such a case excess bus voltage will develop that will destroy capacitor C7 and C8 and transistor Q1. TEST LOOP FOR CURRENT PROBE TP4 TEST POINT FOR VOLTAGE OBSERVATION +15 V D15 D5 TP5 Q1 R10 1k R4 D11 1N5226B (3.3 V) D2 C2 1.5 n CT FB GND VCC + C1 C3 1 C9 1 D3 R11 10 HS1 OUT GND IN PGND/CS C4 D1 C6 JP2 1k 1W C8 T1 R8 1M D14 C5 + 0.1 n2 n1 DRV VCC R9 1M R7 R5 0.47 1W D8 GND C7 D10 10 GND U1 TK75001 R1 115 OR 230 Vrms L1 150 U2 TK75050 F1 1A SLOW D12 JP1 D9 D4 D7 D6 R6 10 TP3 TEST POINT FOR SCOPE GND CLIP R2 TP1 TP2 D13 TEST POINTS FOR VCC MEASUREMENT (MAX. 400 VDC) Q1: IRF820 (IR PREFERRED) R3 HS1: HS121-ND (DIGI-KEY, AAVID) 10 k D1, D2, D5, D8, D9: 1N5817 22 k D3, D4, D6, D7: 1N4148 D10: BYV26C D12-15: 1N4005 C1, C4: 10 , 25 V C6: 15 n, 630 V(e.g. ECQ-E6153KF, PANASONIC) C7, C8: 2.2 , 250 V (PANASONIC SU SERIES, RADIAL, ECE-A2EU2R2) L1: 3.3. , 4 A (e.g. R622LY-3R3M, TOKO) T1: RM5/i, 3E1 (PHILIPS), n1 = 40, n2 = 46, SINGLE LAYER WINDINGS, WIRE SIZE TO FILL THE BOBBIN MYLAR INSULATION BETWEEN LAYERS, FOR 1 kV BETWEEN PRIMARY AND SECONDARY JP2: OPEN AT 230 V, SHORTED AT 115 V. FIGURE 8: CIRCUIT SCHEMATIC Page 10 January 1999 TOKO, Inc. TK75050 APPLICATION INFORMATION (CONT.) Figures 9 and 10 show the measured voltages across Q1 (top trace) and the currents in Q1 (bottom trace). Figure 9 shows the wave forms when there is no inductor in series with Q1 (i.e., L1 is shorted). Figure 10 shows the waveforms when there is an inductor in series with Q1 (i.e., L1 is not shorted). The vertical scales are 100 V/div. (top trace) and 1 A/div (bottom trace). The horizontal scales are 25 ns/div. As can be seen, the peak currents stay below 2.5 A (Figure 9) or 2.8 A (Figure 10). Those numbers correspond to 25% or 40% overshoots above the nominal current-limit threshold of 2 A. Both figures show that the IC shuts off the MOSFET completely in less than 50 ns after the current passed the 2 A threshold. The measured average DC current consumption at a bus voltage of 400 V and a switching frequency of 30 kHz is 4.3 mA when L1 is shorted (Figure 9) and 5.3 mA when L1 is not shorted (Figure 10). SAFETY CONSIDERATIONS/LIABILITY DISCLAIMER Dangerous voltages are present in the demo board. Extreme caution must be used when using and testing the circuit. Only trained personnel, experienced in working with high voltages and power, should operate it. Use an isolating transformer between the line and the circuit if any grounded instrument (including the 20 V auxiliary supply for the square-wave generator at the primary side of transformer T1) is to be connected to the board. Note: Although the two windings of transformer T1 are isolated from each other, the transformer is not designed to provide safety isolation between those windings. Toko, Inc. disclaims any and all liability arising from use or misuse of the demo board described herein. 400V 0V 2A 0A 25ns/div. FIGURE 9 400V 0V 2A 0A 25ns/div. FIGURE 10 January 1999 TOKO, Inc. Page 11 TK75050 PACKAGE OUTLINE Marking Information DIP-8 5 8 Marking TK75050 Marking 75050 6.4 Lot Number Country of Origin 4 1 3.3 + 0.3 0.5 min 3.8 + 0.3 3.3 9.5 0.25 + 0.15 - 0.05 e1 7.62 0~ 15 e 2.54 0.46 + 0.15 - 0.05 M 0.25 Dimensions are shown in millimeters Tolerance: x.x = 0.2 mm (unless otherwise specified) Toko America, Inc. Headquarters 1250 Feehanville Drive, Mount Prospect, Illinois 60056 Tel: (847) 297-0070 Fax: (847) 699-7864 TOKO AMERICA REGIONAL OFFICES Midwest Regional Office Toko America, Inc. 1250 Feehanville Drive Mount Prospect, IL 60056 Tel: (847) 297-0070 Fax: (847) 699-7864 Western Regional Office Toko America, Inc. 2480 North First Street , Suite 260 San Jose, CA 95131 Tel: (408) 432-8281 Fax: (408) 943-9790 Eastern Regional Office Toko America, Inc. 107 Mill Plain Road Danbury, CT 06811 Tel: (203) 748-6871 Fax: (203) 797-1223 Semiconductor Technical Support Toko Design Center 4755 Forge Road Colorado Springs, CO 80907 Tel: (719) 528-2200 Fax: (719) 528-2375 Visit our Internet site at http://www.tokoam.com The information furnished by TOKO, Inc. is believed to be accurate and reliable. However, TOKO reserves the right to make changes or improvements in the design, specification or manufacture of its products without further notice. TOKO does not assume any liability arising from the application or use of any product or circuit described herein, nor for any infringements of patents or other rights of third parties which may result from the use of its products. No license is granted by implication or otherwise under any patent or patent rights of TOKO, Inc. Page 12 © 1999 Toko, Inc. All Rights Reserved January 1999 TOKO, Inc. IC-164-TK75050 0798O0.0K Printed in the USA