T R I Q U I N T S E M I C O N D U C T O R, I N C . TQ8017 Input Buffers D0..15 D0..15 16 x 16 Crosspoint Switch Matrix Output Buffers O0..15 O0..15 1.25 Gigabit/sec 16x16 Digital PECL Crosspoint Switch 64 CONFIGURE (R2) Sixteen 4-Bit Latches RESET LOAD IA0..3 4 (R1) Sixteen 4-Bit Addressable Output Select Latches SWITCHING PRODUCTS 64 VCC VEE OA0..3 4 4:16 Decoder TQ8017 GND The TQ8017 is a non-blocking 16 x 16 digital crosspoint switch capable of data rates greater than 1.25 Gigabits per second per port. Utilizing a fully differential internal data path and PECL I/O, the TQ8017 offers a high data rate with exceptional signal fidelity. The symmetrical switching and noise rejection characteristics inherent in differential logic result in low jitter and signal skew. The TQ8017 is ideally suited for digital video, data communications and telecommunication switching applications. The non-blocking architecture uses 16 fully independent 16:1 multiplexers (see diagram on page 2), allowing each output port to be independently programmed to any input port. The switch is configured by sequentially loading each multiplexer’s 4-bit program latch (OA0:3) with the desired input port address (IA0:3) and enabling the LOAD pin. When complete, the CONFIGURE pin is strobed and all new configurations are simultaneously transferred into the switch multiplexers. Data integrity is maintained on all unchanged data paths. Features • >20 Gb/s aggregate BW • 1.25 Gb/s/port NRZ data rate • Non-blocking architecture • 500 ps delay match • Differential PECL-level data I/O; Selectable CMOS/TTLlevel control inputs • Low jitter and signal skew • Fully differential data path • Double-buffered configuration latches • 132-pin MQFP package • Single +5V supply Electrical Characteristics Min Max Units Jitter 150 ps pk-pk Channel Propagation Delay 2000 ps Ch-to-Ch Propagation Delay Skew 500 ps Data Rate/port Typical output waveform with all channels driven 1.25 Gb/s Applications • Telecom/Datacom Switching • Hubs and Routers • Video Switching For additional information and latest specifications, see our website: www.triquint.com 1 TQ8017 Figure 1. TQ8017 Architecture 16 X 1-BIT MULTIPLEXER . 16 X 1-BIT MULTIPLEXER DATA IN 0 (D0) . . . . . DATA OUT 15 (O15) Input Buffers . . DATA OUT 0 (O0) . . . . DATA IN 15 (D15) CONFIGURE RESET LOAD 4:16 4 DECODE OUTPUT SELECT ADDRESS (OA0:3) Configuration Register 5 Program Register 4 INPUT ADDRESS (IA0:3) Table 1.AbsoluteMaximumRatings5 Symbol Absolute Max. Rating Notes TSTOR Storage Temperature –65° C to +150° C TCH Junction (Channel) Temperature –65° C to +150° C TC Case Temperature Under Bias –65° C to +125° C 2 VCC Supply Voltage 0 V to +7 V 3 VTT Load Termination Supply Voltage VCC to 0 V 4 VIN Voltage Applied to Any PECL Input; Continuous IIN Current Into Any PECL Input; Continuous –1.0 mA to +1.0 mA VIN Voltage Applied to Any TTL/CMOS Input; Continuous –0.5 V to VCC +0.5 V IIN Current Into Any TTL/CMOS Input; Continuous VOUT Voltage Applied to Any PECL Output IOUT Current From Any PECL Output; Continuous –40 mA PD Power Dissipation per Output POUT = (GND – VOUT) x IOUT 50 mW Notes: 1. 2. 3. 4. 5. 2 Parameter 1 GND –0.5 V to VCC +0.5 V –1.0 mA to +1.0 mA GND –0.5 V to VCC +0.5 V For die applications. TC is measured at case top. All voltages specified with respect to GND, defined as 0V. Subject to IOUT and power dissipation limitations. Absolute maximum ratings, as detailed in this table, are the ratings beyond which the device's performance may be impaired and/or permanent damage to the device may occur. For additional information and latest specifications, see our website: www.triquint.com 4 TQ8017 Table 2. Recommended Operating Conditions4 Symbol Parameter Min TC Case Operating Temperature VCC Supply Voltage VTT Load Termination Supply Voltage RLOAD Output Termination Load Resistance ΘJC Thermal Resistance Junction to Case Max Units Notes 1,3 0 85 °C 4.5 5.5 V VCC – 2.0 V 2 50 Ω 2 7 °C/W TC measured at case top. Use of adequate heatsink is required. The VTT and RLOAD combination is subject to maximum output current and power restrictions. Contact the Factory for extended temperature range applications. Functionality and/or adherence to electrical specifications is not implied when the device is subjected to conditions that exceed, singularly or in combination, the operating range specified. SWITCHING PRODUCTS Notes: 1. 2. 3. 4. Typ Table 3. Pin Descriptions Signal Name/Level Description D0 to D15, ND0 to ND15 Data input true and complement. Differential PECL Differential data input ports. O0 to O15, NO0 to NO15 Data output true and complement. Differential PECL Differential data output ports. IA0:3 Input address. CMOS/TTL Input port selection address that is written into the selected output port program latches (OA0:3). IA3 IA2 IA1 IA0 Input port 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 : : : : : 1 1 1 1 15 OA0:3 Output select address. CMOS/TTL Output port selection address. Selects the output port program latches to which the input port selection address (IA0:3) is written. OA3 OA2 OA1 OA0 Output port 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 : : : : : 1 1 1 1 15 LOAD CMOS/TTL Enables the selected output port program latches while set ‘high’. Latches the data when set to a 'low' level. CONFIGURE CMOS/TTL Transfers the program latches data to the configuration latches and implements the switch changes while set ‘high’. Latches the data when set to a ‘low’ level. RESET CMOS/TTL Configures the switch into Broadcast or Pass-Through mode, overwriting existing configurations. Broadcast mode: All output ports are connected to data input port 0. This mode is selected by applying a RESET “high” pulse with CONFIGURE held “low." Pass-through mode: I0 is connected to O0, I1 to O1, etc. This mode is selected by applying a RESET “high” pulse with CONFIGURE held “high." CNTRL LVL Input level control. GND/Open Selects the input levels for the input address (IA0:3), output address (OA0:3), CONFIGURE, LOAD and RESET inputs. Inputs are configured for TTL when tied to GND and CMOS when left unconnected. For additional information and latest specifications, see our website: www.triquint.com 3 TQ8017 Table 4. DC Characteristics1,2 – Within recommended operating conditions, unless otherwise indicated. Symbol Parameter Min Max Units V Test Cond. VIH PECL Input Voltage High VCC –1.1 VCC – 0.5 VIL PECL Input Voltage Low VTT VCC – 1.5 V IIH PECL Input Current High +30 µA VIH = VCC – 0.7 V IIL PECL Input Current Low µA VIL = VCC – 2.0 V –30 VICM PECL Input Common Mode Voltage VCC – 1.5 VIDIF PECL Input Differential Voltage (pk-pk) VIH CMOS/TTL Input Voltage High VIL CMOS/TTL Input Voltage Low 0/0 IIH IIL VOCM PECL Output Common Mode VODIF PECL Output Differential Voltage VOH PECL Output Voltage High VCC –1.0 VCC – 0.6 VOL PECL Output Voltage Low VTT VCC – 1.6 V IOH PECL Output Current High 20 27 mA IOL PECL Output Current Low 0 ICC Power Supply Current (+) Notes VCC –1.1 V 400 1200 mV 3.5/2.0 VCC/VCC V 2 1.5/0.8 V 2 CMOS/TTL Input Current High +200 µA VIH = VCC 2 CMOS/TTL Input Current Low –100 µA VIL = 0 V 2 VCC –1.1 V VCC – 1.5 600 mV V 8 mA 970 mA Notes: 1. Test conditions unless otherwise indicated: VTT = VCC – 2.0 V, RLOAD = 50 Ω to VTT. 2. Input level is selected by the CNTRL LVL input. Tying CNTRL LVL to GND selects TTL levels, leaving CNTRL LVL OPEN selects CMOS levels. Table 5. AC Characteristics1 – Within recommended operating conditions, unless otherwise indicated. Symbol Parameter Min Typ Maximum Data Rate/Port Max Units Notes 1.25 Gb/s 1,2 Jitter 150 ps pk-pk 1 T1 Channel Propagation Delay 2000 ps 3 T2 Ch-to-Ch Propagation Delay Skew 500 ps T3 CONFIG to Data Out (Oi) Delay T4 LOAD Pulse Width T5 CONFIG Pulse Width 7 ns T6 IAi to LOAD High Setup Time 0 ns T7 LOAD to IAi Low Hold Time 3 ns T8 OAi to LOAD High Setup Time 0 ns 5 7 ns ns T9 LOAD to OAi Low Hold Time 3 ns T10 Load ↑ to CONFIG ↑ 0 ns T11 RESET Pulse Width 10 TR,F Output Rise or Fall Time ns 250 400 ps 3 Notes: 1. Test conditions: VCC = 5.0 V; VTT = 3.0 V, RLOAD = 50 Ω to VTT; PECL inputs: VIH = 3.9 V; VIL = 3.5 V; CMOS inputs: VIH = 3.5 V, VIL = 1.5 V; PECL outputs: VOH > 4.0 V, VOL < 3.4 V; PECL inputs rise and fall times < 1 ns; CMOS inputs rise and fall times < 20 ns. A bit error rate of 1E–13 BER or better for 223–1PRBS pattern, jitter and rise/fall times are guaranteed through characterization. 2. 1.2 Gb/s Non-Return-Zero (NRZ) data equivalent to 600 MHz clock signal. 3. Rise and fall times are measured at the 20% and 80% points of the transition from VOL max to VOL min. 4 For additional information and latest specifications, see our website: www.triquint.com TQ8017 Figure 2. Timing Diagram – Switch Configuration RESET Input Address SWITCHING PRODUCTS Output Address LOAD T4 T10 CONFIGURE T8 T7 Data1 In DA T5 T9 T6 DB DE DD DC T1 Data1 Out DF DG T3 OA OB OC OE OD OF OG Invalid Data Out Note:1 No data loss on nchanged data paths Notes: 1. No data loss on unchanged paths Figure 3. Timing Diagram – Reset RESET T11 T3 CONFIGURE Output Data Broadcast Pass-through Notes: 1. LOAD input must remain LOW to insure correct programming of the switch. 2. “Broadcast” is defined as data input 0 to all data outputs (0…15). 3. “Pass-through” is defined as data input 0 to data output 0, data input 1 to data output 1, etc. For additional information and latest specifications, see our website: www.triquint.com 5 TQ8017 Typical Performance Data Figure 4. Data Eye Closure 12 8 6 Figure 5. Data Eye Closure Time & Amplitude vs Data Rate (typical) 4 100 2 90 0 0.5 0.7 0.9 1.1 1.3 1.5 ➤ 1.7 ➤ Data Eye Period (%) 10 80 Data Rate (Gb/s) % Recoverable Data Eye Period – (P-P Jitter) x 100 / Period Percent (%) 70 60 Inner Eye Amplitude V (inner eye) x 100 / V (inner eye @ 400 Mb/s) 50 40 30 20 Figure 6. RMS Jitter vs. Data Rate (typical) 10 0 55 0.5 0.7 0.9 45 Jitter (ps) 40 35 30 25 20 15 10 0.5 0.7 0.9 1.1 1.3 1.5 1.7 Data Rate (Gb/s) 6 1.1 1.3 Data Rate (Gb/s) 50 For additional information and latest specifications, see our website: www.triquint.com 1.5 1.7 TQ8017 Top View 132-Pin Package NOTE: unmarked pins connected. Note: All Unmarked pins areare notnot connected. ND11 D11 VCC ND10 D10 VCC ND9 D9 VCC ND8 D8 VCC ND7 D7 VCC GND GND ND6 D6 VCC ND5 D5 VCC ND4 D4 VCC ND3 D3 VCC ND2 D2 SWITCHING PRODUCTS Pin 1 Index 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VCC VCC VCC NO1 O1 VCC NO0 O0 VCC IADD3 IADD2 VCC IADD1 IADD0 GND GND VCC CONFIGURE LOAD VCC OADD3 OADD2 VCC OADD1 OADD0 VCC D0 ND0 VCC D1 ND1 NO11 O11 VCC NO10 O10 VCC NO9 O9 VCC NO8 O8 VCC NO7 O7 GND GND VCC NO6 O6 VCC NO5 O5 VCC NO4 O4 VCC NO3 O3 VCC NO2 O2 ➤ 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 VCC CNTRL LVL VCC VCC O12 NO12 VCC O13 NO13 VCC O14 NO14 VCC O15 NO15 VCC RESET GND ND15 D15 VCC ND14 D14 VCC ND13 D13 VCC ND12 D12 VCC VCC VCC Figure 5. Package Pinout For additional information and latest specifications, see our website: www.triquint.com 7 TQ8017 Figure 6. Mechanical Dimensions Bottom View Top View PIN 1 INDEX CL PIN 1 INDEX 17 117 18 0.010 PIN WIDTH TYP. TQ8017-Q A XXXX YYWW 116 A TQ8017-Q 0.400 0.540 0.467 REF. SQ. ± .003 ± .003 0.550 ± .003 50 XXXX YYWW 84 51 LOT CODE DATE CODE CL 83 Notes: 1. Part is symmetrical about the center axes. 2. Centerline bisects center pin in both directions. 3. See pad detail below. Section A-A 0.140 ± .005 0.170 ± .010 0.025 TYP. 0.015 CL SEATING PLANE 0.010 0.020 MIN. 0.512 0.053 CL PAD LAYOUT DETAIL Ordering Information TQ8017-Q 1.25 Gb/s 16x16 PECL Crosspoint Switch Additional Information For latest specifications, additional product information, worldwide sales and distribution locations, and information about TriQuint: Web: www.triquint.com Email: [email protected] Tel: (503) 615-9000 Fax: (503) 615-8900 For technical questions and additional information on specific applications: Email: [email protected] The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or omissions. TriQuint assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems. Copyright © 1997 TriQuint Semiconductor, Inc. All rights reserved. Revision 1.1.A November 1997 8 For additional information and latest specifications, see our website: www.triquint.com