T R I Q U I N T S E M I C O N D U C T O R , I N C . TQ8004 IN0 + OUT0 NOUT0 - 4 + 4:1 VTT NIN0 IN1 4:1 + OUT1 NOUT1 - 4:1 + OUT2 NOUT2 - 4 + 2.7 Gbit/sec 3.3V 4x4 Digital Crosspoint Switch NIN1 IN2 4 + Features • 2.7 Gb/s port data bandwidth VTT NIN2 + IN3 + OUT3 NOUT3 - 4 4:1 VTT NIN3 - SWITCHING PRODUCTS VTT 2 2 2 2 IADD OADD LOAD CONFIG 2 2 CONTROL • Single 3.3V power supply • Fully differential data path • Non-blocking architecture • Differential PECL I/O TTL control inputs • On-chip input termination • Low jitter and channel to channel signal skew • Double configuration latches • Small 28-pin TSSOP package The TQ8004 is a non-blocking 4 X 4 digital crosspoint switch capable of data rates greater than 2.7 Gigabits per second per port. Utilizing a fully differential data path from input to output, the TQ8004 offers a high data rate with exceptional fidelity. The symmetrical switching and noise rejection characteristics inherent in differential logic result in low jitter, low crosstalk and minimum signal skew. The TQ8004 is ideal for high speed data switching applications, as well as high fidelity buffering or protection switching. Applications • Telecom/Datacom/Video switching • Fanout buffering • Protection Switching The non-blocking architecture uses 4 fully independent 4:1 multiplexers, allowing each input port to be independently programmed to any output port. For additional information and latest specifications, see our website: www.triquint.com 1 TQ8004 Circuit Description Data inputs The 4 input channels are differential PECL compatible, referenced to VDD = 3.3V power supply (LVPECL). All LVPECL inputs have on-chip 50 Ohm termination to VTT. For AC coupled designs an internal bias generator can be used to supply the VTT voltage. An on-chip voltage divider generates the VTT voltage at VDD-1.3V with an impedance of 800 Ohms. Due to the high impedance of the internal VTT source it is suited only for AC coupled input schemes. For DC coupled designs VTT needs to be externally supplied, nominally at VDD-2.0V for LVPECL systems. Note that the external source needs to be able to sink current. If any inputs are unused, terminate one side of any unused input pair to GND through a 500 Ohm or smaller resistor. This will prevent unwanted oscillations. Data outputs The 4 output channels are differential PECL and are designed to be terminated through 50 Ohm to VDD2.0V. Unused outputs can be left unterminated. Control inputs The control inputs are TTL compatible. Unconnected inputs will default to a logic HI level. configuration latch, stores the current input configuration which is applied to the switch core. The use of two sets of program storage latches allows for a new set of input configurations to be loaded simultaneously without disturbing the existing configuration. The address of the desired output is applied to OADD(0:1). The input address is applied to IADD(0:1). The input address defines which input port connects to the selected output port. The new configuration is loaded into the program latches by asserting the LOAD signal high and is latched when LOAD is de-asserted. The process is repeated for each new output port configuration. Only the output ports which are to receive a new input port configuration need to be programmed in this manner. The new configurations are not applied to the switch core at this time. After all of the new configurations have been loaded into the program latches, the CONFIGURE input is asserted high and the data in the program latches is loaded into the configuration latches. The data is latched when CONFIGURE is de-asserted. Data integrity is maintained on output ports not receiving a new configuration The switch core receives the new configuration immediately following the assertion of CONFIGURE. The integrity of the data on any re-configured output port is unknown for a period tdcf from the time CONFIGURE is asserted. Switch configuration The switch is configured by programming each output to a specific input. Each of the 4 output channels have two sets of program store latches. The first, or program latch, stores a new input configuration prior to application to the switch core. The second, or 2 The LOAD and CONFIGURE inputs can be asserted simultaneously. In this mode, the new configuration will be applied to the switch when LOAD is asserted. For additional information and latest specifications, see our website: www.triquint.com TQ8004 Summary of the IADD(0:1) and OADD(0:1): IADD1 IADD0 Input OADD1 OADD0 Output 0 IN0 0 0 OUT0 0 1 IN1 0 1 OUT1 1 0 IN2 1 0 OUT2 1 1 IN3 1 1 OUT3 SWITCHING PRODUCTS 0 Specifications Specifications subject to change without notice Table 1. Absolute Maximum Ratings4 Parameter Storage Temperature Junction Temperature Case Temperature w/bias Supply Voltage Voltage to any input Voltage to any output Current to any LVTTL input Current to any LVPECL input Current from any output Power Dissipation of output Condition Symbol Minimum (1) (2) (2) (2) (2) (2) (2) (3) Tstore TCH TC VDD Vin Vout Iin Iin Iout Pout –65 –65 0 0 –0.5 –0.5 –1.0 –65 Nominal Maximum Unit 150 150 100 5.5 VDD + 0.5 VDD + 0.5 1.0 65 40.0 50.0 °C °C °C V V V mA mA mA mW Notes: 1. Tc is measured at case top. 2. All voltages are measured with respect to GND (0V) and are continuous. 3. Pout = (VDD – Vout ) x Iout . 4. Absolute maximum ratings, as detailed in this table, are the ratings beyond which the device’s performance may be impaired and/or permanent damage to the device may occur. For additional information and latest specifications, see our website: www.triquint.com 3 TQ8004 Table 2. Recommended Operating Conditions 3 Symbol Parameter Min Typ Max Units Notes TA VDD IDD Operating Temperature Supply Voltage Current Positive Supply 0 3.14 — — 85 3.47 300 °C V 1 VTT RLOAD Load Termination Supply Voltage Output Termination Load Resistance ΘJA Thermal Resistance Junction to Ambient VDD – 2.0 50 mA V Ω 2 2 °C/W 40 Notes: 1. Package thermal pad to be soldered to PCB. 2. The VTT and RLOAD combination is subject to maximum output current and power restrictions. Note that the value shown is for DC coupled LVPECL I/O. 3. Functionality and/or adherence to electrical specifications is not implied when the device is subjected to conditions that exceed, singularly or in combination, the operating range specified. Table 3. DC Characteristics—PECL I/O 3 Parameter Condition Symbol Minimum Nominal Maximum Unit VICOM VIDIFF VOCOM VODIFF RIN CIN COUT VESD VDD – 1500 600 VDD-1500 1200 VDD – 1100 2400 VDD – 1100 2400 — — 1000 — — — — 50 2.5 2.5 — — — — mV mV mV mV Ohm pF pF V Symbol Minimum Nominal Maximum Unit Input HIGH voltage VIH 2.0 — VDD V Input LOW voltage Input HIGH current VIL IIH 0 — — — 0.8 200 V uA IIL CIN VESD –400 — 1000 –200 2.5 — — — — uA pF V Input common mode voltage range Input differential voltage (pk-pk) Output common mode voltage range Output differential voltage (pk-pk) Input termination resistance Input capacitance Output capacitance ESD breakdown rating (1) (1,2) Table 4. DC Characteristics—TTL Inputs3 Parameter Condition Input LOW current Input capacitance ESD breakdown rating VIH(MAX) VIL(MIN) Notes (Tables 3 and 4): 1. Differential Input Peak-Peak = 2| Vin - NVin | 2. RLOAD = 50 ohms to VTT = VDD – 2.0V. 3. Specifications apply over recommended operating ranges. 4 For additional information and latest specifications, see our website: www.triquint.com TQ8004 Table 5. AC Characteristics Parameter Condition Symbol Minimum Nominal Maximum Unit Maximum Data Rate/port Minimum Input pulse width Rise/Fall time 20-80% (1) Tpw Tr/f 2.7 370 — — — — 150 Gb/s ps ps Channel Propagation Delay Ch-to-Ch Prop. Delay Skew (1) (1) Tpd Tskew — — 100 1.0 ns ps Jitter (pk-pk) (2) Tjitter — 25 — ps SWITCHING PRODUCTS Notes: 1. Measured at crossing point of true and complement 2. Crossing of (On) – (NOn) measured with 223 – 1 PRBS, measured over extended time. Figure 1. Timing Diagram Input Address [IADD0:1] Valid Address Output Address [OADD0:1] Valid Address thar tsar[IADD] tsar[OADD] Tpwl tldl LOAD Tldh Tpwc CONFIGURE Tdcf IN(0:3) OUT(0:3) Data Not Valid ** Data Valid tpd ** Data remains valid on outputs with unchanged configurations Table 6. Timing Specifications Symbol Parameter Minimum Maximum tsar thar Address to Load Set-up time Address to Load Hold Time 2 2 ns ns tpwl tldh Min. Load pulse width Load to Configure delay 5 0 ns ns tldl tpwc tdcf Configure to Load delay Min. Configure pulse width Configure to Data Valid 2 5 ns ns ns 20 For additional information and latest specifications, see our website: www.triquint.com Unit 5 TQ8004 Table 7. TQ8004 Pin Descriptions Signal Type Pin Number Description Control and Configuration CONFIGURE TTL Input 17 LOAD 16 Active High. Enables transfer of data from program latches to configuration latches. Active High. Enables program latches to accept new input address based upon which output is selected using OADD inputs. Latches address data on de-assertion. 27 28 Input address LSB Input address MSB 14 13 Output address LSB Output address MSB 19,18 True and Complement Differential PECL Data Out Addressed by OADD(0:1) = 00 True and Complement DPECL Data Out Addressed by OADD(0:1) = 01 True and Complement DPECL Data Out Addressed by OADD(0:1) = 10 True and Complement DPECL Data Out Addressed by OADD(0:1) = 11 TTL Input Input Address Control IADD0 TTL Input IADD1 TTL Input Output Address Control OADD0 TTL Input OADD1 TTL Input Output Ports OUT0,NOUT0 DPECL Output OUT1,NOUT1 DPECL Output 21,20 OUT2,NOUT2 DPECL Output 23,22 OUT3,NOUT3 DPECL Output 25,24 Input Ports IN0,NIN0 DPECL Input 10,11 IN1,NIN1 DPECL Input 8,9 IN2,NIN2 DPECL Input 6,7 IN3,NIN3 DPECL Input 4,5 Power Pins Signal VTT VDD GND Description Input Termination Supply +3.3V Power Supply Ground Supply 6 True and Complement DPECL Data In. Addressed by IADD(O:1) = 00 True and Complement DPECL Data In Addressed by IADD(O:1) = 01 True and Complement DPECL Data In Addressed by IADD(O:1) = 10 True and Complement DPECL Data In Addressed by IADD(O:1) = 11 Pin Number 2 1, 15, 26, Package Down Paddle (required) 3, 12 For additional information and latest specifications, see our website: www.triquint.com TQ8004 SWITCHING PRODUCTS Figure 2. Typical Output Eye with 223-1 PRBS data at 2.7 Gb/s For additional information and latest specifications, see our website: www.triquint.com 7 TQ8004 Figure 3. TSSOP Mechanical Dimensions 1.00 1.00 DIA. C B 3 2 1 B E/2 1.00 MIN NOM MAX 1.1262 1.10 .0254 .1500 0.95 .8500 1.0500 .1900 .3000 .1900 .2500 .0900 .2000 .0900 .1600 9.6000 9.8000 4.3000 4.4000 4.5000 .6500 .6500 .6500 6.4000 .5000 .6000 .7000 28 5.5000 5.00 3.0000 3.0100 A A1 A2 b b1 c c1 D E1 e E L N P P1 Note: All dimensions in millimeters (mm). C L E E1 SEE DETAIL "A" TOP VIEW END VIEW (b) b1 b A2 WITH PLATING A aaa e A1 D SIDE VIEW C c1 (c) SEATING PLANE BASE METAL Moisture Level Rating 3 per SECTION "B-B" o JEDEC Standard J-STD-020A (14 ) P 0.25 P1 (OC) L (1.00) EXPOSED PAD VIEW Ordering Information TQ8004 DETAIL 'A' (14 ) o (VIEW ROTATED 90 C.W.) o 2.7Gbit/sec 4x4 Crosspoint Switch Additional Information For latest specifications, additional product information, worldwide sales and distribution locations, and information about TriQuint: Web: www.triquint.com Email: [email protected] Tel: (503) 615-9000 Fax: (503) 615-8900 For technical questions and additional information on specific applications: Email: [email protected] The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or omissions. TriQuint assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems. Copyright © 2001 TriQuint Semiconductor, Inc. All rights reserved. Revision 1.0.A May 2001 8 For additional information and latest specifications, see our website: www.triquint.com