TRIQUINT TQ8034

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S E M I C O N D U C T O R , I N C .
TQ8034
PRELIMINARY DATA SHEET
68
Output
Buffers
OUT0:33
68
34 6-Bit Configuration Latches
CONFIGURE
LOAD
MODE(1)
1.6 Gbit/sec
3.3V 34x34 Digital
Crosspoint Switch
Features
SWITCHING
PRODUCTS
34 x 34
Crosspoint
Switch Matrix
Input
Buffers
IN0:33
• >1.6 Gb/s port data bandwidth
>50 Gb/s aggregate bandwidth
34 6-Bit Program Latches
IADD0:5
• 3.3V power supply
MODE(0)
Output Address Select
TQ8034
0:33
OADD0:33
0:5
6:34 Decoder
34
• Fully differential data path for
superior signal fidelity
• Non-blocking architecture
• Full broadcast and multi-cast
capability
The TQ8034 is a non-blocking 34 X 34 digital crosspoint switch capable of data
rates greater than 1.6 Gigabits per second per port. Utilizing a fully differential
data path from input to output, the TQ8034 offers a high data rate with
exceptional fidelity. The symmetrical switching and noise rejection
characteristics inherent in differential logic result in low jitter, low crosstalk and
minimum signal skew. The TQ8034 is ideally suited for gigabit data and HDTV
switching applications.
• Differential LVPECL I/O with
TTL control
• On-chip 50 Ohm LVPECL input
termination
• Low jitter and signal skew
• Two-stage configuration register
• Multiple programming modes
• 304-pin BGA package
The non-blocking architecture uses 34 fully independent 34:1 multiplexers,
allowing each output port to be independently programmed to any input port.
The TQ8034 supports full broadcast and multicast operation, with
programming modes optimized for these applications.
Applications
Four methods are provided for configuration of the switch. Two modes are
used for programming one input to one output at a time and the other two are
for programming one input to multiple outputs (1 to 34) at once. In all modes,
data integrity is maintained on all unchanged data paths.
• Hubs and routers
• Telecom/datacom switching
including Fibre Channel and
Gigabit Ethernet
• Video switching including
High-Definition TV (HDTV)
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1
TQ8034
PRELIMINARY DATA SHEET
Circuit Description
Configuration Modes
Data inputs
There are two primary modes for configuring the
TQ8034; Sequential and Multicast. Sequential mode is
used to program one input to one output per LOAD
cycle and Multicast is used to program one input to
multiple outputs per LOAD cycle. Both modes allow
either a user defined input port assignment or an
internal default input port assignment.
The 34 input channels are differential LVPECL
compatible with on-chip 50-Ohm termination to VTT.
Unused input-pairs should have one side connected to
GND through a 500-Ohm or smaller resistor to prevent
unwanted oscillations. See figure 6 for examples of DC
and AC coupled termination.
Data outputs
The 34 output channels are differential LVPECL
compatible and designed to be terminated through 50Ohms to VDD-2.0V. Unused outputs can be left unterminated to save power. See figure 6 for examples of
DC and AC coupled termination.
Control Inputs
The control inputs are TTL compatible. Unconnected
inputs will default to logic HI levels.
Configuration Storage
Each of the 34 output channels has two sets of
configuration storage registers. The registers are built
using transparent latches which are controlled by the
LOAD and CONFIGURE inputs. The first set of latches,
or program register, stores a new input configuration
prior to application to the switch core. The second set
of latches, or configuration register, stores the
configuration that is applied to the switch core. The
use of two sets of program storage latches allows new
configurations to be loaded without disturbing the
existing configuration. The two-stage architecture also
allows all of the new configurations to be applied to the
switch core simultaneously.
2
The default input port assignment for each output port
is the output's corresponding input port (IN0 to OUT0,
IN1 to OUT1, etc.). This default configuration is
referred to as pass-through.
All programming modes result in the loading of a new
configuration into the appropriate output port
PROGRAM (first stage) registers. Changing the
contents of the PROGRAM registers does not change
the configuration of the switch core. The configuration
of the switch core is updated following the assertion of
CONFIGURE. CONFIGURE is a global input that
simultaneously transfers the contents of all PROGRAM
registers into their second stage CONFIGURATION
registers. The data is latched into the CONFIGURATION
register when CONFIGURE is de-asserted.
The integrity of the data flowing through the switch
core is maintained during the load cycle. The integrity
of the data flowing through the switch core to outputs
that do not receive a new configuration is also
maintained during the configure cycle. Data integrity is
unknown on output ports receiving a new input port
configuration for a time Tdcf after assertion of
CONFIGURE (see timing diagrams).
The CONFIGURE inputs can be tied to a "HI" level or
asserted simultaneously with LOAD. In this case, the
new configuration will be applied to the switch
multiplexer when LOAD is asserted.
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TQ8034
PRELIMINARY DATA SHEET
The configuration modes are defined by the MODE0
and MODE1 control inputs.
MODE0 MODE1
configuration is loaded into the PROGRAM register by
asserting the LOAD input high and is latched when
LOAD is de-asserted.
Switch Configuration Mode
0
0
Sequential Mode: User defined input port assignment
0
1
Sequential Mode: Default input port assignment
1
0
Multicast Mode: User defined input port assignment
1
1
Multicast Mode: Default input port assignment
Multicast Program Mode
Sequential programming allows for a single input to
output port assignment per LOAD cycle. Any number
of port assignments can be made with repeated LOAD
cycles prior to assertion of CONFIGURE.
User defined input port assignment
(MODE0=0, MODE1=0)
User defined input port assignment Sequential
programming uses the address inputs IADD(0:5) and
the lower 6 bits of OADD(0:33).
To program, apply the desired output port address to
the address inputs OADD(0:5) and the desired input
port address to the address inputs IADD(0:5). The
input address defines which input port connects to the
selected output port. The new configuration is loaded
into the PROGRAM register by asserting the LOAD
input high and is latched when LOAD is de-asserted.
Default input port assignment (MODE0=0, MODE1=1)
Default input port assignment Sequential programming
uses the same lower 6 bits of OADD(0:33) and ignores
the IADD(0:5) inputs.
SWITCHING
PRODUCTS
Sequential Program Mode
Multicast programming allows any combination of
output ports to be configured to a single input port in a
single LOAD cycle.
User defined input port assignment
(MODE0=1, MODE1=0)
User defined input port assignment Multicast
programming uses input addresses IADD(0:5) and
output addresses OADD(0:33).
To program, apply the desired input port address to
IADD(0:5) and the OADD(0:33) bits which correspond
to the desired output ports. For example, to program
input 1 to output ports 1, 2 and 5; apply "000001" to
IADD(0:5) and apply "00..0100110" to OADD(0:33). The
new configuration is loaded into the program latches
by asserting the LOAD signal high and is latched when
LOAD is de-asserted. This process is continued for
each set of outputs to be programmed to a unique
input. Data is then transferred to the CONFIGURATION
latches upon assertion of CONFIGURE input.
Default input port assignment (MODE0=1, MODE1=1)
Default input port assignment Multicast programming
uses the OADD(0:33) inputs and ignores the IADD(05)
inputs. Apply the desired output ports to be configured
to inputs OADD(0:33). Upon assertion of LOAD, each
output port selected will be programed to its
corresponding input port.
To program, apply the desired output port address to
the address inputs OADD(0:5). The default
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3
TQ8034
PRELIMINARY DATA SHEET
Specifications
Specifications subject to change without notice
Table 1. Absolute Maximum Ratings4
Parameter
Condition
Symbol
Minimum
Storage Temperature
Junction Temperature
Case Temperature w/bias
Supply Voltage
Voltage to any input
Voltage to any output
(1)
(2)
(2)
(2)
Tstore
TCH
TC
VDD
Vin
Vout
Current to any TTL input
Current from any output
Power Dissipation of output
(2)
(2)
(3)
Iin
Iout
Pout
Electrostatic Discharge
Nominal
Maximum
Unit
–65
–65
0
0
–0.5
–0.5
150
150
100
5.5
VDD + 0.5
VDD + 0.5
°C
°C
°C
V
V
V
–1.0
1.0
40.0
50.0
mA
mA
mW
2000
V
ESD
Notes: 1. Tc is measured at case top.
2. All voltages are measured with respect to GND (0V) and are continuous.
3. Pout = (VDD – Vout ) x Iout .
4. Absolute maximum ratings, as detailed in this table, are the ratings beyond which the device’s performance may be impaired
and/or permanent damage to the device may occur.
Table 2. Recommended Operating Conditions 7
Symbol
Parameter
Min
Typ
Max
Units
Notes
TC
Case Operating Temperature
0
VDD
IDDcore
IDDoutput
VTT
RLOAD
PDcore
PDoutput
PDinputAC
Supply Voltage
Positive Supply Current Switch Core
Positive Supply Current Per Output Pair
Load Termination Supply Voltage
Output Termination Load Resistance
Power Dissipation Switch Core
Dissipation per terminated output pair
Dissipation per AC coupled input pair
3.14
—
100
°C
1
—
2.25
30
VDD – 2.0
50
7.4
32
2.8
3.47
V
A
mA
V
Ω
W
mW
mW
PDinputDC
Θ JC
Dissipation per DC coupled input pair
Thermal Resistance Junction to Case
9.8
2.2
mW
°C/W
2
3
3
4
5
6
Notes: 1. TC measured at case top. Use of adequate heatsink is required.
2. IDDoutput is additive to IDDcore for each terminated differential output pair (true and complement).
3. The VTT and R LOAD combination is subject to maximum output current and power restrictions.
4. PDoutput is additive to PDcore for each terminated differential output pair (true and complement).
5. PDinputAC is additive to PDcore for each AC-coupled differential input pair (true and complement).
6. PDinputDC is additive to PDcore for each DC-coupled differential input pair (true and complement).
7. Functionality and/or adherence to electrical specifications is not implied when the device is subjected to conditions that exceed,
singularly or in combination, the operating range specified.
4
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TQ8034
PRELIMINARY DATA SHEET
Table 3. DC Characteristics—PECL I/O 3
Parameter
Condition
Input common mode voltage range
Input differential voltage (pk-pk)
Output common mode voltage range
Output differential voltage (pk-pk)
Input termination resistance
(1)
(2)
Symbol
Minimum
Nominal
Maximum
Unit
VICOM
VIDIFF
VOCOM
VODIFF
RIN
VDD – 1500
600
VDD-1500
1200
—
—
—
—
50
VDD – 1100
2400
VDD – 1100
2400
mV
mV
mV
mV
Ohm
Symbol
Minimum
Nominal
Maximum
Unit
VIH
VIL
2.0
0
—
—
VDD+1.8
0.8
V
V
IIH
IIL
CIN
—
–400
—
—
–200
—
200
—
TBD
uA
uA
pF
Parameter
Condition
Input HIGH voltage
Input LOW voltage
Input HIGH current
Input LOW current
Input capacitance
VIH(MAX)
VIL(MIN)
SWITCHING
PRODUCTS
Table 4. DC Characteristics—TTL Inputs3
Notes (Tables 3 and 4):
1. Differential inputs.
2. RLOAD = 50 ohms to VTT = VDD – 2.0V.
3. Specifications apply over recommended operating ranges.
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5
TQ8034
PRELIMINARY DATA SHEET
Table 5. AC Characteristics
Parameter
Condition
Maximum Data Rate/port
Minimum Input pulse width
Rise/Fall time
Channel Propagation Delay
IN(0:31)
IN(32:33)
Ch-to-Ch Prop. Delay Skew OUT(0:31)
OUT(0:33) Jitter
Symbol
Minimum
(1)
20-80%
Tpw
Tr/f
1.6
625
—
(1)
Tpd
(1)
(1)
(2)
Tpd
Tskew
Tjitter
Nominal
Maximum
Unit
—
—
—
220
Gb/s
ps
ps
—
—
—
—
—
70
2.0
1.75
500
150
ns
ns
ps
ps
Notes: 1. Measured at crossing point of true and complement
2. Crossing of (On) – (NOn) measured with 223 – 1 PRBS, measured over extended time.
Table 6. Timing Specifications
Symbol
6
Parameter
Minimum
Maximum
Unit
tsar [IADD],[OADD]
thar [IADD],[OADD]
tpwl
Address to Load Set-up Time
Address to Load Hold Time
Load Pulse Width
3
3
7
ns
ns
ns
tldh
tldl
Load to Configure Delay
Configure to Load Delay
0
ns
ns
tpwc
tdcf
Configure Pulse Width
Configure to Data Valid
7
30
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ns
ns
TQ8034
PRELIMINARY DATA SHEET
Figure 1. Sequential Configuration (User Defined Input Address; MODE0 = 0, MODE1 = 0)
Input Address
[IADD0:5]
Valid Address
Output Address
[OADD0:5]
Valid Address
tthar
tsar[IADD]
tpwl
tldl
SWITCHING
PRODUCTS
tsar[OADD]
LOAD
tldh
tpwc
CONFIG
tdcf
IN(0:33)
1234
123456789012
12345
1234
123456789012
12345
123456789012
1234
12345 Data Valid
OUT(0:33)
tpd
** Data remains valid on outputs with unchanged configuration
Figure 2. Sequential Configuration (Default Input Address; MODE0 = 0, MODE1 = 1)
Output Address
[OADD0:5]
Output Selected for Pass-through
tthar
tsar[OADD]
tpwl
tldl
LOAD
tldh
tpwc
CONFIG
tdcf
IN(0:33)
123456
12345678901234567
1234567
123456
12345678901234567
1234567
123456
12345678901234567
1234567
123456
1234567
12345678901234567
123456
12345678901234567
1234567
OUT(0:33)
Data Valid
tpd
** Data remains valid on outputs with unchanged configuration
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7
TQ8034
PRELIMINARY DATA SHEET
Figure 3. Multicast Configuration (User Defined Input Address; MODE0 = 1, MODE1 = 0)
Input Address
[IADD0:5]
Output Address
[OADD0:33]
Valid Address
Outputs Selected for Multicast
thar
tsar[IADD]
tsar[OADD]
tpwl
tldl
LOAD
tldh
tpwc
CONFIG
tdcf
IN(0:33)
12345
12345678901
1234
12345
12345678901
1234
12345
12345678901
1234
12345
12345678901
1234
OUT(0:33)
Data Valid
tpd
** Data remains valid on outputs with unchanged configuration
Figure 4. Multicast Configuration (Default Input Address; MODE0 = 1, MODE1 = 1)
Output Address
[OADD0:33]
Outputs Selected for Pass-through
tthar
tsar[OADD]
tpwl
tldl
LOAD
tldh
tpwc
CONFIG
tdcf
IN(0:33)
123456
12345678901234567
123456
123456
12345678901234567
123456
123456
12345678901234567
123456
123456
123456
12345678901234567
123456
12345678901234567
123456
OUT(0:33)
Data Valid
tpd
** Data remains valid on outputs with unchanged configuration
8
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TQ8034
PRELIMINARY DATA SHEET
Figure 5. TQ8034 Pinout —Top View
Inputs
IN0
GND
GND
NIN3
IN5
GND
NIN6
IN32
NINO
NIN1
IN3
NIN4
NIN5
IN7
NIN32
IN1
NIN2
IN4
IN6
VTT
VCC
IN2
VTT
VCC
VCC
GND
NOUT2
NOUT1
GND
VCC
GND
OUT2
OUT1
GND
VCC
NOUT3
VCC
NOUT0
OUT5
OUT4
VCC
VCC
OUT3
VCC
OUT7
NOUT5
NOUT4
GND
NOUT7
OUT6
VCC
VCC
NOUT9
OUT9
OUT8
NOUT6
IADD4
GND
NOUT10
OUT10
NOUT8
OADD2 OADD4 OADD5
GND
NOUT11 OUT11
GND
OUT0
GND
GND
IN8
NIN9
NIN10
NIN7
NIN8
IN10
IN11
VTT
IN9
VCC
VTT
NIN11
GND
NIN12
IN14
IN12
NIN13
VCC
IN13
VCC
VTT
TQ8034
VCC
NOUT13 OUT13 NOUT12 OUT12
NOUT16 OUT16
GND
OUT22
OUT23
VCC
OUT25 NOUT26
GND
VCC
GND
VCC
GND
LOAD
VCC
CONFIG
IADD1
IADD0
IADD2
IADD5
IADD3
OADD0
GND
VCC
OADD1 OADD3
GND
OADD6 OADD7
GND
OADD10
OADD15 OADD14
OADD18
304-pin BGA
Top View
VCC
OUT24
GND
OADD17 OADD16
OADD21 OADD20 OADD19
OADD23 OADD22
GND
OADD28 OADD25 OADD24
GND
VCC
OADD31 OADD29 OADD27 OADD26
VCC
VCC
NOUT25 OUT27
VCC
OUT29
NOUT27 OUT28
NOUT29
VCC
NOUT30
VCC
VCC
OUT33
GND
VCC
OUT30
GND
VCC
GND
NOUT31 NOUT32
VCC
GND
OUT31
GND
VTT
VCC
NIN29
NIN31
NIN30
IN29
NIN33
IN31
IN30
NIN28
IN33
GND
GND
IN28
NOUT33
VCC
IN24
VTT
VCC
NIN19
VTT
NIN26
NIN24
IN23
IN22
NIN20
IN19
NIN27
IN26
IN25
NIN23
NIN22
NIN21
IN20
NIN18
NIN17
IN27
GND
NIN25
GND
GND
IN21
GND
IN18
VTT
VCC
VTT
GND
OADD32
VCC
NOUT28
OUT32
IN15
VCC
NOUT22 NOUT23 NOUT24 OUT26
GND
VCC
OADD11 OADD12 OADD13
OUT19 NOUT19 OUT20 NOUT20
OUT21 NOUT21
GND
OADD8 OADD9
OUT17 NOUT17 OUT18 NOUT18
GND
NIN15
VCC
NOUT15 OUT15 NOUT14 OUT14
GND
NIN14
VCC
OADD33 OADD30
MODE0
VCC
GND
MODE1
NIN16
GND
VCC
GND
IN17
IN16
GND
VCC
VCC
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
Configure
Outputs
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
SWITCHING
PRODUCTS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
= NC (Do Not Connect)
Inputs
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9
TQ8034
PRELIMINARY DATA SHEET
Table 7. Pin Descriptions
Signal
Type
Package Grid Ref
Control and Configuration
CONFIGURE
TTL Input
D22
LOAD
C23
TTL Input
MODE0
TTL Input
MODE1
TTL Input
Input Address Control
IADD0
TTL Input
IADD1
TTL Input
IADD2
TTL Input
IADD3
TTL Input
IADD4
TTL Input
IADD5
TTL Input
Output Address Control
OADD0
TTL Input
OADD1
TTL Input
OADD2
TTL Input
OADD3
TTL Input
OADD4
TTL Input
OADD5
TTL Input
OADD6
TTL Input
OADD7
TTL Input
OADD8
TTL Input
OADD9
TTL Input
OADD10
TTL Input
OADD11
TTL Input
OADD12
TTL Input
OADD13
TTL Input
OADD14
TTL Input
OADD15
TTL Input
OADD16
TTL Input
OADD17
TTL Input
OADD18
TTL Input
OADD19
TTL Input
OADD20
TTL Input
OADD21
TTL Input
OADD22
TTL Input
OADD23
TTL Input
OADD24
TTL Input
OADD25
TTL Input
OADD26
TTL Input
10
Y22
AA23
E21
D23
E22
F21
G20
E23
F22
G21
H20
G22
H21
H22
J21
J22
K20
K21
K23
L20
L21
L22
M22
M21
N23
N22
N20
P23
P22
P21
R22
R21
T22
T21
U23
Description
Active High. Enables transfer of data from program latches
to configuration latches.
Active High. Enables program latches to accept new input
address data based upon which output(s) are selected using
OADD inputs.
Program mode select LSB
Program mode select MSB
Input address LSB
Input address
Input address
Input address
Input address
Input address MSB
Sequential
Output address LSB
Output address
Output address
Output address
Output address
Output address MSB
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Multicast
Output select Bit 0
Output select Bit 1
Output select Bit 2
Output select Bit 3
Output select Bit 4
Output select Bit 5
Output select Bit 6
Output select Bit 7
Output select Bit 8
Output select Bit 9
Output select Bit 10
Output select Bit 11
Output select Bit 12
Output select Bit 13
Output select Bit 14
Output select Bit 15
Output select Bit 16
Output select Bit 17
Output select Bit 18
Output select Bit 19
Output select Bit 20
Output select Bit 21
Output select Bit 22
Output select Bit 23
Output select Bit 24
Output select Bit 25
Output select Bit 26
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TQ8034
PRELIMINARY DATA SHEET
Table 7. Pin Descriptions (cont.)
Type
Grid Ref
Description
OADD27
OADD28
OADD29
OADD30
OADD31
OADD32
OADD33
Output Ports
OUT0,NOUT0
OUT1,NOUT1
OUT2,NOUT2
OUT3,NOUT3
OUT4,NOUT4
OUT5,NOUT5
OUT6,NOUT6
OUT7,NOUT7
OUT8,NOUT8
OUT9,NOUT9
OUT10,NOUT10
OUT11,NOUT11
OUT12,NOUT12
OUT13,NOUT13
OUT14,NOUT14
OUT15,NOUT15
OUT16,NOUT16
OUT17,NOUT17
OUT18,NOUT18
OUT19,NOUT19
OUT20,NOUT20
OUT21,NOUT21
OUT22,NOUT22
OUT23,NOUT23
OUT24,NOUT24
OUT25,NOUT25
OUT26,NOUT26
OUT27,NOUT27
OUT28,NOUT28
OUT29,NOUT29
OUT30,NOUT30
OUT31,NOUT31
OUT32,NOUT32
OUT33,NOUT33
TTL Input
TTL Input
TTL Input
TTL Input
TTL Input
TTL Input
TTL Input
U22
T20
U21
W23
U20
V21
W22
Sequential
N/A
N/A
N/A
N/A
N/A
N/A
N/A
DPECL Outputs
DPECL Outputs
DPECL Outputs
DPECL Outputs
DPECL Outputs
DPECL Outputs
DPECL Outputs
DPECL Outputs
DPECL Outputs
DPECL Outputs
DPECL Outputs
DPECL Outputs
DPECL Outputs
DPECL Outputs
DPECL Outputs
DPECL Outputs
DPECL Outputs
DPECL Outputs
DPECL Outputs
DPECL Outputs
DPECL Outputs
DPECL Outputs
DPECL Outputs
DPECL Outputs
DPECL Outputs
DPECL Outputs
DPECL Outputs
DPECL Outputs
DPECL Outputs
DPECL Outputs
DPECL Outputs
DPECL Outputs
DPECL Outputs
DPECL Outputs
D7,C6
B5,A4
B4,A3
D5,C4
D2,E3
D1,E2
F3,G4
E1,F2
G3,H4
G2,G1
H3,H2
J3,J2
K4,K3
K2,K1
L4,L3
L2,L1
M3,M2
N1,N2
N3,N4
P1,P2
P3,P4
R2,R3
T2,U1
T3,U2
T4,U3
V2,W1
U4,V3
W2,Y1
Y2,AA1
W4,Y3
AA4,Y5
AC3,AB4
AC4,AB5
AA6,Y7
True/Complement
True/Complement
True/Complement
True/Complement
True/Complement
True/Complement
True/Complement
True/Complement
True/Complement
True/Complement
True/Complement
True/Complement
True/Complement
True/Complement
True/Complement
True/Complement
True/Complement
True/Complement
True/Complement
True/Complement
True/Complement
True/Complement
True/Complement
True/Complement
True/Complement
True/Complement
True/Complement
True/Complement
True/Complement
True/Complement
True/Complement
True/Complement
True/Complement
True/Complement
Multicast
Output select Bit 27
Output select Bit 28
Output select Bit 29
Output select Bit 30
Output select Bit 31
Output select Bit 32
Output select Bit 33
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
SWITCHING
PRODUCTS
Signal
OADD = 000000
OADD = 000001
OADD = 000010
OADD = 000011
OADD = 000100
OADD = 000101
OADD = 000110
OADD = 000111
OADD = 001000
OADD = 001001
OADD = 001010
OADD = 001011
OADD = 001100
OADD = 001101
OADD = 001110
OADD = 001111
OADD = 010000
OADD = 010001
OADD = 010010
OADD = 010011
OADD = 010100
OADD = 010101
OADD = 010110
OADD = 010111
OADD = 011000
OADD = 011001
OADD = 011010
OADD = 011011
OADD = 011100
OADD = 011101
OADD = 011110
OADD = 011111
OADD = 10xxxx
OADD = 11xxxx
For additional information and latest specifications, see our website: www.triquint.com
11
TQ8034
PRELIMINARY DATA SHEET
Table 7. Pin Descriptions (cont.)
Input Ports
IN0,NIN0
IN1,NIN1
IN2,NIN2
IN3,NIN3
IN4,NIN4
IN5,NIN5
IN6,NIN6
IN7,NIN7
IN8,NIN8
IN9,NIN9
IN10,NIN10
IN11,NIN11
IN12,NIN12
IN13,NIN13
IN14,NIN14
IN15,NIN15
IN16,NIN16
IN17,NIN17
IN18,NIN18
IN19,NIN19
IN20,NIN20
IN21,NIN21
IN22,NIN22
IN23,NIN23
IN24,NIN24
IN25,NIN25
IN26,NIN26
IN27,NIN27
IN28,NIN28
IN29,NIN29
IN30,NIN30
IN31,NIN31
IN32,NIN32
IN33,NIN33
12
Type
DPECL Input
DPECL Input
DPECL Input
DPECL Input
DPECL Input
DPECL Input
DPECL Input
DPECL Input
DPECL Input
DPECL Input
DPECL Input
DPECL Input
DPECL Input
DPECL Input
DPECL Input
DPECL Input
DPECL Input
DPECL Input
DPECL Input
DPECL Input
DPECL Input
DPECL Input
DPECL Input
DPECL Input
DPECL Input
DPECL Input
DPECL Input
DPECL Input
DPECL Input
DPECL Input
DPECL Input
DPECL Input
DPECL Input
DPECL Input
Grid Ref.
A7,B8
C9,B9
D10,C10
B10,A10
C11,B11
A11,B12
C12,A13
B13,C13
B14,C14
D14,B15
C15,B16
C16,A17
C17,B18
D17,C18
B19,A20
B20,A21
AC21,AB20
AC20,AB19
AC19,AB18
AA17,Y16
AB17,AA16
AC17,AB16
AA15,AB15
AA14,AB14
Y13,AA13
AB13,AC13
AB12,AA12
AC11,AB11
AC10,AB10
AA10,Y10
AB9,AA9
AB8,AA8
B7,C8
AC7,AB7
Description
True/Complement Data IN0
True/Complement Data IN1
True/Complement Data IN2
True/Complement Data IN3
True/Complement Data IN4
True/Complement Data IN5
True/Complement Data IN6
True/Complement Data IN7
True/Complement Data IN8
True/Complement Data IN9
True/Complement Data IN10
True/Complement Data IN11
True/Complement Data IN12
True/Complement Data IN13
True/Complement Data IN14
True/Complement Data IN15
True/Complement Data IN16
True/Complement Data IN17
True/Complement Data IN18
True/Complement Data IN19
True/Complement Data IN20
True/Complement Data IN21
True/Complement Data IN22
True/Complement Data IN23
True/Complement Data IN24
True/Complement Data IN25
True/Complement Data IN26
True/Complement Data IN27
True/Complement Data IN28
True/Complement Data IN29
True/Complement Data IN30
True/Complement Data IN31
True/Complement Data IN32
True/Complement Data IN33
For additional information and latest specifications, see our website: www.triquint.com
IADD=000000
IADD=000001
IADD=000010
IADD=000011
IADD=000100
IADD=000101
IADD=000110
IADD=000111
IADD=001000
IADD=001001
IADD=001010
IADD=001011
IADD=001100
IADD=001101
IADD=001110
IADD=001111
IADD=010000
IADD=010001
IADD=010010
IADD=010011
IADD=010100
IADD=010101
IADD=010110
IADD=010111
IADD=011000
IADD=011001
IADD=011010
IADD=011011
IADD=011100
IADD=011101
IADD=011110
IADD=011111
IADD=10xxxx
IADD=11xxxx
Differential LVPECL Output Into Oscilloscope
TQ8034
PRELIMINARY DATA SHEET
Power Pins and Unused Pins
Signal
Description
VTT
Input Termination
Supply
VDD
+3.3V Power Supply
GND
Grid Ref
D8
Y14
A1
D3
D20
M20
Y4
AA3
AC23
A2
A18
C22
M1
V23
AC2
AC18
Ground Supply
D11
Y11
A23
D4
D21
R4
Y6
AA5
C5
A6
A22
F1
M23
AA2
AC6
AC22
D13
Y8
B2
D6
F4
R20
Y9
AA19
D16
D19
Y19
Y17
B22
D9
F20
V4
Y12
AA21
C3
D12
J4
V20
Y15
AB2
C19
D15
J20
W3
Y18
AB22
C21
D18
M4
W21
Y20
AC1
A8
B1
F23
R1
AA22
AC8
A9
B3
H1
R23
AB1
AC9
A12
B21
H23
T1
AB3
AC12
A15
B23
J1
T23
AB21
AC15
A16
C2
J23
V1
AB23
AC16
Figure 7. Interface Circuits
DC Coupled LVPECL Input
AC Coupled LVPECL Input
GND
50 Ω Trace
GND
LVPECL
TQ8034
130 Ω
50 Ω Trace
IN
LVPECL
GND
IN
LVPECL
GND
50 Ω
VCC - 2.0V
VTT
LVPECL
GND
VCC - 1.3V
50 Ω
VTT
50 Ω
50 Ω Trace
50 Ω
50 Ω Trace
NIN
NIN
LVPECL
LVPECL
GND
TQ8034
GND
130 Ω
GND
GND
GND
LVTTL Input
LVTTL
TQ8034
LVTTL
For additional information and latest specifications, see our website: www.triquint.com
13
SWITCHING
PRODUCTS
Table 7. Pin Descriptions (cont.)
TQ8034
PRELIMINARY DATA SHEET
Figure 8. Typical Performance
Typical Performance at 1.6Gb/s
with 223-1 PRBS data
Figure 9. Suggested measurement setup
TQ8034
VCC
Scope
OUT
PECL/ECL
LVPECL
Termination
OUT
50 Ω
VBias
VCC
PECL/ECL
Termination
NOUT
LVPECL
14
GND
NOUT
50 Ω
GND
** PECL/ECL terminations available from
Cascade Microtech model 523-0150 and
Picosecond Pulse Labs model 5623
For additional information and latest specifications, see our website: www.triquint.com
OUT - NOUT
TQ8034
PRELIMINARY DATA SHEET
Figure 10. BGA Mechanical Dimensions
Top view
Bottom view
D
D1
b
A1 ball corner
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A-1 ball I.D. mark
S
E
A
e
E1
SWITCHING
PRODUCTS
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
e
S
A
A
Side view
A2
Section A-A
P
Seating plane
d
A1
ddd
Table 8. BGA Dimensions (in millimeters)
Symbol
Parameter
Min.
Nom.
Max.
A
A1
Overall thickness
Ball Height
1.41
0.56
1.54
0.63
1.67
0.70
A2
D
D1
E
E1
Body thickness
Body size
Ball footprint
Body size
Ball footprint
0.85
30.90
27.84
30.90
27.84
0.91
31.00
27.94
31.00
27.94
0.97
31.10
28.04
31.10
28.04
b
d
e
ddd
P
Ball diameter
Distance encapsulation to balls
Ball pitch
Seating plane clearance
Encapulation height
0.60
0.75
0.6
1.27
0.30
0.30
0.90
S
Solder ball placement
PCB pad size
0.15
0.20
—
—
0.63
0.35
0.35
0.00
For additional information and latest specifications, see our website: www.triquint.com
15
TQ8034
PRELIMINARY DATA SHEET
Heat Sink Vendors
Thermal Management
Most applications will require the use of a heatsink or
other thermal management system in order to keep the
package case temperature within the recommended
operation limits. As long as the package case
temperature does not exceed 85 degrees C, the die
temperature will remain well within TriQuint’s
requirements for reliability.
Selection of a thermal management device is very
dependent on the system mechanical and
environmental constrains. Several vendors of heatsink
and other thermal management systems support the
TQ8034’s thermally enhanced Ball Grid Array package.
These vendors will work with you to evaluate the
system requirements and recommend the best
solution.
Aavid Thermal Technologies
One Kool Path
P.O. Box 400
Laconia, NH 03247
603-528-3400
Sumitomo Metal (SMI)
2953 Bunker Hill Lane
Santa Clara, CA 95054
408-982-0990
Wakefield Engineering, Inc.
60 Audubon Road
Wakefield, MA 01880
617-345-5900
Ordering Information
TQ8034
1.6 Gbit/sec 34x34 Crosspoint Switch
Additional Information
For latest specifications, additional product information, worldwide sales and distribution locations, and
information about TriQuint:
Web: www.triquint.com
Email: [email protected]
Tel: (503) 615-9000
Fax: (503) 615-8900
For technical questions and additional information on specific applications:
Email: [email protected]
The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or omissions. TriQuint assumes no
responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party.
TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems.
Copyright © 1999 TriQuint Semiconductor, Inc. All rights reserved.
Revision 0.1.B
August 1999
16
For additional information and latest specifications, see our website: www.triquint.com