VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet OC-48 16:1 SONET/SDH MUX with Clock Generator VSC8163 Features • 2.488Gb/s 16:1 Multiplexer • On-Chip PLL-Based Clock Generator • Targeted for SONET OC-48 / SDH STM-16 Applications • 128 Pin, 14x20mm PQFP Package • Differential LVPECL Low-Speed Interface • Single +3.3V Supply General Description The VSC8163 is a 16:1 multiplexer with integrated clock generator for use in SONET/SDH systems operating at a 2.48832Gb/s data rate. The internal clock generator uses a Phase-Locked Loop (PLL) to multiply either a 77.76MHz or 155.52MHz reference clock in order to provide the 2.48832GHz clock for internal logic and output retiming. The 16-bit parallel interface incorporates an on-board FIFO, eliminating loop timing design issues by providing a flexible parallel timing architecture. The device operates using a +3.3V power supply, and is packaged in a thermally-enhanced plastic package. The thermal performance of the 128PQFP allows the use of the VSC8163 without a heat sink under most thermal conditions. VSC8163 Block Diagram CLK16I+ CLK16I- REFCLKO+ REFCLKO- 16x5 FIFO D15+ D15- Input Register D0+ D0- Write Pointer Output Retime FIFO Control Read Pointer DO+ DO- CLKO+ CLKOFIFO_WARN Reset CLK16O+ CLK16OREFCLK+ REFCLK Divide by 16 Divide by 2 2.488GHz PLL REF_FREQSEL G52216-0, Rev 3.3 01/05/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 1 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet OC-48 16:1 SONET/SDH MUX with Clock Generator VSC8163 Functional Description Low-Speed Interface The Upstream Device should use the CLK16O as the timing source for its final output latch (see Figure 1). The Upstream Device should then generate a CLK16I phase aligned with the data. The VSC8163 will latch D[15:0]± on the rising edge of CLK16I+. The data must meet setup and hold times with respect to CLK16I (see Table 2). In addition to the CLK16O clock output, there also exists a utility REFCLKO output signal, which is a clock with the same rate as that presented at the REFCLK input. A FIFO exists within the VSC8163 to eliminate difficult system loop timing issues. Once the PLL has locked to the reference clock, RESET must be held low for a minimum of five CLK16 cycles ( > 32ns) to initialize the FIFO, then RESET should be set high and held constant for continuous FIFO operation. For the transparent mode of operation (no FIFO), simply hold RESET at a constant low state (see Figure 2). The use of a FIFO permits the system designer to tolerate an arbitrary amount of delay between CLK16O and CLK16I. Once RESET is asserted and the FIFO initialized, the delay between CLK16O and CLK16I can decrease or increase up to one period of the low-speed clock (6.4ns). Should this delay drift exceed one period, the write pointer and the read pointer could point to the same word in the FIFO, resulting in a loss of transmitted data (a FIFO overflow). In the event of a FIFO overflow, an active low FIFO_WARN signal is asserted (for a minimum of 5 CLK16I cycles) which can be used to initiate a reset signal from an external controller. The CLK16O± output driver is a LVPECL output driver designed to drive a 50Ω transmission line. The transmission line can be DC terminated with a split-end termination scheme (see Figure 3), or DC terminated by 50Ω to VCC-2V on each line (see Figure 4). At any time, the equivalent split-end termination technique can be substituted for the traditional 50Ω to VCC-2V on each line. AC-coupling can be achieved by a number of methods. Figure 5 illustrates an example AC-coupling method for the occasion when the downstream device provides the bias point for AC-coupling. If the downstream device were to have internal termination, the line-toline 100Ω resistor may not be necessary. Figure 1: Low-Speed Systems Interface CLK16I Write 16 x 5 FIFO x16 Upstream Device Read VSC8163 CLK16O REFCLK Divide by 16 2.488GHz PLL Page 2 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com G52216-0, Rev 3.3 01/05/00 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet OC-48 16:1 SONET/SDH MUX with Clock Generator VSC8163 Figure 2: Enabling FIFO Operation PLL locked to reference clock. Minimum 5 CLK16 cycles (32ns) FIFO Mode Operation Transparent Mode Operation RESET Holding RESET “low” for a minimum of five CLK16 cycles, then setting “high” enables FIFO operation. Holding RESET constantly “low” bypasses the FIFO for transparent mode operation. Figure 3: Split-End DC Termination of CLK16O+/-, REFCLKO+/VCC VSC8163 Split-end equivalent termination is Z0 to VTERM R1 = 125Ω R2 = 83Ω, Zo=50Ω, VTERM= VCC-2V R1 R1 R2 R2 Zo Zo R1||R2 = Z0 VCCR2 + VEER1 R1+R2 = VTERM VEE Figure 4: Traditional DC Termination of CLK16O+/-, REFCLKO+/- VSC8163 Z0 Z0 50Ω 50Ω VCC-2V G52216-0, Rev 3.3 01/05/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 3 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet OC-48 16:1 SONET/SDH MUX with Clock Generator VSC8163 Figure 5: AC Termination of CLK16O+/-, REFCLKO+/- VSC8163 Z0 100nF downstream bias point generated internally Z0 50Ω 50Ω 100nF VCC-2V High-Speed Data and Clock Output The high-speed data and clock output drivers consist of a differential pair designed to drive a 50Ω transmission line. The transmission line should be terminated with a 100Ω resistor at the load between true and complement outputs (see Figure 6). Connection to a termination voltage is not required. The output driver is back terminated to 50Ω on-chip, providing a snubbing of any reflections. If used single-ended, the high-speed output driver must still be terminated differentially at the load with a 100Ω resistor between true and complement outputs. The high-speed clock output can be powered down for additional power savings. To power down the highspeed clock, tie the associated pins to VCC (see Table 3, Package Pin Descriptions, pins 5,6,7). Figure 6: High-Speed Output Termination VCC 50Ω 50Ω 100Ω Z0 = 50Ω Pre-Driver VEE Page 4 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com G52216-0, Rev 3.3 01/05/00 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet OC-48 16:1 SONET/SDH MUX with Clock Generator VSC8163 Clock Generator An on-chip PLL generates the 2.48832GHz transmit clock from the externally provided REFCLK input. The on-chip PLL uses a low phase noise reactance-based Voltage Controlled Oscillator (VCO) with an on-chip loop filter. The loop bandwidth of the PLL is within the SONET specified limit of 2MHz. The customer can select to provide either a 77.76MHz reference (recommended), or the 2x of that reference, 155.52MHz. REF_FREQSEL is used to select the desired reference frequency. REF_FREQSEL = “0” designates REFCLK input as 77.76MHz, REF_FREQSEL = “1” designates REFCLK input as 155.52MHz. The REFCLK should be of high quality since noise on the REFCLK below the loop band width of the PLL will pass through the PLL and appear as jitter on the output. Preconditioning of the REFCLK signal with a VCXO may be required to avoid passing REFCLK noise with greater than 2ps of RMS jitter to the output. The VSC8163 will output the REFCLK noise in addition to the intrinsic jitter from the VSC8163 itself during such conditions. Figure 7: AC Termination of Low-Speed LVPECL REFCLK, D[15:0] Inputs Split-end equivalent termination is Z0 to VTERM R1 = 83Ω R2 = 125Ω, Z0=50Ω, VTERM = VCC-2V Chip Boundary VCC = 3.3V VCC R1+R2 R1 ZO R1||R2 = Zo VCCR2 + VEER1 = VBIAS CIN R2 VEE VCC R1 ZO CIN R2 VEE VEE = 0V CIN typ = 100nF for AC operation Low-Speed Inputs The incoming low-speed data and reference clock input are received by LVPECL inputs D[15:0] and REFCLK. Off-chip termination of these inputs is required. For AC-coupling, a bias voltage suitable for AC-coupling needs to be provided (see Figure 7 for external biasing resistor scheme). In most situations these inputs will have high transition density and little DC offset. However, in cases where this does not hold, direct DC connection is possible. All serial data inputs have the same circuit topology, as shown in Figure 7. If the input signal is driven differentially and DC-coupled to the part, the mid-point of the G52216-0, Rev 3.3 01/05/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 5 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet OC-48 16:1 SONET/SDH MUX with Clock Generator VSC8163 input signal swing should be centered about this common-mode reference voltage (VCMI) and not exceed the maximum allowable amplitude. For single-ended, DC-coupling operations, it is recommended that the user provides an external reference voltage. The external reference should have a nominal value equivalent to the common mode switch point of the DC-coupled signal, and can be connected to either side of the differential gate. Power Supplies This device is specified as a LVPECL device with a single positive 3.3V supply. Should the user desire to use the device in an ECL environment with a negative 3.3V supply, then VCC will be ground and VEE will be -3.3V. If used with VEE tied to -3.3V, the TTL control signals are still referenced to VEE. Decoupling of the power supplies is a critical element in maintaining the proper operation of the part. It is recommended that the VCC power supply be decoupled using a 0.1µF and 0.01µF capacitor placed in parallel on each VCC power supply pin as close to the package as possible. If room permits, a 0.001µF capacitor should also be placed in parallel with the 0.1µF and 0.01µF capacitors mentioned above. Recommended capacitors are low inductance ceramic SMT X7R devices. For the 0.1 µF capacitor, a 0603 package should be used. The 0.01µF and 0.001µF capacitors can be either 0603 or 0402 packages. Extra care needs to be taken when decoupling the analog power supply pins (VCCANA). In order to maintain the optimal jitter and loop bandwidth characteristics of the PLL contained in the VSC8163, the analog power supply pins should be filtered from the main power supply with a 10µH C-L-C pi filter. If preferred, a ferrite bead may be used to provide the isolation. The 0.1µF and 0.01µF decoupling capacitors are still required and must be connected to the supply pins between the device and the C-L-C pi filter (or ferrite bead). For low frequency decoupling, 47µF tantalum low inductance SMT caps are sprinkled over the board’s main +3.3V power supply and placed close to the C-L-C pi filter. If the device is being used in an ECL environment with a -3.3V supply, then all references to decoupling VCC must be changed to VEE, and all references to decoupling 3.3V must be changed to -3.3V. Figure 8: PLL Power Supply Decoupling Scheme 10µH VCC VCC_ANA 10µF 0.1µF VEE Page 6 0.1µF 0.01µF VEE_ANA © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com G52216-0, Rev 3.3 01/05/00 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet OC-48 16:1 SONET/SDH MUX with Clock Generator VSC8163 AC Characteristics Figure 9: Parallel Input Data and Clock Timing Waveforms CLK16I+ Parallel Data Clock Input tTXDSU D[0...15]+ Parallel Data Inputs tTXDH Valid Data 1 Valid Data 2 CLK16O+ Parallel Data Clock Output = don't care Figure 10: Serial Data and Clock Output Phase Timing Waveforms CLKOPER DO+ Differential Serial Data Output D15 D14 D13 D1 D0 LSB MSB Time tSET CLKO+ Differential Clock Output tHOLD NOTE: Bit 15 (MSB) is received first, Bit 0 (LSB) is received last. G52216-0, Rev 3.3 01/05/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 7 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet OC-48 16:1 SONET/SDH MUX with Clock Generator VSC8163 Table 1: AC Characteristics Parameters Description Min Typ Max Units Conditions TDSU Data setup time to the rising edge of CLK16I+ 0.75 — — ns TDH Data hold time after the rising edge of CLK16+ 1.0 — — ns TDOR,TDOF DO± rise and fall time — — 120 ps 20% to 80% into 100Ω load See Figure 6 tCLKR, tCLKF CLK16O± rise and fall times — — 250 ps See Figures 3 and 4 CLK16OD CLK16O± duty cycle 40 — 60 % CLKID CLK16I± duty cycle 30 — 70 % RCKD Reference clock duty cycle 40 — 60 % CLKOD CLKO duty cycle 40 — 60 % CLKOPER CLKO period — 401.9 — ps SONET based 77.76MHz or 155.52MHz reference clock CLK16OPER CLK16O period — 6.4 — ns SONET based 77.76MHz or 155.52MHz reference clock tSET DO setup time with respect to rising CLKO edge — 90 — ps Inverting CLKO will switch (approx) tSET and tHOLD values. tHOLD DO hold time with respect to rising CLKO edge — 310 — ps Inverting CLKO will switch (approx) tSET and tHOLD values. Assuming 10% distortion of CLKO Clock Multiplier Performance TDJ Output data jitter — — 4 ps rms, tested to SONET specification (12kHz to 20MHz) with 2ps rms jitter on REFCLK. TCJ Output clock jitter — — 4 ps rms, tested to SONET specification (12kHz to 20MHz) with 2ps rms jitter on REFCLK. Jittertol Jitter tolerance — — — — Exceeds SONET/SDH mask Tuning Range -100 +100 ppm Page 8 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com G52216-0, Rev 3.3 01/05/00 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet OC-48 16:1 SONET/SDH MUX with Clock Generator VSC8163 Figure 11: Differential and Single-Ended Input / Output Voltage Measurement b a b a Single Ended Swing =α Differential Swing =α * Differential swing (α) is specified as | b - a | ( or | a - b | ), as is the single ended swing. Differential swing is specified as equal in magnitude to single ended swing. Table 2: DC Characteristics (Over recommended operating conditions) Parameters Description Min Typ Max Units Conditions VOH(DO) Output HIGH voltage (DO) VCC - 0.825 — VCC V See Figure 12 VOL(DO) Output LOW voltage (DO) VCC - 1.30 — VCC - 0.50 V See Figure 12 ∆VOD(DO) Data output differential voltage (DO) 550 — 900 mV 100Ω termination between DO± at load ∆VOCLK(CLKO) CLK output differential voltage (CLKO) 500 — 900 mV 100Ω termination between DO± at load VCMO Output common-mode voltage 2.10 — 3.00 V RDO Back termination impedance 40 — 60 Ω Guaranteed, not tested VOH Output HIGH voltage (CLK16O, REFCLKO) VCC - 1.020 — VCC - 0.700 V See Figure 12 VOL Output LOW voltage (CLK16O, REFCLKO) VCC - 2.000 — VCC - 1.620 V See Figure 12 VIH Input HIGH voltage (LVPECL) VCC - 1.100 — VCC - 0.700 V VIL Input LOW voltage (LVPECL) VCC - 2.0 — VCC - 1.540 V IIH Input HIGH current (LVPECL) — — 200 µA VIN=VIH(max) IIL Input LOW current (LVPECL) -50 — — µA VIN=VIL(min) RI Input resistance (LVPECL) 10k — — Ω ∆VI Input differential voltage (LVPECL) 200 — — mV VCMI Input common-mode voltage (LVPECL) VCC - 1.5 — VCC - 0.5 V VOH Output HIGH voltage (TTL) 2.4 — — V IOH = -1.0mA VOL Output LOW voltage (TTL) — — 0.5 V IOL = +1.0mA VIH Input HIGH voltage (TTL) 2.0 — 5.5 V G52216-0, Rev 3.3 01/05/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 9 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet OC-48 16:1 SONET/SDH MUX with Clock Generator Parameters VSC8163 Description Min Typ Max Units Conditions VIL Input LOW voltage (TTL) 0.0 — 0.8 V IIH Input HIGH current (TTL) — — 500 µA VIN = 2.4V IIL Input LOW current (TTL) — — -500 µA VIN = 0.4V VCC Supply voltage 3.14 — 3.47 V 3.3V± 5% PD Power dissipation — 1.2 1.7 W Outputs open, VCC = VCC max ICC Supply current — 350 490 mA Outputs open, VCC = VCC max Figure 12: Parametric Measurement Information Parametric Test Load Circuit PECL Rise and Fall Time Serial Output Load 80% 20% Z0 = 50Ω Tr Tf 50Ω VCC-2V Parametric Test Load Circuit High-Speed Data Output Z0 = 50Ω 50Ω VCC Page 10 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com G52216-0, Rev 3.3 01/05/00 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC8163 OC-48 16:1 SONET/SDH MUX with Clock Generator Absolute Maximum Ratings (1) Power Supply Voltage (VCC).......................................................................................................... -0.5V to +3.8V DC Input Voltage (differential inputs).................................................................................... -0.5V to VCC +0.5V DC Input Voltage (TTL inputs) ...................................................................................................... -0.5V to +5.5V DC Output Voltage (TTL outputs) ........................................................................................ -0.5V to VCC + 0.5V Output Current (TTL outputs) ................................................................................................................. +/-50mA Output Current (differential outputs)........................................................................................................ +/-50mA Case Temperature Under Bias ......................................................................................................-55oC to +125oC Recommended Operating Conditions Power Supply Voltage, (VCC)................................................................................................................ +3.3V+5% Operating Temperature Range ........................................................... 0oC Ambient to +85oC Case Temperature NOTE: (1) CAUTION: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods may affect device reliability. ESD Ratings Proper ESD procedures should be used when handling this product. The VSC8163 is rated to the following ESD voltages based on the human body model: 1. All pins are rated at or above 1500V. G52216-0, Rev 3.3 01/05/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 11 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet OC-48 16:1 SONET/SDH MUX with Clock Generator VSC8163 Package Pin Descriptions Page 12 VCC VEE VEE NC NC VCC_ANA VEE_ANA REFCLKO– REFCLKO+ VEE VCC REFCLK– REFCLK+ NC NC NC NC NC VEE D15+ D15– VCC D14+ D14– NC VCC 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 Figure 13: Pin Diagram—128-Pin PQFP NC 1 102 VCC NC 2 101 D13+ NC 3 100 D13– VCC 4 99 VCC VEEP_CLK 5 98 D12+ VEEP_CLK 6 97 D12– VEEP_CLK 7 96 VEE VCC 8 95 D11+ CLKO+ 9 94 D11– CLKO- 10 93 VCC VCC 11 92 D10+ VCC 12 91 D10– NC 13 90 VCC NC 14 89 D9+ VEE 15 88 D9– VEE 16 87 VEE VEE 17 86 D8+ VCC 18 85 D8– DO+ 19 84 VCC DO– 20 83 D7+ VCC 21 82 D7– NC 22 81 VCC VCC 23 80 D6+ VCC 24 79 D6– VCC 25 78 VEE VEE 26 77 D5+ VEE 27 76 D5– VEE 28 75 VCC VEE 29 74 D4+ VEE 30 73 D4– NC 31 72 VCC NC 32 71 D3+ NC 33 70 D3– NC 34 69 VEE NC 35 68 D2+ NC 36 67 D2– NC 37 66 VCC REF_FREQSEL 38 65 NC 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 VCC VEE FIFO_WARN VEE VCC RESET NC NC NC NC NC VCC VEE CLK16O+ CLK16O– VCC CLKI+ CLKI– VEE D0– D0+ VCC D1– D1+ NC VCC VSC8163 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com G52216-0, Rev 3.3 01/05/00 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet OC-48 16:1 SONET/SDH MUX with Clock Generator VSC8163 Package Pin Descriptions Table 3: Package Pin Identification Pin # Name I/O Level 1 NC — — No connect, leave unconnected(1) 2 NC — — No connect, leave unconnected(1) 3 NC — — No connect, leave unconnected(1) 4 VCC — +3.3V typ. Positive power supply 5 VEEP_CLK — GND typ. High-speed clock VEE power supply (tie to VCC for power down) 6 VEEP_CLK — GND typ. High-speed clock VEE power supply (tie to VCC for power down) 7 VEEP_CLK — GND typ. High-speed clock VEE power supply (tie to V CC for power down) 8 VCC — +3.3V typ. Positive power supply 9 CLKO+ O HS High-speed clock output, true 10 CLKO- O HS High-speed clock output, complement 11 VCC — +3.3V typ. Positive power supply 12 VCC — +3.3V typ. Positive power supply 13 NC — — No connect, leave unconnected(1) 14 NC — — No connect, leave unconnected(1) 15 VEE — GND typ. Negative power supply 16 VEE — GND typ. Negative power supply 17 VEE — GND typ. Negative power supply 18 VCC — +3.3V typ. Positive power supply 19 DO+ O HS High-speed data output, true 20 DO- O HS High-speed data output, complement 21 VCC — +3.3V typ. 22 NC — — 23 VCC — +3.3V typ. Positive power supply 24 VCC — +3.3V typ. Positive power supply 25 VCC — +3.3V typ. Positive power supply 26 VEE — GND typ. Negative power supply 27 VEE — GND typ. Negative power supply 28 VEE — GND typ. Negative power supply 29 VEE — GND typ. Negative power supply 30 VEE — GND typ. Negative power supply 31 NC — — G52216-0, Rev 3.3 01/05/01 Description Positive power supply No connect, leave unconnected(1) No connect, leave unconnected(1) © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 13 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet OC-48 16:1 SONET/SDH MUX with Clock Generator VSC8163 Pin # Name I/O Level 32 NC — — No connect, leave unconnected(1) 33 NC — — No connect, leave unconnected(1) 34 NC — — No connect, leave unconnected(1) 35 NC — — No connect, leave unconnected(1) 36 NC — — No connect, leave unconnected(1) 37 NC — — No connect, leave unconnected(1) 38 REF_FREQSEL I TTL 39 VCC — +3.3V typ. Positive power supply 40 VEE — GND typ. Negative power supply 41 FIFO_WARN O TTL FIFO overflow warning 42 VEE — GND typ. Negative power supply 43 VCC — +3.3V typ. Positive power supply 44 RESET I TTL 45 NC — — No connect, leave unconnected(1) 46 NC — — No connect, leave unconnected(1) 47 NC — — No connect, leave unconnected(1) 48 NC — — No connect, leave unconnected(1) 49 NC — — No connect, leave unconnected(1) 50 VCC — +3.3V typ. Positive power supply 51 VEE — GND typ. Negative power supply 52 CLK16O+ O LVPECL Low-speed clock output, true. A divide-by-16 version of the 2.48832GHz PLL. 53 CLK16O- O LVPECL Low-speed clock output, complement. A divide-by-16 version of the 2.48832GHz PLL. 54 VCC — +3.3V typ. 55 CLKI+ I LVPECL Low-speed clock input for latching low-speed data, true 56 CLKI- I LVPECL Low-speed clock input for latching low-speed data, complement 57 VEE — GND typ. Negative power supply 58 D0- I LVPECL Low-speed differential parallel data (MSB) 59 D0+ I LVPECL Low-speed differential parallel data (MSB) 60 VCC — +3.3V typ. 61 D1- I LVPECL Low-speed differential parallel data 62 D1+ I LVPECL Low-speed differential parallel data 63 NC — — Page 14 Description Reference clock input select Reset to align FIFO Write and Read pointers Positive power supply Positive power supply No connect, leave unconnected(1) © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com G52216-0, Rev 3.3 01/05/00 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet OC-48 16:1 SONET/SDH MUX with Clock Generator VSC8163 Pin # Name I/O Level 64 VCC — +3.3V typ. 65 NC — — 66 VCC — +3.3V typ. 67 D2- I LVPECL Low-speed differential parallel data 68 D2+ I LVPECL Low-speed differential parallel data 69 VEE — GND typ. Negative power supply 70 D3- I LVPECL Low-speed differential parallel data 71 D3+ I LVPECL Low-speed differential parallel data 72 VCC — +3.3V typ. 73 D4- I LVPECL Low-speed differential parallel data 74 D4+ I LVPECL Low-speed differential parallel data 75 VCC — +3.3V typ. 76 D5- I LVPECL Low-speed differential parallel data 77 D5+ I LVPECL Low-speed differential parallel data 78 VEE — GND typ. Negative power supply 79 D6- I LVPECL Low-speed differential parallel data 80 D6+ I LVPECL Low-speed differential parallel data 81 VCC — +3.3V typ. 82 D7- I LVPECL Low-speed differential parallel data 83 D7+ I LVPECL Low-speed differential parallel data 84 VCC — +3.3V typ. 85 D8- I LVPECL Low-speed differential parallel data 86 D8+ I LVPECL Low-speed differential parallel data 87 VEE — GND typ. Negative power supply 88 D9- I LVPECL Low-speed differential parallel data 89 D9+ I LVPECL Low-speed differential parallel data 90 VCC — +3.3V typ. 91 D10- I LVPECL Low-speed differential parallel data 92 D10+ I LVPECL Low-speed differential parallel data 93 VCC — +3.3V typ. 94 D11- I LVPECL Low-speed differential parallel data 95 D11+ I LVPECL Low-speed differential parallel data 96 VEE — GND typ. Negative power supply 97 D12- I LVPECL Low-speed differential parallel data G52216-0, Rev 3.3 01/05/01 Description Positive power supply No connect, leave unconnected(1) Positive power supply Positive power supply Positive power supply Positive power supply Positive power supply Positive power supply Positive power supply © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 15 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet OC-48 16:1 SONET/SDH MUX with Clock Generator VSC8163 Pin # Name I/O Level Description 98 D12+ I LVPECL 99 VCC — +3.3V typ. 100 D13- I LVPECL Low-speed differential parallel data 101 D13+ I LVPECL Low-speed differential parallel data 102 VCC — +3.3V typ. Positive power supply 103 VCC — +3.3V typ. Positive power supply 104 NC — — 105 D14- I LVPECL Low-speed differential parallel data 106 D14+ I LVPECL Low-speed differential parallel data 107 VCC — +3.3V typ. 108 D15- I LVPECL Low-speed differential parallel data (LSB) 109 D15+ I LVPECL Low-speed differential parallel data (LSB) 110 VEE — GND typ. Negative power supply 111 NC — — No connect, leave unconnected(1) 112 NC — — No connect, leave unconnected(1) 113 NC — — No connect, leave unconnected(1) 114 NC — — No connect, leave unconnected(1) 115 NC — — No connect, leave unconnected(1) 116 REFCLK+ I LVPECL Reference clock input, true 117 REFCLK- I LVPECL Reference clock input, complement 118 VCC — +3.3V typ. Positive power supply 119 VEE — GND typ. Negative power supply 120 REFCLKO+ O LVPECL Reference clock output, true 121 REFCLKO- O LVPECL Reference clock output, complement 122 VEE_ANA — GND typ. Negative power supply pins for analog parts of CMU 123 VCC_ANA — +3.3V typ. Positive power supply pins for analog parts of CMU 124 NC — — No connect, leave unconnected(1) 125 NC — — No connect, leave unconnected(1) 126 VEE — GND typ. Negative power supply 127 VEE — GND typ. Negative power supply 128 VCC — +3.3V typ. Positive power supply Low-speed differential parallel data Positive power supply No connect, leave unconnected(1) Positive power supply NOTE: (1) No connect (NC) pins must be left unconnected, or floating. Connecting any of these pins to either the positive or negative power supply rails may cause improper operation or failure of the device or in extreme cases, cause permanent damage to the device. Page 16 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com G52216-0, Rev 3.3 01/05/00 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet OC-48 16:1 SONET/SDH MUX with Clock Generator VSC8163 Package Information 128-Pin PQFP Package Drawing PIN 128 PIN 102 PIN 1 RAD. 2.92 ± .50 (2) E1 EXPOSED INTRUSION 0.127 MAX. E 2.54 ± .50 EXPOSED HEATSINK PIN 38 PIN 64 D1 D TOP VIEW Key mm Tolerance A 2.35 MAX A1 0.25 MAX A2 2.00 +.10 D 17.20 ±.20 D1 14.00 ±.10 E 23.20 ±.20 E1 20.00 ±.10 L .88 +.15/-.10 e .50 BASIC ±.05 b .22 θ 0°-7° R .30 TYP R1 .20 TYP 10° TYP. A2 A e A1 10° TYP. R R1 θ1 A Notes: 1) 2) 3) Drawing is not to scale All dimensions in mm Package represented is also used for the 64, 80, & 100 PQFP packages. Pin count drawn does not reflect the 128 Package. G52216-0, Rev 3.3 01/05/01 STANDOFF A1 .25 θ 0.17 MAX. b LEAD COPLANARITY L © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com NOTES: Package #: 101-322-5 Issue #: 2 Page 17 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet OC-48 16:1 SONET/SDH MUX with Clock Generator VSC8163 Thermal Considerations This package has been enhanced with a copper heat slug to provide a low thermal resistance path from the die to the exposed surface of the heat spreader. The thermal resistance is shown in the following table Table 4: Thermal Resistance Symbol °C/W Description θJC Thermal resistance from junction-to-case. 1.34 θCA Thermal resistance from case-to-ambient with no airflow, including conduction through the leads. 25.0 Thermal Resistance with Airflow Shown in the Table 5 is the thermal resistance with airflow. This thermal resistance value reflects all the thermal paths including through the leads in an environment where the leads are exposed. The temperature difference between the ambient airflow temperature and the case temperature should be the worst-case power of the device multiplied by the thermal resistance. Table 5: Thermal Resistance with Airflow Airflow θca (oC/W) 100 lfpm 21 200 lfpm 18 400 lfpm 16 600 lfpm 14.5 Maximum Ambient Temperature without Heatsink The worst case ambient temperature without use of a heatsink is given by the equation: T where: θCA ΤA(MAX) ΤC(MAX) P(MAX) Page 18 A ( MAX ) = T C ( MAX ) –P θ ( MAX ) CA Theta case-to-ambient at appropriate airflow Ambient Air temperature Case temperature (85oC for VSC8163) Power (1.7W for VSC8163) © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com G52216-0, Rev 3.3 01/05/00 VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet OC-48 16:1 SONET/SDH MUX with Clock Generator VSC8163 The results of this calculation are listed in Table 6: Table 6: Maximum Ambient Air Temperature without Heatsink Airflow Max Ambient Temp( oC) None 43 100 lfpm 49 200 lfpm 54 400 lfpm 58 600 lfpm 60 Note that ambient air temperature varies throughout the system based on the positioning and magnitude of heat sources and the direction of air flow. Ordering Information The order number for this product is formed by a combination of the device number, and package type. VSC8163 XX Device Type VSC8163: OC-48 16:1 SONET/SDH MUX with Clock Generator Package Style QR: 128-pin PQFP Notice Vitesse Semiconductor Corporation (“Vitesse”) provides this document for informational purposes only. This document contains pre-production information about Vitesse products in their concept, development and/or testing phase. All information in this document, including descriptions of features, functions, performance, technical specifications and availability, is subject to change without notice at any time. Nothing contained in this document shall be construed as extending any warranty or promise, express or implied, that any Vitesse product will be available as described or will be suitable for or will accomplish any particular task. Vitesse products are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without written consent is prohibited. G52216-0, Rev 3.3 01/05/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 19 VITESSE SEMICONDUCTOR CORPORATION OC-48 16:1 SONET/SDH MUX with Clock Generator Page 20 Preliminary Data Sheet © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com VSC8163 G52216-0, Rev 3.3 01/05/00