ETC VSC8074RB

VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
10Gb/s 16-Bit Demultiplexer for
STS-192 and STM-64 Applications
VSC8074
Features
• Performs 1:16 DEMUX Between 10Gb/s HighSpeed Signal and 16 622Mb/s Low-Speed Signals
• Internal Input Terminations
• Industry-Standard 80-Pin PQFP Package
• Fully Differential Low-Speed Interface
• Proven E/D Mode GaAs Technology
• Industry Standard –5.2V Power Supply
• Supports STS-192 SONET Applications
• 50Ω Output Drive Capability
Typical System Block Diagram
PU
PD
D0 - D15±
Frame
Processor
Q0 - Q15±
DI±
VSC8073
CLK16I±
DOUT±
E/O
O/E
CLKI
Frame
Processor
VSC8074
CLK16O±
CLK16O±
CLKI
General Description
The VSC8074 accepts a differential 10Gb/s serial input data stream (DI±). Using a 10GHz clock input
(CLKI), the high-speed data stream is demultiplexed into 16 differential 622Mb/s parallel outputs (Q0-Q15±).
In addition to the data outputs, a differential 622MHz clock output (CLK16O±) is provided. The device operates using a –5.2V power supply and is packaged in a thermally-enhanced, standard plastic package.
Functional Block Diagram
Q0+
Q0–
DI+
DI–
1:16
Demultiplexer
CLKI/2
CLKI
G52280-0, Rev. 4.0
3/29/00
DQ
•
•
•
CLKI/16
•
•
•
Q1+
Q1–
Q15+
Q15–
CLK16O+
CLK16O–
Timing
Generator
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 1
VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
10Gb/s 16-Bit Demultiplexer for
STS-192 and STM-64 Applications
VSC8074
Functional Description
Low-Speed Interface
The deserialized data outputs (Q0-Q15±) and divided clock (CLK16O±) are ECL-compatible outputs and
should be terminated with 50Ω resistors to VTT. These low-speed interfaces are realized using ECL levels as
defined in Table 2. The recommended load configuration for the outputs is 50Ω. The internal schematic for the
low speed outputs is shown in Figure 1.
Figure 1: Low-Speed ECL- Output Driverr
VCC
D
QN
D
Q
High-Speed Interface
Serial data inputs (DI±) and bit rate clocks (CLKI) are internally terminated with 50Ω resistors to VCC.
The internal input receiver and termination schemes for the data and clock inputs are shown in Figures 2 and 3,
respectively. The high-speed differential data in (DI±) requirements appear in Table 3. The high-speed clock
input (CLKI) requirements appear in Table 4.
Page 2
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52280-0, Rev. 4.0
3/29/00
VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
10Gb/s 16-Bit Demultiplexer for
STS-192 and STM-64 Applications
VSC8074
Figure 2: High-Speed Data Input Receiver
VCC
50Ω
50Ω
DI+
DI–
1mA
1mA
VEE
Figure 3: High-Speed Clock Input Receiver
VCC
50Ω
CLKI
VEE
Power Supply
The device is typically operated from a single –5.2V supply (VEE). VCC is typically held at ground potential. Decoupling of the power supply is a critical element in maintaining proper operation of the part. It is recommended that VCC be decoupled using a 0.1µF and a 0.01µF capacitor placed in parallel on each VCC pin as
close to the package as possible. If room permits, a 0.001µF capacitor should also be placed in parallel with the
0.1µF and 0.01µF capacitors previously mentioned. Recommended capacitors are low-inductance, ceramic
SMT X7R devices. A 0603 package should be used for the 0.1µF capacitor; the 0.01µF and 0.001µF capacitors
can be either 0603 or 0403 packages.
G52280-0, Rev. 4.0
3/29/00
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 3
VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
10Gb/s 16-Bit Demultiplexer for
STS-192 and STM-64 Applications
VSC8074
Table 1: AC Timing Characteristics (Over Recommended Operating Conditions)
Parameter
Min
Typ
Max
Units
CLK16O Rise and Fall Times
—
200
350
ps
See Figure 7, 20% to 80%
tCLKI
High-Speed Input Clock Period
—
100.46
—
ps
—
tLCLK
Low-Speed Clock Period
—
1607
—
ps
—
DCHSCLK
Duty Cycle of
High-Speed Clock In
40
—
60
%
—
DCLSCLK
Duty Cycle of
Low-Speed Clock In
40
—
60
%
—
tDIR, tDIF
Serial Data Rise and Fall Times
—
30
35
ps
See Figure 7, 20% to 80%
Parallel Data Out
Rise and Fall Times
—
300
—
ps
See Figure 7
tQS
Output Data Valid Time
Before CLK16O
300
—
—
ps
See Figure 4
tQH
Output Data Valid Time
After CLK16O
300
—
—
ps
See Figure 4
tPM
Phase Margin
150
180
—
degrees
tCLK16OR,
tCLK16OF
tQR, tQF
Description
Conditions
At (231– 1) PRBS. See Figure 6.
Figure 4: VSC8074 AC Timing Waveforms
DI±
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
16 Bit Times
CLK16O±
tQS
tQH
Q0 - Q15±
Page 4
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52280-0, Rev. 4.0
3/29/00
VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
10Gb/s 16-Bit Demultiplexer for
STS-192 and STM-64 Applications
VSC8074
Figure 5: Input Timing
(360°)
tCLK
DI±
tPM
Rising edge of CLK
can occur within
this period
CLKI
Rising edge is the active edge
Figure 6: Data Input Sensitivity vs. Phase Margin
AMPLITUDE
500mV
VFLOOR
tPM
PHASE
tOPT
Figure 7: Parametric Measurement Information
Parametric Test Load Circuit
VCC
50Ω
Z0 = 50Ω
Signal
Pin
Serial Output Load
G52280-0, Rev. 4.0
50Ω
tF
tR
VTT
50Ω
Z0 = 50Ω
3/29/00
Z0 = 50Ω
VCC
80%
50%
20%
ECL Output Load
Output Rise and Fall Times
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 5
VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
10Gb/s 16-Bit Demultiplexer for
STS-192 and STM-64 Applications
VSC8074
DC Characteristics (Over Recommended Operating Conditions)
Table 2: ECL Inputs/Outputs
Parameter
Description
Min
Typ
Max
Units
Conditions
VOH
Output HIGH Voltage
–1100
—
–700
mV
Measure into 50Ω Load.
See Figure 7.
VOL
Output LOW Voltage
-2V
—
–1620
mV
50Ω to VTT Load
Min
Typ
Max
Units
500
—
—
mV
At tPM = tOPT. See Figure 6.
200
—
—
mV
At minimum tPM. See Figure 6.
–1.8
–0.5
0.5
V
—
40
50
60
Ω
—
Min
Typ
Max
Units
—
500
—
mV
–1.8
—
+1.8
V
—
40
50
60
Ω
—
Min
Typ
Max
Units
Table 3: High-Speed Data Inputs
Parameter
VFLOOR
VIN
RTERM
Description
Differential Data Input
Input Voltage
Termination Resistor
Conditions
Table 4: High-Speed Clock Inputs
Parameter
VIN
Description
Input Swing, Single-Ended
RINDC
DC Value of CLKI
RTERM
Termination Resistor
Conditions
Peak-to-Peak
Table 5: Power Dissipation
Parameter
Page 6
Description
IEE
Supply Current
—
600
TBD
mA
PD
Power Dissipation
—
3.5
—
W
Conditions
Outputs Open
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
—
G52280-0, Rev. 4.0
3/29/00
VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
10Gb/s 16-Bit Demultiplexer for
STS-192 and STM-64 Applications
VSC8074
Absolute Maximum Ratings(1)
ECL Power Supply Voltage, (VEE) ............................................................................................... –7.0V to +0.7V
DC Input Voltage (low-speed inputs, Q0-Q15±).......................................................................... – 2.5V to +0.5V
Input Voltage, CLKI(2) ................................................................................................................... –2.8V to +2.8V
Input Voltage DI± ........................................................................................................................... –1.8V to +0.5V
Case Temperature Under Bias ....................................................................................................... –55o to + 125oC
Storage Temperature.................................................................................................................... –65°C to +150°C
Recommended Operating Conditions
Power Supply Voltage (VEE) .................................................................................................................–5.2V ±5%
Operating Case Temperature Range (T)(3) ............................................................................................ 0o to 85oC
Notes: (1) CAUTION: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without causing
permanent damage. Functionality at or exceeding the values listed is not implied. Exposure to these values for extended
periods may affect device reliability.
(2) Static voltage on CLKI must be within –1.8V to +1.8V.
(3) Lower limit is ambient temperature and upper limit is case temperature.
G52280-0, Rev. 4.0
3/29/00
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 7
VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
10Gb/s 16-Bit Demultiplexer for
STS-192 and STM-64 Applications
VSC8074
Package Pin Descriptions
VEE
NC
61
NC
NC
63
VCC
VEE
65
NC
VCC
67
DIN+
DIN–
69
VCC
VCC
71
VCC
CLKI
73
VCC
VEE
75
VCC
NC
NC
77
NC
79
NC
Figure 8: Pin Diagram
1
VEE
NC
VCC
59
3
CLK16O–
VEE
VCC
57
5
55
7
53
9
51
11
49
13
47
15
45
17
Q4–
Q4+
NC
VCC
Q3+
VEE
Q12–
VEE
VCC
Q3–
VCC
Q12+
Q2–
Q2+
Q13+
Q13–
Q1–
Q1+
Q14–
VEE
Q0+
VEE
VCC
Q14+
VCC
Q0–
Q15+
Q15–
CLK16O+
43
19
Q5–
Q5+
NC
VEE
VCC
39
VEE
Q6–
37
Q6+
VCC
35
Q7–
33
VEE
Q7+
31
Q8–
Q8+
VCC
29
Q9–
Q9+
27
VEE
Q10–
25
Q10+
23
VCC
Q11–
VEE
Q11+
21
41
Top View
Page 8
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52280-0, Rev. 4.0
3/29/00
VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
10Gb/s 16-Bit Demultiplexer for
STS-192 and STM-64 Applications
VSC8074
Table 6: Pin Identification
Pin
I/O
Pin Description
68, 69
DI±
73
CLKI
6, 7, 9, 10, 12, 13, 15, 16, 22, 23,
25, 26, 28, 29, 31, 32, 34, 35, 37,
38, 42-45, 47, 48, 50-53, 55, 56
Q0-Q15±
OUTPUT—ECL DIFFERENTIAL:
Deserialized parallel data outputs. These outputs are updated at
1/16 of the bit rate.
58, 59
CLK16O±
OUTPUT—ECL DIFFERENTIAL:
Bit rate clock divided by 16.
3, 5, 8, 14, 19, 24, 30, 36, 40, 49,
57, 64, 67, 70-72, 74, 76
VCC
GROUND
1, 4, 11, 17, 21, 27, 33, 39,
41, 46, 54, 60, 65, 75
VEE
POWER SUPPLY: –5.2 nominal.
2, 18, 20, 61-63, 66, 77-80
NC
Do not connect, leave open.
INPUT—HIGH-SPEED DIFFERENTIAL:
Serial data input stream. These inputs are internally terminated.
INPUT—HIGH SPEED CLOCK:
Bit rate clock input. This clock is terminated with 50Ω resistors to
VCC, and is AC-coupled.
Table 7: Pin Descriptions
Pin
Number
Pin
Name
I/O
Level
1
VEE
I
–5.2V nom
2
NC
NA
NA
3
VCC
I
GND
4
VEE
I
–5.2V nom
5
VCC
I
GND
Ground
6
Q15+
O
ECL
Low-speed differential parallel data
7
Q15–
O
ECL
Low-speed differential parallel data
Power supply at –5.2V nominal
Do not connect, leave open.
Ground
Power supply at –5.2V nominal
8
VCC
I
GND
Ground
9
Q14+
O
ECL
Low-speed differential parallel data
10
Q14–
O
ECL
Low-speed differential parallel data
11
VEE
I
–5.2V nom
12
Q13+
O
ECL
Low-speed differential parallel data
13
Q13–
O
ECL
Low-speed differential parallel data
Power supply at –5.2V nominal
14
VCC
I
GND
Ground
15
Q12+
O
ECL
Low-speed differential parallel data
16
Q12–
O
ECL
Low-speed differential parallel data
17
VEE
I
–5.2V nom
G52280-0, Rev. 4.0
3/29/00
Description
Power supply at –5.2V nominal
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
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VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
10Gb/s 16-Bit Demultiplexer for
STS-192 and STM-64 Applications
VSC8074
Table 7: Pin Descriptions
Pin
Number
Pin
Name
I/O
Level
18
NC
NA
NA
19
VCC
I
GND
20
NC
NA
NA
Page 10
Description
Do not connect, leave open.
Ground
Do not connect, leave open.
21
VEE
I
–5.2V nom
22
Q11+
O
ECL
Power supply at –5.2V nominal
Low-speed differential parallel data
23
Q11–
O
ECL
Low-speed differential parallel data
24
VCC
I
GND
Ground
25
Q10+
O
ECL
Low-speed differential parallel data
26
Q10–
O
ECL
Low-speed differential parallel data
27
VEE
I
–5.2V nom
28
Q9+
O
ECL
Power supply at –5.2V nominal
29
Q9–
O
ECL
Low-speed differential parallel data
30
VCC
I
GND
Ground
31
Q8+
O
ECL
Low-speed differential parallel data
32
Q8–
O
ECL
Low-speed differential parallel data
Low-speed differential parallel data
33
VEE
I
–5.2V nom
34
Q7+
O
ECL
Power supply at –5.2V nominal
35
Q7–
O
ECL
Low-speed differential parallel data
36
VCC
I
GND
Ground
37
Q6+
O
ECL
Low-speed differential parallel data
38
Q6–
O
ECL
Low-speed differential parallel data
39
VEE
I
–5.2V nom
40
VCC
I
GND
Low-speed differential parallel data
Power supply at –5.2V nominal
Ground
41
VEE
I
–5.2V nom
42
Q5+
O
ECL
Power supply at –5.2V nominal
Low-speed differential parallel data
43
Q5–
O
ECL
Low-speed differential parallel data
44
Q4+
O
ECL
Low-speed differential parallel data
45
Q4–
O
ECL
46
VEE
I
–5.2V nom
47
Q3+
O
ECL
Low-speed differential parallel data
48
Q3–
O
ECL
Low-speed differential parallel data
49
VCC
I
GND
Ground
50
Q2+
O
ECL
Low-speed differential parallel data
51
Q2+
O
ECL
Low-speed differential parallel data
52
Q1+
O
ECL
Low-speed differential parallel data
53
Q1–
O
ECL
Low-speed differential parallel data
Low-speed differential parallel data
Power supply at –5.2V nominal
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52280-0, Rev. 4.0
3/29/00
VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
10Gb/s 16-Bit Demultiplexer for
STS-192 and STM-64 Applications
VSC8074
Table 7: Pin Descriptions
Pin
Number
Pin
Name
I/O
Level
54
VEE
I
–5.2V nom
55
Q0+
O
ECL
Low-speed differential parallel data
56
Q0–
O
ECL
Low-speed differential parallel data
Power supply at –5.2V nominal
57
VCC
I
GND
Ground
58
CLK16O–
O
ECL
Low-speed differential parallel data
59
CLK16O+
O
ECL
60
VEE
I
–5.2V nom
61
NC
NA
NA
Do not connect, leave open.
62
NC
NA
NA
Do not connect, leave open.
63
NC
NA
NA
Do not connect, leave open.
64
VCC
I
GND
65
VEE
I
–5.2V nom
66
NC
NA
NA
67
VCC
I
GND
68
DI+
I
HS
High-speed differential clock input
69
DI–
I
HS
High-speed differential clock input
70
VCC
I
GND
Ground
71
VCC
I
GND
Ground
72
VCC
I
GND
Ground
73
CLKI
I
HS
74
VCC
I
GND
75
VEE
I
–5.2V nom
76
VCC
I
GND
77
NC
NA
NA
Do not connect, leave open.
78
NC
NA
NA
Do not connect, leave open.
79
NC
NA
NA
Do not connect, leave open.
80
NC
NA
NA
Do not connect, leave open.
G52280-0, Rev. 4.0
3/29/00
Description
Low-speed differential parallel data
Power supply at –5.2V nominal
Ground
Power supply at –5.2V nominal
Do not connect, leave open.
Ground
High-speed single-ended clock input
Ground
Power supply at –5.2V nominal
Ground
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 11
VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
10Gb/s 16-Bit Demultiplexer for
STS-192 and STM-64 Applications
VSC8074
Package Information
80-Pin PQFP Package Drawing
F
G
80
61
1
60
I
20
H
41
21
40
EXPOSED HEATSINK
6.85 – 0.50 DIA
HEATSINK INTRUSION
0.0127 MAX
10¡ TYP
A
D
10¡ TYP
K
0.30 RAD. TYP
0.20 RAD. TYP
A
STANDOFF
0.25 MAX
0.25
0.102 MAX LEAD
COPLANARITY
0¡ — 8¡
0.17 MAX
J
E
NOTES:
Drawing not scale.
All units in mm unless otherwise noted.
Page 12
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52280-0, Rev. 4.0
3/29/00
VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
10Gb/s 16-Bit Demultiplexer for
STS-192 and STM-64 Applications
VSC8074
Package Thermal Conditions
This package has been enhanced with a copper heat slug to provide a low thermal resistance path from the
die to the exposed surface of the heat spreader. Refer to Table 8 for thermal resistance.
Table 8: Thermal Resistance
Symbol
°C/W
Description
θJC
Thermal resistance from junction-to-case.
2.2
θCA
Thermal resistance from case-to-ambient with no airflow,
including conduction through the leads.
25.8
θJA
Thermal resistance from junction-to-ambient
28
Thermal Resistance with Airflow
Table 9 shows the thermal resistance with airflow. This thermal resistance value reflects all the thermal
paths including through the leads in an environment where the leads are exposed. The temperature difference
between the ambient airflow temperature and the case temperature should be the worst-case power of the device
multiplied by the thermal resistance.
Table 9: Thermal Resistance with Airflow
Airflow (lfpm)
θCA (oC/W)
100
24
200
21
400
19
600
17
Maximum Ambient Temperature Without Heatsink
The worst-case ambient temperature without the use of a heatsink is given by:
TA(MAX) = TC(MAX) – P (MAX) θCA
where,
θCA = Theta case-to-ambient at appropriate airflow
ΤA (MAX) = Ambient air temperature
ΤC(MAX) = Case temperature (85°C)
P(MAX) = Power (4.0W)
G52280-0, Rev. 4.0
3/29/00
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 13
VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
10Gb/s 16-Bit Demultiplexer for
STS-192 and STM-64 Applications
VSC8074
Ordering Information
The order number for this product is formed by a combination of the device number, and package type.
VSC80xx
xx
Device Type
VSC8074: 1:16 Demux
Package
RB 80-Pin PQFP
Notice
Vitesse Semiconductor Corporation reserves the right to make changes in its products specifications or
other information at any time without prior notice. Therefore the reader is cautioned to confirm that this
datasheet is current prior to placing orders. The company assumes no responsibility for any circuitry described
other than circuitry entirely embodied in a Vitesse product.
Warning
Vitesse Semiconductor Corporation’s product are not intended for use in life support appliances, devices or
systems.
Page 14
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52280-0, Rev. 4.0
3/29/00