VITESSE SEMICONDUCTOR CORPORATION Advance Product Information 2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery VSC8162 Features • 2.488Gb/s 1:16 Demux with Integrated Clock and Data Recovery • Recovered Clock and Data Available • Differential Low Speed Outputs • Differential/Single-ended Reference Clock • Loss of Lock Detection • Monolithic Phase Locked Loop • Digitally Adjustable Serial Data Sampling Point • Meets SONET OC-48 and SDH STM-16 Jitter Tolerance Requirements General Description The VSC8162 combines a clock recovery unit (CRU) with a 1:16 demultiplexer on a single chip to directly generate 16-bit wide data from an incoming 2.488Gb/s NRZ data stream. An on-chip Phase Locked Loop (PLL) generates a 2.488GHz clock which remains phase locked to the incoming data. The incoming data is retimed and demultiplexed to a 16-bit word. A Loss of Lock (LOL) signal indicates gross conditions where incoming data no longer has sufficient transitions to keep the CRU in lock. VSC8162 Functional Block DIagram RTDO+ RTDO– DINVERT D0+ D0– Data Retime DI– REFCK+ Clock Recovery REFCK– 5 Output Register DI+ D15+ D15– PARITY+ PADJ[4:0] PARITY– Divide by 16 CLK16+ CLK16– CLKO+ CLKO– LOL NOREF G52209-0, Rev. 2.0 9/14/98 VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 1 VITESSE SEMICONDUCTOR CORPORATION 2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery Advance Product Information VSC8162 Functional Description Clock Recovery: The clock recovery unit (CRU) consists of a phase detector, voltage controlled oscillator (VCO), loop filter and frequency control unit (FCU). The components of the CRU are fully integrated on the VSC8162. A 19.44MHz reference clock (REFCLK) is required for proper operation of the Clock Recovery Unit (CRU). Jitter tolerance of the CRU is well above the SONET and SDH jitter tolerance masks. In addition, the recovered high speed clock is output on the CLKO pins. Incoming data is presented to both the clock recovery circuit and the data retiming circuit. When the CRU is in lock mode, a phase detector circuit is effective. When there is a phase error between the incoming data and the on-chip VCO, the phase detector output raises or lowers the voltage on the loop filter to null the phase difference. The frequency control unit (FCU) monitors the frequency difference between the reference clock, REFCK, and the recovered clock. At the time that the VCO frequency, fVCO, and the 128x REFCK frequency, 128 x fREF, differ by less than 1 MHz, the FCU only passively monitors the frequency difference continuously without sending any corrections to the loop filter. In the event of the loss of an input signal, or if the input is switching randomly, the VCO will drift in one direction. At the time that fVCO and 128 x fREF differ by more than 1 MHz, the FCU will maintain the VCO frequency to be at approximately 1MHz off the frequency of 128 x fREF, and the lock detector will assert the LOL output. LOL is designed to be asserted from between 2.3us and 100us after the interruption of data. When NRZ data is again presented at the data input, the phase detector will permit the VCO to lock to the incoming data. Hysteresis is provided which delays the deassertion of LOL until approximately 160us following the restoration of valid data. The NOREF output will go high to indicate that there is no signal on the REFCK input, or that the REFCK is more than approximately 25% above or below the expected value. Retiming: The retiming decision circuit functions as a D Flip Flop. The recovered clock nominally clocks the decision circuit in the center of the data eye. Internally, the recovered clock is duplicated to create 32 copies, with a phase difference between each of 1/32 of a unit interval. The PADJ[4:0] inputs select which of the 32 phases are to be used to retime the data. Certain lightwave systems employing optical amplifiers suffer from noise in the leading edge of the data eye. Therefore these systems may achieve their lowest Bit Error Rate (BER) by delaying the retiming point until later in the eye. The PADJ inputs can be strapped to generate a fixed delay or the customer can develop a dynamic circuit which can select the optimum retiming point during a training sequence. The retimed high speed data can be monitored using the RTDO pins. Figure 1 and Table 1 indicate how the PADJ pins adjust the sampling point in the data eye. The step size of each unit interval is approximately 12.5ps. The values in Table 1 are not exact and should be used only as an approximation of the expected delay. Due to environmental variations, the actual measured value at any point could vary by as much as +/- 1 step size. It should be noted that PADJ[4:0] = ‘00000’ always corresponds to the sampling center point and that the delay between unit intervals increases monotonically. Page 2 VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52209-0, Rev. 2.0 9/14/98 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information 2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery VSC8162 PADJ are ECL compatible inputs (see Table 6). If the pins are left floating, the inputs will default to the logic low state. In order to set to a logic high level, the inputs can be tied directly to VCC without the need for a resistor. Table 1: Retiming Phase Adjust Settings PS From Center PADJ3 PADJ2 PADJ1 PADJ0 0 0 0 0 0 0.00 0.0 0 0 0 0 1 11.25 12.6 0 0 0 1 0 22.50 25.1 0 0 0 1 1 33.75 37.7 0 0 1 0 0 45.00 50.2 0 0 1 0 1 56.25 62.8 0 0 1 1 0 67.50 75.4 0 0 1 1 1 78.75 87.9 0 1 0 0 0 90.00 100.5 0 1 0 0 1 101.25 113.0 0 1 0 1 0 112.50 125.6 0 1 0 1 1 123.75 138.2 0 1 1 0 0 135.00 150.7 0 1 1 0 1 146.25 163.3 0 1 1 1 0 157.50 175.8 0 1 1 1 1 168.75 188.4 1 0 0 0 0 180.00 201.0 1 0 0 0 1 -168.75 -188.4 1 0 0 1 0 -157.50 -175.8 1 0 0 1 1 -146.25 -163.3 1 0 1 0 0 -135.00 -150.7 1 0 1 0 1 -123.75 -138.2 1 0 1 1 0 -112.50 -125.6 1 0 1 1 1 -101.25 -113.0 1 1 0 0 0 -90.00 -100.5 1 1 0 0 1 -78.75 -87.9 1 1 0 1 0 -67.50 -75.4 1 1 0 1 1 -56.25 -62.8 1 1 1 0 0 -45.00 -50.2 1 1 1 0 1 -33.75 -37.7 1 1 1 1 0 -22.50 -25.1 1 1 1 1 1 -11.25 -12.6 G52209-0, Rev. 2.0 9/14/98 Degrees From Center PADJ4 VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 3 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information 2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery VSC8162 Figure 1: Retiming Offset DI Sampling point at the center of the eye PH_ADJ[4:0] = 00000 Sampling point delayed ~50ps from the center of the eye PH_ADJ[4:0] = 00100 1:16 Demultiplexer The demultiplexer inside of the VSC8162 consists of a 1:16 demultiplexer and timing circuitry which generates a divide-by-16 clock from the high speed clock input. The demultiplexer accepts a serial data stream input (DI+/DI-) at 2.488 Gb/s and deserializes it into 16 parallel differential outputs (D0..D15). The timing parameters of the parallel data outputs (D0..D15) are specified with respect to the falling edge of CLK16, so that CLK16 can be used to clock the destination of D0..D15. The parity output of the demultiplexer is the XOR of all 16 parallel outputs. The DINVERT input is an ECL input (see Table 6) which can be used to invert the sense of the data through the demultiplexer. If DINVERT is left floating, it defaults to the low state, which is the state that corresponds to normal operation (no data inversion). FILTI, FILTO Pins The FILTI and FILTO pins are used to provide additional capacitance to the loop filter of the VCO. To optimize the VCO’s performance, it is recommended that 0.1µF, size 0805 capacitors are connected between the FILTI+ and FILTI- pins, as well as the FILTO+ and FILTO- pins. Supplies The VSC8161 is designed to operate with VEE = -5.2V, VTT = -2.0V and VCC = GND (0.0V). However, the part can be operated in an all positive supply environment, or a mixed positive and negative supply environment. To operate in an all positive supply environment, each of the supply voltages must be shifted up by 5.2V such that VEE will now be GND, VTT = +3.2V and VCC = +5.2V. To operate in a mixed positive and negative supply environment, each of the supply voltages must be shifted up by 2.0V such that VTT will now be GND, VEE = -3.2V and VCC = +2.0V. Bear in mind that termination voltages must be adjusted to reflect any shift in supply voltages. Page 4 VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52209-0, Rev. 2.0 9/14/98 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information 2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery VSC8162 Interface Recommendations REFCK+, REFCK– Inputs Internal biasing will position the reference voltage of approximately -1.32V on both the true and complement inputs. This input can either be DC coupled or AC coupled; it can also be driven single-ended or differentially. Figure 2 shows the configuration for single-ended, AC-coupling operation. In the case of direct coupling and single-ended input, it is recommended that a stable VREF for ECL levels be used for the complementary input. Figure 2: Single-ended AC Coupling for REFCK+, REFCK– Inputs Chip Boundary VCC = GND ZO CIN REFCK+ -1.32V -1.32V RT = ZO R| | = 1kΩ (Approx.) VTT CSE VTT REFCK– VTT = -2V CIN TYP = 0.1µF CSE TYP = 0.1µF for single ended applications. (Capacitor values are selected for REFCLK = 19.44 MHz) G52209-0, Rev. 2.0 9/14/98 VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 5 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information 2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery VSC8162 High Speed Data Input: The data input receiver is internally terminated with a 100 ohm resistor between the true and complement inputs. The inputs are internally biased to allow AC coupling. These inputs are recommended to be AC coupled to permit use with a variety of limiting amplifiers. See Figure 3. Figure 3: High-Speed Data Input Termination Limiting Amp 8162 Zo = 50Ω 0.1 µF DI 100Ω Zo = 50Ω 0.1 µF DIN High Speed Data Output: A high speed data output termination scheme is shown in Figure 4. In order to disable the high speed data switching, the 422Ω pulldown resistors can be removed. Figure 4: High-Speed Data Output Termination 8162 Laser Driver VTERM VEE 422Ω 422Ω VEE Page 6 Zo = 50Ω DO DON 0.1 µF 0.1 µF 50Ω 50Ω VTERM VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52209-0, Rev. 2.0 9/14/98 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information 2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery VSC8162 High Speed Clock Output The high speed clock output is provided for test and measurement purposes. A termination method for the high speed clock output is shown in Figure 5. In addition to the AC coupling method shown, the device may also be DC coupled with a 50Ω resistor connected to VCC. By using these termination methods, a nominal voltage swing of 200mV - 300mV, single-ended peak-to-peak, can be expected. In order to reduce noise on the board, the clock output can be disabled by using the CKOE pin. CKOE is a normal ECL input, which, when left floating, will default to a low level (output disabled). In order to set the CKOE pin to a logic high, it can be tied directly to VCC without the need for a resistor. Figure 5: High-Speed Clock Output Termination 8162 VCC CLK CLKN 270Ω 270Ω VCC G52209-0, Rev. 2.0 9/14/98 VTERM Zo = 50Ω 0.1 uF 50Ω Zo = 50Ω 0.1 uF 50Ω VTERM VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 7 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information 2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery VSC8162 D[0-15]+/-, PARITY+/-, CLK16+/- Outputs: The D[0:15]+/-, PARITY+/-, and CLK16+/- output drivers are special-purpose output drivers designed for low power dissipation. Four possible termination schemes are shown in Figures 6, 7, 8, and 9. Figures 6 and 7 are the preferred termination methods. Figure 6 indicates a DC-differential termination method, and Figure 7 is true differential termination. For interfacing the VSC8162 device directly to a VSC8161, Figure 6 is preferred since the DC differential method does not force a DC common mode level at the receiver. The VSC8161 input receivers have internal DC bias resistor that allow them to set their own DC bias level. Figure 6: Low-Speed Output Termination #1 Receiving Device 8162 Zo = 50Ω 0.1 µF Zo = 50Ω 0.1 µF 50Ω 0.1 µF 50Ω Figure 7: Low-Speed Output Termination #2 Receiving Device 8162 Zo = 50Ω 0.1 µF 100Ω Zo = 50Ω Page 8 0.1 µF VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52209-0, Rev. 2.0 9/14/98 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information 2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery VSC8162 Figure 8 is a DC coupled termination method and provides the best low frequency response. For applications with low data transition density, a DC coupling termination such as that shown in Figure 6 may be required. Figure 8: Low-Speed Output Termination #3 8162 Receiving Device -1.1V Zo = 50Ω 50Ω Zo = 50Ω 50Ω -1.1V Figure 9 is provided to show that after the AC coupling capacitors, the 50Ω termination resistors can be terminated to any DC voltage, shown in Figure 9 by the ground symbol. Please note that Figure 9 will not work when interfacing the VSC8162 directly to the VSC8161. Figure 9: Low-Speed Output Termination #4 8162 G52209-0, Rev. 2.0 9/14/98 Receiving Device Zo = 50Ω 0.1 µF 50Ω Zo = 50Ω 0.1 µF 50Ω VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 9 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information 2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery VSC8162 AC Characteristics (Over recommended operating conditions) Table 2: High Speed Clock and Data Outputs Timing Characteristics Parameters Description Min Typ Max Units Conditions tpd Center of output data eye from falling edge of CLKO+ -75 — +75 ps — tDH CLKO period — 401.9 — ps — tr,tf RTDO± rise and fall times — — 150 ps. 20% to 80% into 50Ω load. tr,tf CLKO± rise and fall times — — 135 ps 20% to 80% into 50Ω load. Figure 10: VSC8162 High Speed Output Interface tDH CLKO+ High Speed Clock Output tpd RTDO+/– tDH Retimed Data Output Table 3: D[0-15]+/-, PARITY+/-, CLK16+/- Output Specifications Parameters MIN Typ MAX Unit Output level 600 — 1100 mV tr,tf Output Rise/Fall Times — — 1200 ps 20% to 80% into 50Ω load tCQ Clock-to-Data -0.2 — 1.8 ns — tDC CLK16 duty cycle 45 — 55 % — tD CLK16 period — 6.4 — ns — VDIFF Description Conditions — Figure 11: VSC8162 Parallel Interface tD DI+/- D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 High speed differential serial data input Serialized Data tD CLK16+ Parallel data clock output tCQ D(0...15),PARITY Parallel data outputs Page 10 VALID DATA (1) VALID DATA (2) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52209-0, Rev. 2.0 9/14/98 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information 2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery VSC8162 Table 4: PLL Parameters Parameters Description Min Typ Max Units Conditions RCd REFCK Duty Cycle 45 — 55 % — RCf REFCK Frequency — 19.44 — MHz — ∆fRC REFCK Frequency Tolerance -100 — +100 ppm tACQ Acquisition time — — 20 µs With valid reference clock — tset Loss of Lock set time 2.3 — 100 µs From data interruption tclr Loss of Lock clear time 125 — 250 µs From data restoration tdensity Maximum zero-timing-content period — 1200 — UI For 0 BER tjitter Jitter generationa — 3.6 4.0 ps rms ttolerance Jitter toleranceb — Exceeds mask in Figure 9 — a. Measured at the HS clock output for jitter in the 12 kHz to 20 MHz band. Assume 1.2 ps rms input data jitter b. Error-free operation guaranteed when electrical input signal is subject to jitter specified by mask in Figure 9. Figure 12: VSC8162 Jitter Mask Specification slope = -20 dB/decade sinusoidal input jitter amplitude (UI p-p) 30 15 VSC8162 Mask 3.0 1.5 SONET/SDH Mask 0.30 0.15 10 600 6k 100k 1000k frequency (Hz) G52209-0, Rev. 2.0 9/14/98 VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 11 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information 2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery VSC8162 DC Characteristics (Over Recommended Operating Conditions) Table 5: High Speed Data and Clock Inputs and Outputs Parameters VDIFF VCM RIN ∆VOD VODCM ∆VOC VOCCM Description Serial input absolute voltage differential peak-to-peak swing (DI±) Input common mode range Input Resistance between DI+ and DIData Output voltage swing Data Output common mode Clock Output voltage swing Clock Output common mode Min Typ Max Units Conditions 200 — 1200 mV — -1.6 — -1 V — 80 100 120 Ohm — 600 — 1200 mV — -1.6 — -1 V — 100 — 300 mV — -0.2 — 0 V — Min Typ Max Units -1100 — -700 mV VTT — -1620 mV 50 ohms to VTT 50 ohms to VTT Table 6: Low Speed ECL Inputs and Outputs Parameters VOH VOL VIH VIL IIH IIL Description Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage Input HIGH current Input LOW current Conditions -1040 — -600 mV — VTT — -1600 mV — — — 200 µA — -50 — — µA — Min Typ Max Units -5.46 — -4.94 V — -2.1 — -1.9 V — — — 4.2 W — — 620 mA — — 380 mA Outputs open Outputs open Outputs open Table 7: Power Supply Parameters VEE VTT PD IEE ITT Page 12 Description Supply voltage Supply voltage Power dissipation Supply Current Supply Current Conditions VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52209-0, Rev. 2.0 9/14/98 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC8162 2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery Absolute Maximum Ratings1 Power Supply Voltage, (VEE) .................................................................................................. -7V to VCC+0.5V Power Supply Voltage, (VTT) ............................................................................................................ -3V to 0.5V DC Input Voltage (Differential inputs) .........................................................................................-2.5V to +0.5V Output Current (Differential Outputs)....................................................................................................+/-50mA Case Temperature Under Bias ......................................................................................................-55o to +125oC Storage Temperature.................................................................................................................. -65oC to +150oC Recommended Operating Conditions Power Supply Voltage, (VEE) ...............................................................................................................-5.2V+5% Power Supply Voltage, (VTT) ...............................................................................................................-2.0V+5% Operating Temperature Range ...........................................................0oC Ambient to +85oC Case Temperature Notes: (1) CAUTION: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods may affect device reliability. G52209-0, Rev. 2.0 9/14/98 VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 13 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information 2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery VSC8162 Package Pin Descriptions 103 104 105 106 109 108 107 110 114 113 112 111 115 117 116 118 120 119 121 123 122 125 124 80 79 25 26 78 77 27 28 29 30 76 75 74 73 31 32 33 34 72 71 70 69 35 36 37 38 68 67 66 65 VCC VTT VTT D3D3+ D4D4+ VCC VTT D5D5+ D6D6+ VCC VTT VTT D7D7+ D8D8+ VTT VCC D9D9+ D10D10+ VTT VCC D11D11+ D12D12+ VTT VTT VCC VCC NC VSUB FILTO+ FILTI+ FILTIFILTOVEEANA VCCANA VCC NC NC NC NC LOL NOREF VTT VTT VCC PARITY+ PARITYD15+ D15VCC VTT D14+ D14D13+ D13- 64 23 24 63 84 83 82 81 62 19 20 21 22 61 88 87 86 85 58 59 60 15 16 17 18 57 92 91 90 89 53 54 55 56 11 12 13 14 52 94 93 50 51 9 10 49 96 95 47 48 7 8 46 100 99 98 97 44 45 3 4 5 6 42 43 102 101 41 1 2 39 40 VCC VCC NC VCC VEE VCC VCC VEE VCC VEE VCC RTDORTDO+ VCC VEE VCC VEE VCC DIDI+ VCC NC VEE VEEANA VCCANA PADJ4 PADJ3 PADJ2 PADJ1 PADJ0 VTT NC NC NC NC NC VCC VCC 126 128 127 VEE VCC CLKOCLKO+ VCC VEE VTT CKOE DINVERT NC REFCK+ REFCKVTT VCC VTT CLK16CLK16+ VTT D0D0+ VTT VCC D1D1+ D2D2+ Figure 13: Package Pin Diagram Page 14 VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52209-0, Rev. 2.0 9/14/98 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information 2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery VSC8162 Table 8: Package Pin Identification Signal Name Pin # I/O VCC 1 - Power supply (GND typ.) VCC 2 - Power supply (GND typ.). NC 3 - Do not connect, leave open VCC 4 - Power supply (GND typ.) VEE 5 - Power supply (-5.2V typ.) VCC 6 - Power supply (GND typ.) VCC 7 - Power supply (GND typ.) VEE 8 - Power supply (-5.2V typ.) VCC 9 - Power supply (GND typ.) VEE 10 - Power supply (-5.2V typ.) VCC 11 - Power supply (GND typ.) RTDO- 12 O High speed data output (complement) RTDO+ 13 O High speed data output (true) VCC 14 - Power supply (GND typ.) VEE 15 - Power supply (-5.2V typ.) VCC 16 - Power supply (GND typ.) VEE 17 - Power supply (-5.2V typ.) VCC 18 - Power supply (GND typ.) DI- 19 I High speed data input (complement) DI+ 20 I High speed data input (true) VCC 21 - Power supply (GND typ.) NC 22 - Do not connect, leave open VEE 23 - Power supply (-5.2V typ.) VEEANA 24 - Power supply for analog circuits (-5.2V typ.) VCCANA 25 - Power supply for analog circuits (GND typ.) PADJ4 26 I Decision circuit phase adjust PADJ3 27 I Decision circuit phase adjust PADJ2 28 I Decision circuit phase adjust PADJ1 29 I Decision circuit phase adjust PADJ0 30 I Decision circuit phase adjust VTT 31 - Power supply (-2.0V typ.) NC 32 - Do not connect, leave open NC 33 - Do not connect, leave open NC 34 - Do not connect, leave open NC 35 - Do not connect, leave open NC 36 - Do not connect, leave open G52209-0, Rev. 2.0 9/14/98 Description VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 15 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information 2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery VSC8162 Signal Name Pin # I/O VCC 37 - Power supply (GND typ.) Power supply (GND typ.) Page 16 Description VCC 38 - FILTO+ 39 I/O Connect to FILTI+ with 0.1 µF, 0805 capacitor FILTI+ 40 I/O Connect to FILTO+ with 0.1 µF, 0805 capacitor FILTI- 41 I/O Connect to FILTO- with 0.1 µF, 0805 capacitor FILTO- 42 I/O Connect to FILTI- with 0.1 µF, 0805 capacitor VEEANA 43 - Power supply for analog circuits (-5.2V typ.) VCCANA 44 - Power supply for analog circuits (GND typ.) VCC 45 - Power supply (GND typ.) NC 46 - Do not connect, leave open NC 47 - Do not connect, leave open NC 48 - Do not connect, leave open NC 49 - Do not connect, leave open LOL 50 O Loss of lock NOREF 51 O Loss of reference VTT 52 - Power supply (-2.0V typ.) VTT 53 - Power supply (-2.0V typ.) VCC 54 - Power supply (GND typ.) PARITY+ 55 O Parity bit (true) PARITY- 56 O Parity bit (complement) D15+ 57 O Low-speed Differential Parallel Data (true) D15- 58 O Low-speed Differential Parallel Data (complement) VCC 59 - Power supply (GND typ.) VTT 60 - Power supply (-2.0V typ.) D14+ 61 O Low-speed Differential Parallel Data (true) D14- 62 O Low-speed Differential Parallel Data (complement) D13+ 63 O Low-speed Differential Parallel Data (true) D13- 64 O Low-speed Differential Parallel Data (complement) VSUB 65 - Substrate Voltage (connect to lowest supply voltage, i.e., VEE) NC 66 - Do not connect, leave open VCC 67 - Power supply (GND typ.) VCC 68 - Power supply (GND typ.) VTT 69 - Power supply (-2.0V typ.) VTT 70 - Power supply (-2.0V typ.) D12+ 71 O Low-speed Differential Parallel Data (true) D12- 72 O Low-speed Differential Parallel Data (complement) D11+ 73 O Low-speed Differential Parallel Data (true) D11- 74 O Low-speed Differential Parallel Data (complement) VCC 75 - Power supply (GND typ.) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52209-0, Rev. 2.0 9/14/98 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC8162 2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery Signal Name Pin # I/O VTT 76 - Power supply (-2.0V typ.) D10+ 77 O Low-speed Differential Parallel Data (true) D10- 78 O Low-speed Differential Parallel Data (complement) D9+ 79 O Low-speed Differential Parallel Data (true) D9- 80 O Low-speed Differential Parallel Data (complement) VCC 81 - Power supply (GND typ.) VTT 82 - Power supply (-2.0V typ.) D8+ 83 O Low-speed Differential Parallel Data (true) D8- 84 O Low-speed Differential Parallel Data (complement) D7+ 85 O Low-speed Differential Parallel Data (true) D7- 86 O Low-speed Differential Parallel Data (complement) VTT 87 - Power supply (-2.0V typ.) VTT 88 - Power supply (-2.0V typ.) VCC 89 - Power supply (GND typ.) D6+ 90 O Low-speed Differential Parallel Data (true) D6- 91 O Low-speed Differential Parallel Data (complement) D5+ 92 O Low-speed Differential Parallel Data (true) D5- 93 O Low-speed Differential Parallel Data (complement) VTT 94 - Power supply (-2.0V typ.) VCC 95 - Power supply (GND typ.) D4+ 96 O Low-speed Differential Parallel Data (true) D4- 97 O Low-speed Differential Parallel Data (complement) D3+ 98 O Low-speed Differential Parallel Data (true) D3- 99 O Low-speed Differential Parallel Data (complement) VTT 100 - Power supply (-2.0V typ.) VTT 101 - Power supply (-2.0V typ.) VCC 102 - Power supply (GND typ.) D2+ 103 O Low-speed Differential Parallel Data (true) D2- 104 O Low-speed Differential Parallel Data (complement) D1+ 105 O Low-speed Differential Parallel Data (true) D1- 106 O Low-speed Differential Parallel Data (complement) VCC 107 - Power supply (GND typ.) VTT 108 - Power supply (-2.0V typ.) D0+ 109 O Low-speed Differential Parallel Data (true) D0- 110 O Low-speed Differential Parallel Data (complement) VTT 111 - Power supply (-2.0V typ.) CLK16+ 112 O Low-speed clock f = 155.52 MHz (true) CLK16- 113 O Low-speed clock f = 155.52 MHz (complement) VTT 114 - Power supply (-2.0V typ.) G52209-0, Rev. 2.0 9/14/98 Description VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 17 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information 2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery VSC8162 Signal Name Pin # I/O Description VCC 115 - Power supply (GND typ.) VTT 116 - Power supply (-2.0V typ.) REFCK- 117 I 19.44 MHz Reference Clock (complement) REFCK+ 118 I 19.44 MHz Reference Clock (true) NC 119 - Do not connect, leave open DINVERT 120 I Invert Parallel Data Outputs (Logic High = Invert) CKOE 121 I Test input (logic high enables 2.488 GHz clock output) VTT 122 - Power supply (-2.0V typ.) VEE 123 - Power supply (-5.2V typ.) VCC 124 - Power supply (GND typ.) CLKO+ 125 O Test signal - low-swing high speed clock output (true) CLKO- 126 O Test signal - low-swing high speed clock output (complement) VCC 127 - Power supply (GND typ.) VEE 128 - Power supply (-5.2V typ.) Table 9: Power Supply Summary Signal Name Pin # Description VEE 5,8,10,15,17,23,123,128 VEEANA 24,43 Power supply (-5.2V typ.) VTT 31,52,53,60,69,70,76, 82,87,88,94,100,101, 108,111,114,116,122 Power supply (-2.0V typ.) VCC 1,2,4,6,7,9,11,14,16,18, 21,37,38,45,54,59,67, 68,75,81,89,95,102,107, 115,124,127 Power supply (GND typ.) VCCANA 25,44 VSUB 65 Power supply for analog circuits (-5.2 typ.) Power supply for analog circuits (GND typ.) Substrate Voltage (connect to lowest supply voltage, i.e., VEE) All supplies which reference the same voltage may be connected to the same power supply plane. The VCCANA, and VEEANA are noise sensitive supplies. Appropriate power supply noise suppression should be applied to optimize the performance of the device. Page 18 VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52209-0, Rev. 2.0 9/14/98 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information 2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery VSC8162 Package Information 128 PQFP Package Drawings PIN 128 PIN 102 PIN 1 RAD. 2.92 ± .50 (2) E1 EXPOSED INTRUSION 0.127 MAX. E 2.54 ± .50 EXPOSED HEATSINK PIN 38 PIN 64 D1 D TOP VIEW Key mm Tolerance A 2.35 MAX A1 0.25 MAX A2 2.00 +.10 D 17.20 ±.20 D1 14.00 ±.10 E 23.20 ±.20 E1 20.00 ±.10 L .88 +.15/-.10 e .50 BASIC b .22 ±.05 θ 0°-7° R .30 TYP R1 .20 TYP 10° TYP. A2 A e A1 10° TYP. R R1 θ1 A Notes: 1) 2) 3) Drawing is not to scale All dimensions in mm Package represented is also used for the 64, 80, & 100 PQFP packages. Pin count drawn does not reflect the 128 Package. G52209-0, Rev. 2.0 9/14/98 STANDOFF A1 .25 θ 0.17 MAX. b LEAD COPLANARITY L VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 NOTES: Package #: 101-322-5 Issue #: 2 Page 19 VITESSE SEMICONDUCTOR CORPORATION 2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery Advance Product Information VSC8162 Notice This document contains information about a product during its fabrication or early sampling phase of development. The information contained in this document is based on design targets, simulation results or early prototype test results. Characteristic data and other specifications are subject to change without notice. Therefore the reader is cautioned to confirm that this datasheet is current prior to design or order placement. Warning Vitesse Semiconductor Corporation’s product are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without written consent is prohibited. Page 20 VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52209-0, Rev. 2.0 9/14/98