Preliminary W49V002A 256K x 8 CMOS FLASH MEMORY WITH LPC INTERFACE GENERAL DESCRIPTION The W49V002A is a 2-megabit, 3.3-volt only CMOS flash memory organized as 256K × 8 bits. The device can be programmed and erased in-system with a standard 3.3V power supply. A 12-volt VPP is not required. The unique cell architecture of the W49V002A results in fast program/erase operations with extremely low current consumption. This device can operate at two modes, Programmer bus interface mode and LPC bus interface mode. As in the Programmer interface mode, it acts like the traditional flash but with a multiplexed address inputs. But in the LPC interface mode, this device complies with the Intel LPC specification 1.0. The device can also be programmed and erased using standard EPROM programmers. FEATURES bytes, 64K bytes, 64K bytes each) •Single 3.3-volt operations: − 3.3-volt Read • Low power consumption − 3.3-volt Erase − Active current: 25 mA (typ.) − 3.3-volt Program − Standby current: 20 µA (typ.) • Fast Program operation: − Byte-by-Byte programming: 50 µS (typ.) • Fast Erase operation: 150 mS (typ.) • Automatic program and erase timing with internal VPP generation • End of program or erase detection − Toggle bit • Endurance: 10K cycles (typ.) • Twenty-year data retention • Hardware data protection − Data polling • Latched address and data − #TBL & #WP serve as hardware protection • TTL compatible I/O • One 16K bytes Boot Block with lockout • Available packages: 32L PLCC and 32L protection STSOP • Two 8K bytes Parameter Blocks • Four Main Memory Blocks (with 32K bytes, 64K -1 - Publication Release Date: April 2001 Revision A1 Preliminary W49V002A PIN CONFIGURATIONS A 8 ^ G P I 2 v A 9 ^ # G R P E I S V 3 E N D v T C D 4 3 2 PIN DESCRIPTION R # C ^ C L K v SYMB A 1 0 ^ G P I 4 v 5 29 MODE A6(GPI0) 6 28 GND A5(#WP) 7 27 NC A4(#TBL) 8 26 NC 32-pin PLCC A3(RSV) 9 25 VDD A2(RSV) 10 24 #OE(#INIT) A1(RSV) 11 23 #WE(#LFRAM) A0(RSV) 12 22 NC 13 21 DQ7(RSV) 14 15 16 17 18 19 20 D D G Q Q N 1 2 D ^ ^ L L A A D D 1 2 v v D D D Q Q Q 3 4 5 ^ ^ ^ L R R A S S D V V 3 v v v D Q 6 ^ R S V v NC NC 1 32 #OE(#INIT) 2 31 #WE(#LFRAM) NC 3 30 NC GND 4 29 DQ7(RSV) MODE 5 28 DQ6(RSV) A10(GPI4) 6 27 DQ5(RSV) R/#C(CLK) 7 VDD NC 8 26 32-pin TSOP DQ4(RSV) 25 DQ3(LAD3) 24 GND 23 DQ2(LAD2) #RESET 9 10 A9(GPI3) 11 22 DQ1(LAD1) A8(GPI2) 12 21 DQ0(LAD0) A7(GPI1) 13 20 A0(RSV) A6(GPI0) 14 19 A1(RSV) A5(#WP) 15 18 A2(RSV) A4(#TBL) 16 17 A3(RSV) BLOCK DIAGRAM #WP #TBL CLK LAD[3:0] #LFRAM MODE LPC Interface BOOT BLOCK 16K BYTES PARAMETER BLOCK1 8K BYTES PARAMETER BLOCK2 8K BYTES #INIT #RESET MAIN MEMORY BLOCK1 32K BYTES R/#C A[10:0] DQ[7:0] #OE #WE Programmer Interface PIN NAME PGM LPC MODE * * #RESET * * Reset #INIT * Initialize #TBL * Top Boot Block Lock #WP * Write Protect CLK * CLK Input GPI[4:0] * General Purpose Inputs LAD[3:0] * Address/Data Inputs #LFRAM * LPC Cycle Initial Interface Mode Selection 1 32 31 30 A7(GPI1) DQ0(LAD0) INTERFACE MAIN MEMORY BLOCK2 64K BYTES MAIN MEMORY BLOCK3 64K BYTES MAIN MEMORY BLOCK4 64K BYTES 3FFFF 3C000 3BFFF 3A000 39FFF 38000 37FFF 30000 2FFFF 20000 1FFFF 10000 0FFFF 00000 -2 - R/#C * Row/Column Select A[10:0] * Address Inputs DQ[7:0] * Data Inputs/Outputs #OE * Output Enable #WE * Write Enable VDD * * Power Supply GND * * Ground RSV * * Reserve Pins NC * * No Connection Preliminary W49V002A FUNCTIONAL DESCRIPTION Interface Mode Selection And Description This device can be operated in two interface modes, one is Programmer interface mode, the other is LPC interface mode. The MODE pin of the device provides the control between these two interface modes. These interface modes need to be configured before power up or return from #RESET. When MODE pin is set to high state, the device is in the Programmer mode; while the MODE pin is set to low state(or leaved no connection), it is in the LPC mode. In Programmer mode, this device just behaves like traditional flash parts with 8 data lines. But the row and column address inputs are multiplexed, which go through the address inputs A[10:0]. For LPC mode, It complies with the LPC Interface Specification Revision 1.0. Through LAD[3:0] to communicate with the system chipset . Read(Write) Mode In Programmer interface mode, the read(write) operation of the W49V002A is controlled by #OE (#WE). The #OE (#WE) is held low for the host to obtain(write) data from(to) the outputs(inputs). #OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when #OE is high. As in the LPC interface mode, the read or write is determined by the "bit 1 of CYCLE TYPER+DIR". Reset Operation The #RESET input pin can be used in some application. When #RESET pin is at high state, the device is in normal operation mode. When #RESET pin is at low state, it will halt the device and all outputs will be at high impedance state. As the high state re-asserted to the #RESET pin, the device will return to read or standby mode, it depends on the control signals. Chip Erase Operation The chip-erase mode can be initiated by a six-byte command sequence. After the command loading cycle, the device enters the internal chip erase mode, which is automatically timed and will be completed within fast 100 mS (typical). The host system is not required to provide any control or timing during this operation. If the boot block programming lockout is activated, only the data in the other memory blocks will be erased to FF(hex) while the data in the boot block will not be erased (remains as the same state before the chip erase operation). The entire memory array will be erased to FF(hex) by the chip erase operation if the boot block programming lockout feature is not activated. The device will automatically return to normal read mode after the erase operation completed. Data polling and/or Toggle Bits can be used to detect end of erase cycle. Sector Erase Operation The seven sectors, one boot block and two parameter blocks and four main blocks, can be erased individually by initiating a six-byte command sequence. Sector address is latched on the falling #WE edge of the sixth cycle, while the 30(hex) data input command is latched at the rising edge of #WE. After the command loading cycle, the device enters the internal sector erase mode, which is automatically timed and will be completed within fast 150 mS (typical). The host system is not required to provide any control or timing during this operation. The device will automatically return to normal read mode after the erase operation completed. Data polling and/or Toggle Bits can be used to detect end of erase cycle. Program Operation The W49V002A is programmed on a byte-by-byte basis. Program operation can only change logical data -3 - Publication Release Date: April 2001 Revision A1 Preliminary W49V002A "1" to logical data "0." The erase operation, which changed entire data in main memory and/or boot block from "0" to "1", is needed before programming. The program operation is initiated by a 4-byte command cycle (see Command Codes for Byte Programming). The device will internally enter the program operation immediately after the byte-program command is entered. The internal program timer will automatically time-out (100 µS max. - TBP) once it is completed and then return to normal read mode. Data polling and/or Toggle Bits can be used to detect end of program cycle. Boot Block Operation and Hardware Protection at Initial- #TBL & #WP There are two alternatives to set the boot block. One is software command sequences method; the other is hardware method. 16K-byte in the top location of this device can be locked as boot block, which can be used to store boot codes. It is located in the last 16K bytes of the memory with the address range from 3C000(hex) to 3FFFF(hex). Please see Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set, the data for the designated block cannot be erased or programmed (programming lockout), other memory locations can be changed by the regular programming method. Besides the software method, there is a hardware method to protect the top boot block and other sectors. Before program/erase to this device, set the #TBL pin to low state and then the top boot block will not be programmed/erased. When enabling hardware top boot block, #TBL being low state, it will override the software method setting. That is, if #TBL is at low state, then top boot block cannot be programmed/erased no matter how the software boot block lock setting. Another pin, #WP, will protect the whole chip if this pin is set to low state before program/erase. The enable of this pin will override the #TBL setting. That is, the top boot block cannot be programmed/erased if this pin is set to low no matter how the #TBL or software boot block lock setting. Hardware Data Protection The integrity of the data stored in the W49V002A is also hardware protected in the following ways: (1) Noise/Glitch Protection: A #WE pulse of less than 15 nS in duration will not initiate a write cycle. (2) VDD Power Up/Down Detection: The programming operation is inhibited when VDD is less than 1.5V typical. (3) Write Inhibit Mode: Forcing #OE low or #WE high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down periods. (4) VDD power-on delay: When VDD has reached its sense level, the device will automatically time-out 5 mS before any write (erase/program) operation. Data Polling (DQ7)- Write Status Detection The W49V002A includes a data polling feature to indicate the end of a program or erase cycle. When the W49V002A is in the internal program or erase cycle, any attempts to read DQ7 of the last byte loaded will receive the complement of the true data. Once the program or erase cycle is completed, DQ7 will show the true data. Note that DQ7 will show logical "0" during the erase cycle, and when erase cycle has been completed it becomes logical "1" or true data. Toggle Bit (DQ6)- Write Status Detection In addition to data polling, the W49V002A provides another method for determining the end of a program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ6 will produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between 0's and 1's will stop. The device is then ready for the next operation. -4 - Preliminary W49V002A Memory Address Map There are 8M bytes space reserved for BIOS Addressing. The ROM will respond to 256K byte pages whenever the memory address rang is within the top 4M bytes and bottom 128K bytes. The 32bit address space is as below: Block Address Range 4M Byte BIOS ROM FFFF,FFFFh:FFC0,0000h 128K Byte BIOS ROM 000F,FFFFh:000E,0000h Registers FFBC,0100h General Purpose Inputs Register This register reads the GPI[4:0] pins on the W49V002A.This is a pass-through register which can read via memory address FFBC0100(hex). Since it is pass-through register, there is no default value. Bit 7-5 4 3 2 1 0 Function Reserved Read GPI4 pin status Read GPI3 pin status Read GPI2 pin status Read GPI1 pin status Read GPI0 pin status Product Identification The product ID operation outputs the manufacturer code and device code. Programming equipment automatically matches the device with its proper erase and programming algorithms. The manufacturer and device codes can be accessed by software operation. In the software access mode, a six-byte (or JEDEC 3-byte) command sequence can be used to access the product ID. A read from address 0000(hex) outputs the manufacturer code, DA(hex). A read from address 0001(hex) outputs the device code, B0(hex).” The product ID operation can be terminated by a three-byte command sequence or an alternate one-byte command sequence (see Command Definition table). -5 - Publication Release Date: April 2001 Revision A1 Preliminary W49V002A TABLE OF OPERATING MODES Operating Mode Selection - Programmer Mode (V HH = 12V ± 5%) MODE #OE VIL VIH X VIL X VIH Read Write Standby Write Inhibit Output Disable #WE VIH VIL X X VIH X #RESET VIH VIH VIL VIH VIH VIH PINS ADDRESS DQ. Dout Din High Z High Z/DOUT High Z/DOUT High Z AIN AIN X X X X Operating Mode Selection - LPC Mode Operation modes in LPC interface mode are determined by "cycle type" when it is selected. When it is not selected, its outputs (LAD[3:0]) will be disable. Please reference to the "Standard LPC Memory Cycle Definition". TABLE OF COMMAND DEFINITION COMMAND NO. OF 1ST CYCLE 2ND CYCLE 3RD CYCLE 4TH CYCLE 5TH CYCLE 6TH CYCLE DESCRIPTION Cycles Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Read 1 A IN Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10 Sector Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA Byte Program 4 5555 AA 2AAA 55 5555 A0 A IN Boot Block Lockout 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40 Product ID Entry 3 5555 AA 2AAA 55 5555 90 Product ID Exit (1) 3 5555 AA 2AAA 55 5555 F0 (1) 1 XXXX F0 Product ID Exit DOUT 30 DIN Note: 1. The cycle means the write command cycle not the LPC clock cycle. 2. The Column Address / Row Address are mapped to the Low / High order Internal Address. i.e. Column Address A[10:0] are mapped to the internal A[10:0], Row Address A[6:0] are mapped to the internal A[17:11] 3. Address Format: A14−A0 (Hex); Data Format: DQ7-DQ0 (Hex) 4. Either one of the two Product ID Exit commands can be used. 5. SA : Sector Address SA = 3C000h to 3FFFFh for Boot Block SA = 3A000h to 3BFFFh for Parameter Block1 SA = 38000h to 39FFFh for Parameter Block2 SA = 30000h to 37FFFh for Main Memory Block1 SA = 2XXXXh for Main Memory Block2 SA = 1XXXXh for Main Memory Block3 SA = 0XXXXh for Main Memory Block4 -6 - Preliminary W49V002A STANDARD LPC MEMORY CYCLE DEFINITION FIELD NO. OF CLOCKS DESCRIPTION Start 1 "0000b" appears on LPC bus to indicate the initial Cycle Type & Dir 1 "010Xb" indicates memory read cycle; while "011xb" indicates memory write cycle. "X" mean don't have to care. TAR 2 Turned Around Time Addr. 8 Address Phase for Memory Cycle. LPC supports the 32 bits address protocol. The addresses transfer most significant nibble first and least significant nibble last. (i.e. Address[31:28] on LAD[3:0] first , and Address[3:0] on LAD[3:0] last.) Sync. N Synchronous to add wait state. "0000b" means Ready, "0101b" means Short Wait, "0110b" means Long Wait, "1001b" for DMA only, "1010b" means error, and other values are reserved. Data 2 Data Phase for Memory Cycle. The data transfer least significant nibble first and most significant nibble last. (i.e. DQ[3:0] on LAD[3:0] first , then DQ[7:4] on LAD[3:0] last.) Note: 1. For detail related LPC specification, please refer to Intel LPC spec. 1.0 or later. -7 - Publication Release Date: April 2001 Revision A1 Preliminary W49V002A Command Codes for Byte Program BYTE SEQUENCE ADDRESS DATA 0 Write 5555H AAH 1 Write 2AAAH 55H 2 Write 5555H A0H 3 Write Programmed-Address Programmed-Data Byte Program Flow Chart Byte Program Command Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data A0 to address 5555 Load data Din to programmedaddress Pause TBP Exit Notes for software program code: Data Format: DQ7−DQ0 (Hex); XX = Don't Care Address Format: A14−A0 (Hex) -8 - Preliminary W49V002A Command Codes for Chip Erase BYTE SEQUENCE ADDRESS DATA 1 Write 5555H AAH 2 Write 2AAAH 55H 3 Write 5555H 80H 4 Write 5555H AAH 5 Write 2AAAH 55H 6 Write 5555H 10H Chip Erase Acquisition Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 10 to address 5555 Pause T EC Exit Notes for chip erase: Data Format: DQ7−DQ0 (Hex) Address Format: A14−A0 (Hex) -9 - Publication Release Date: April 2001 Revision A1 Preliminary W49V002A Command Codes for Sector Erase BYTE SEQUENCE ADDRESS 1 Write 5555H AAH 2 Write 2AAAH 55H 3 Write 5555H 80H 4 Write 5555H AAH 5 Write 2AAAH 55H 6 Write SA* 30H Sector Erase Acquisition Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 30 to address SA* Pause T EC Exit Notes for chip erase: Data Format: DQ7−DQ0 (Hex) Address Format: A14−A0 (Hex) SA : Sector Address SA = 3C000h to 3FFFFh for Boot Block SA = 3A000h to 3BFFFh for Parameter Block1 SA = 2XXXXh for Main Memory Block2 SA = 38000h to 39FFFh for Parameter Block2 SA = 1XXXXh for Main Memory Block3 SA = 30000h to 37FFFh for Main Memory Block1 SA = 0XXXXh for Main Memory Block4 - 10 - DATA Preliminary W49V002A Command Codes for Product Identification and Boot Block Lockout Detection BYTE SEQUENCE SOFTWARE PRODUCT IDENTIFICATION / BOOT BLOCK LOCKOUT DETECTION ENTRY SOFTWARE PRODUCT IDENTIFICATION / BOOT BLOCK LOCKOUT DETECTION EXIT (6) ADDRESS DATA ADDRESS DATA 1 Write 5555 AA 5555H AAH 2 Write 2AAA 55 2AAAH 55H 3 Write 5555 90 5555H F0H Pause 10µS Pause 10µS Software Product Identification and Boot Block Lockout Detection Acquisition Flow Product Identification Entry (1) Load data AA to address 5555 Product Product Identification Exit(6) Identification and Boot Block Lockout Detection Mode (3) Load data AA to address 5555 (2) Load data 55 to address 2AAA Read address = 00000 data = DA Load data 90 to address 5555 Read address = 00001 data = B0 Pause 10µ S Read address = 00002 DQ0 of data outputs = 1/0 (2) (4) Load data 55 to address 2AAA Load data F0 to address 5555 Pause 10µ S (5) Normal Mode Notes for software product identification/boot block lockout detection: (1) Data Format: DQ7−DQ0 (Hex); Address Format: A14−A0 (Hex) (2) A1−A17 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH. (3) The device does not remain in identification and boot block lockout detection mode if power down. (4) If the DQ0 of output data is "1," the boot block programming lockout feature is activated; if the DQ0 of output data "0," the lockout feature is inactivated and the block can be programmed. (5) The device returns to standard operation mode. (6) Optional 1-write cycle (write F0 hex at XXXX address) can be used to exit the product identification/boot block lockout detection. - 11 - Publication Release Date: April 2001 Revision A1 Preliminary W49V002A Command Codes for Boot Block Lockout Enable BYTE SEQUENCE BOOT BLOCK LOCKOUT FEATURE SET ADDRESS DATA 1 Write 5555H AAH 2 Write 2AAAH 55H 3 Write 5555H 80H 4 Write 5555H AAH 5 Write 2AAAH 55H 6 Write 5555H 40H Pause 1 Sec. Boot Block Lockout Enable Acquisition Flow Boot Block Lockout Feature Set Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 40 to address 5555 Pause T BP Exit Notes for boot block lockout enable: Data Format: DQ7−DQ0 (Hex) Address Format: A14−A0 (Hex) - 12 - Preliminary W49V002A DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER RATING UNIT -0.5 to +4.1 V 0 to +70 °C -65 to +150 °C D.C. Voltage on Any Pin to Ground Potential -0.5 to VDD +0.5 V Transient Voltage (<20 nS ) on Any Pin to Ground Potential -1.0 to VDD +0.5 V Power Supply Voltage to Vss Potential Operating Temperature Storage Temperature Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. Programmer interface Mode DC Operating Characteristics (V DD 3.3V ± 5%, V GND= 0V, TA = 0 to 70° C) PARAMETER SYM. TEST CONDITIONS LIMITS MIN. TYP. Power Supply Current ICC Input Leakage Current ILI Output Leakage Current In Read or Write mode, all DQs open UNIT MAX. - 20 30 mA VIN = GND to VDD - - 10 µA ILO VOUT = GND to VDD - - 10 µA Input Low Voltage VIL - -0.3 - 0.8 V Input High Voltage VIH - 2.0 - VDD +0.5 V Output Low Voltage VOL IOL = 2.1 mA - - 0.45 V Output High Voltage VOH IOH = -0.1mA 2.4 - - V Address inputs = 3.0V/0V, at f = 3 MHz - 13 - Publication Release Date: April 2001 Revision A1 Preliminary W49V002A LPC interface Mode DC Operating Characteristics (V DD = 3.3V ± 5%, V GND= 0V, TA = 0 to 70° C) PARAMETER SYM. TEST CONDITIONS LIMITS MIN. TYP. Power Supply Current ICC All Iout = 0A, CLK = 33MHz, UNIT MAX. - 40 60 mA - 20 100 uA - 3 10 mA in LPC mode operation. CMOS Standby Current Isb1 TTL Standby Current Isb2 #LFRAM = 0.9 VDD, CLK = 33MHz, all inputs = 0.9 VDD / 0.1 VDD #LFRAM = 0.1 VDD, CLK = 33MHz, all inputs = 0.9 VDD / 0.1 VDD Input Low Voltage VIL - -0.3 - 0.2 VDD V Input High Voltage VIH - 0.6 VDD - VDD +0.5 V Output Low Voltage VOL IOL = 1.5 mA - - 0.1 VDD V Output High Voltage VOH IOH = -0.5 mA 0.9 VDD - - V Power-up Timing PARAMETER SYMBOL TYPICAL UNIT Power-up to Read Operation TPU. READ 100 µS Power-up to Write Operation TPU. WRITE 5 mS CAPACITANCE (V DD = 3.3V, TA = 25° C, f = 1 MHz) PARAMETER SYMBOL CONDITIONS MAX. UNIT I/O Pin Capacitance CI/O VI/O = 0V 12 pf Input Capacitance CIN VIN = 0V 6 pf - 14 - Preliminary W49V002A PROGRAMMER INTERFACE MODE AC CHARACTERISTICS AC Test Conditions PARAMETER CONDITIONS Input Pulse Levels 0V to 0.9VDD Input Rise/Fall Time < 5 nS Input/Output Timing Level 1.5V/1.5V Output Load 1 TTL Gate and CL = 30 pF AC Test Load and Waveform +3.3V 1.8KΩ DOUT Input 30 pF (Including Jig and Scope) Output 0.9V DD 1.3K Ω 1.5V 1.5V 0V Test Point - 15 - Test Point Publication Release Date: April 2001 Revision A1 Preliminary W49V002A Programmer Interface Mode AC Characteristics, continued AC Characteristics Read Cycle Timing Parameters (V DD = 3.3V ± 5%, V GND = 0V, TA = 0 to 70° C) PARAMETER Read Cycle Time Row / Column Address Set Up Time Row / Column Address Hold Time Address Access Time Output Enable Access Time #OE Low to Active Output #OE High to High-Z Output Output Hold from Address Change SYM. TRC TAS TAH TAA TOE TOLZ TOHZ TOH W49V002A MIN. MAX. 300 50 50 200 100 0 50 0 - UNIT nS nS nS nS nS nS nS nS Write Cycle Timing Parameters PARAMETER Reset Time Address Setup Time Address Hold Time R/#C to Write Enable High Time #WE Pulse Width #WE High Width Data Setup Time Data Hold Time #OE Hold Time Byte programming Time Erase Cycle Time SYMBOL TRST TAS TAH TCWH TWP TWPH TDS TDH TOEH TBP TEC MIN. 1 50 50 50 100 100 50 50 0 - TYP. 50 0.15 MAX. 100 0.2 UNIT µS nS nS nS nS nS nS nS nS µS S Note: All AC timing signals observe the following guidelines for determining setup and hold times: (a) High level signal's reference level is input high and (b) low level signal's reference level is input low. Ref. to the AC testing condition. Data Polling and Toggle Bit Timing Parameters PARAMETER SYM. W49V002A MIN. MAX. UNIT #OE to Data Polling Output Delay TOEP - 40 nS #OE to Toggle Bit Output Delay TOET - 40 nS - 16 - Preliminary W49V002A TIMING WAVEFORMS FOR PROGRAMMER INTERFACE MODE Read Cycle Timing Diagram #RESET TRST TRC A[10:0] Column Address TAS Column Address Row Address TAH TAS Row Address TAH R/#C VIH #WE TAA #OE TOH T OE T OHZ TOLZ High-Z High-Z DQ[7:0] Data Valid Write Cycle Timing Diagram TRST #RESET A[10:0] Column Address TAS TAH Row Address TAS TAH R/ #C TCWH TOEH #OE TWP TWPH #WE TDS DQ[7:0] TDH Data Valid - 17 - Publication Release Date: April 2001 Revision A1 Preliminary W49V002A Timing Waveforms for Programmer Interface Mode, continued Program Cycle Timing Diagram Byte Program Cycle A[10:0] (Internal A[17:0]) 5555 DQ[7:0] 2AAA 5555 55 AA Programmed Address A0 Data-In R/#C #OE TWPH TBP TWP #WE Byte 0 Byte 1 Byte 2 Byte 3 Internal Write Start Note: The internal address A[17:0] are converted from external Column/Row address. Column/Row Address are mapped to the Low/High order internal address. i.e. Column Address A[10:0] are mapped to the internal A[10:0], Row Address A[6:0] are mapped to the internal A[17:11]. #DATA Polling Timing Diagram A[10:0] (Internal A[17:0]) An An An An R/ #C #WE #OE TOEP DQ7 X X X X TBP orTEC - 18 - Preliminary W49V002A Timing Waveforms for Programmer Interface Mode, continued Toggle Bit Timing Diagram A[10:0] R/ #C #WE #OE TOET DQ6 T BP or T EC Boot Block Lockout Enable Timing Diagram Six-byte code for 3.3V-only software chip erase A[10:0] (Internal A[17:0]) DQ[7:0] 5555 2AAA AA 55 5555 80 5555 AA 2AAA 55 5555 40 R/#C #OE TWP TWC #WE TWPH SB0 SB1 SB2 SB3 SB4 SB5 Note: The internal address A[17:0] are converted from external Column/Row address. Column/Row Address are mapped to the Low/High order internal address. i.e. Column Address A[10:0] are mapped to the internal A[10:0], Row Address A[6:0] are mapped to the internal A[17:11]. - 19 - Publication Release Date: April 2001 Revision A1 Preliminary W49V002A Timing Waveforms for Programmer Interface Mode, continued Chip Erase Timing Diagram Six-byte code for 3.3V-only software chip erase A[10:0] 2AAA 5555 (Internal A[17:0]) DQ[7:0] AA 55 5555 80 5555 2AAA AA 5555 55 10 R/#C #OE TWP #WE TEC TWPH SB0 SB1 SB2 SB3 SB4 Internal Erasure Starts SB5 Note: The internal address A[17:0] are converted from external Column/Row address. Column/Row Address are mapped to the Low/High order internal address. i.e. Column Address A[10:0] are mapped to the internal A[10:0], Row Address A[6:0] are mapped to the internal A[17:11]. Sector Erase Timing Diagram Six-byte code for 5V-only software Main Memory Erase A[10:0] (Internal A[17:0]) DQ[7:0] 5555 2AAA 5555 55 80 AA 5555 AA 2AAA 55 SA 30 R/ #C #OE TWP TEC #WE TWPH SB0 SB1 SB2 SB3 SB4 Note: The internal address A[17:0] are converted from external Column/Row address. Column/Row Address are mapped to the Low/High order internal address. i.e. Column Address A[10:0] are mapped to the internal A[10:0], Row Address A[6:0] are mapped to the internal A[17:11]. SA = Sector Address, Please ref. to the "Table of Command Definition" - 20 - SB5 Internal Erase starts Preliminary W49V002A LPC INTERFACE MODE AC CHARACTERISTICS AC Test Conditions PARAMETER CONDITIONS Input Pulse Levels 0.6 VDD to 0.2 VDD Input Rise/Fall Slew Rate 1 V/nS Input/Output Timing Level 0.4V DD / 0.4V DD Output Load 1 TTL Gate and CL = 10 pF AC Test Load and Waveform DOUT DOUT 10 pF 10 pF 25 Ω 25 Ω Input V DD Output 0.6V DD 0.4VDD 0.4V DD 0.2V DD Test Point Test when output from low to high Test Point Test when output from high to low Read/Write Cycle Timing Parameters (V DD = 3.3V ± 5%, V GND = 0V, TA = 0 to 70° C) PARAMETER SYM. W49V002A UNIT MIN. MAX. Clock Cycle Time TCYC 30 - nS Input Set Up Time TSU 7 - nS Input Hold Time THD 0 - nS Clock to Data Valid TKQ - 11 nS Reset Timing Parameters PARAMETER SYMBOL MIN. TYP. MAX. UNIT Vdd stable to Reset Active TPRST 1 - - mS Clock Stable to Reset Active TKRST 100 - - µS Reset Pulse Width TRSTP 100 - - nS Reset Active to Output Float TRSTF - - 50 nS Reset Inactive to Input Active TRST 1 - - µS Note: All AC timing signals observe the following guidelines for determining setup and hold times: (a) High level signal's reference level is input high and (b) low level signal's reference level is input low. Ref. to the AC testing condition. - 21 - Publication Release Date: April 2001 Revision A1 Preliminary W49V002A TIMING WAVEFORMS FOR LPC INTERFACE MODE Read Cycle Timing Diagram TCYC CLK #RESET TSU THD #LFRAM LAD[3:0] TSU THD Start Memory Read Cycle 0000b 010Xb 1 Clock 1 Clock TKQ Address A[31:28] A[27:24] A[23:20] A[19:16] TAR A[15:12] A[11:8] A[7:4] A[3:0] Load Address in 8 Clocks, the address should be within the top 4MByte, FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E0000. 1111b Sync 2 Clocks D[3:0] 1 Clock Next Start Data Tri-State 0000b D[7:4] TAR Data out 2 Clocks 0000b 1 Clock Write Cycle Timing Diagram TCYC CLK #RESET TSU THD #LFRAM LAD[3:0] Start Memory Write Cycle 0000b 011Xb 1 Clock 1 Clock Address A[31:28] A[27:24] A[23:20] A[19:16] TAR Data A[15:12] A[11:8] A[7:4] A[3:0] D[3:0] D[7:4] Load Data in 2 Clocks Load Address in 8 Clocks, the address should be within the top 4MByte, FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E0000. - 22 - 1111b Tri-State 2 Clocks Sync 0000b 1 Clock Next Start TAR 0000b 1 Clock Preliminary W49V002A Program Cycle Timing Diagram CLK #RESET #LFRAM Memory Write LAD[3:0] 0000b 011Xb Data Address 1st Start Cycle A[31:28] A[27:24] 1 Clock 1 Clock A[23:20] A[19:16] X101b 0101b 0101b 0101b 1010b TAR 1010b 1111b Load Data "AA" in 2 Clocks Load Address "5555" in 8 Clocks 2 Clocks Start next command Sync Tri-State 0000b TAR 1 Clock 1 Clock Write the 1st command to the device in LPC mode. CLK #RESET #LFRAM Memory Write LAD[3:0] 0000b 1 Clock 011Xb Data Address 2nd Start Cycle A[31:28] A[27:24] 1 Clock A[23:20] A[19:16] X010b 1010b 1010b 1010b 0101b TAR 0101b Load Data "55" in 2 Clocks Load Address "2AAA" in 8 Clocks 1111b Tri-State 2 Clocks Start next command Sync 0000b TAR 1 Clock 1 Clock Write the 2nd command to the device in LPC mode. CLK #RESET #LFRAM Memory Write LAD[3:0] 0000b 011Xb Data Address 3rd Start Cycle A[31:28] A[27:24] A[23:20] A[19:16] X101b 0101b 0101b 0101b Load Address "5555" in 8 Clocks 1 Clock 1 Clock 0000b TAR 1010b Load Data "A0" in 2 Clocks 1111b Tri-State 2 Clocks Start next command Sync 0000b TAR 1 Clock 1 Clock Write the 3rd command to the device in LPC mode. CLK #RESET Internal program start #LFRAM 4th Start LAD[3:0] 0000b Memory Write Cycle 011Xb 1 Clock 1 Clock Address A[31:28] A[27:24] A[23:20] A[19:16] Data A[15:12] A[11:8] A[7:4] A[3:0] D[3:0] TAR D[7:4] Load Din in 2 Clocks Load Ain in 8 Clocks 1111b Tri-State 2 Clocks Sync 0000b TAR Internal program start 1 Clock Write the 4th command(target location to be programmed) to the device in LPC mode. All the address loaded should be within the top 4MByte,FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E0000. - 23 - Publication Release Date: April 2001 Revision A1 Preliminary W49V002A Timing Waveforms for LPC Interface Mode, continued #DATA Polling Timing Diagram CLK #RESET #LFRAM Memory Write 1st Start Cycle LAD[3:0] 0000b 011Xb Data Address An[31:28] An[27:24] An[23:20] An[19:16] An[15:12] An[11:8] An[7:4] An[3:0] Dn[7:4] Load Data "Dn" in 2 Clocks Load Address "An" in 8 Clocks 1 Clock 1 Clock Dn[3:0] TAR 1111b Start next command Sync 0000b Tri-State 2 Clocks TAR 1 Clock 0000b 1 Clock Write the last command(program or erase) to the device in LPC mode. CLK #RESET XXXXb #LFRAM LAD[3:0] Start Memory Read Cycle 0000b 010Xb Address An[31:28] An[27:24] An[23:20] TAR An[19:16] An[15:12] An[11:8] An[7:4] An[3:0] Load Address in 8 Clocks 1 Clock 1 Clock 1111b Tri-State 2 Clocks Sync 0000b Next Start Data XXXXb Dn7,xxx TAR 1 Clock Data out 2 Clocks 0000b 1 Clock Read the DQ7 to see if the internal write complete or not. CLK #RESET #LFRAM LAD[3:0] Start Memory Read Cycle 0000b 010Xb 1 Clock 1 Clock Address An[31:28] An[27:24] An[23:20] An[19:16] TAR An[15:12] An[11:8] Load Address in 8 Clocks An[7:4] An[3:0] 1111b Sync Tri-State 0000b 2 Clocks Dn7,xxx 1 Clock Data out 2 Clocks When internal write complete, the DQ7 will equal to Dn7. All the address loaded should be within the top 4MByte,FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E0000. - 24 - Next Start Data XXXXb TAR 0000b 1 Clock Preliminary W49V002A Timing Waveforms for LPC Interface Mode, continued Toggle Bit Timing Diagram CLK #RESET #LFRAM Memory Write 1st Start Cycle LAD[3:0] 0000b 011Xb Data Address A[31:28] A[27:24] 1 Clock 1 Clock A[23:20] A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] D[3:0] D[7:4] TAR 1111b Load Data "Dn" in 2 Clocks Load Address "An" in 8 Clocks Start next command Sync Tri-State 2 Clocks 0000b TAR 1 Clock 1 Clock Write the last command(program or erase) to the device in LPC mode. CLK #RESET #LFRAM LAD[3:0] Start Memory Read Cycle 0000b 010Xb Address A[31:28] A[27:24] A[23:20] A[19:16] TAR XXXXb XXXXb XXXXb XXXXb Load Address in 8 Clocks 1 Clock 1 Clock 1111b Tri-State 2 Clocks Sync 0000b Next Start Data XXXXb X,D6,XXb TAR 1 Clock Data out 2 Clocks 0000b 1 Clock Read the DQ6 to see if the internal write complete or not. CLK #RESET #LFRAM LAD[3:0] Start Memory Read Cycle 0000b 010Xb 1 Clock 1 Clock Address A[31:28] A[27:24] A[23:20] A[19:16] TAR XXXXb XXXXb XXXXb Load Address in 8 Clocks XXXXb 1111b Tri-State 2 Clocks Data Sync 0000b XXXXb X,D6,XXb 1 Clock Data out 2 Clocks Next Start TAR 0000b 1 Clock When internal write complete, the DQ6 will stop toggle. All the address loaded should be within the top 4MByte,FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E0000. - 25 - Publication Release Date: April 2001 Revision A1 Preliminary W49V002A Timing Waveforms for LPC Interface Mode, continued Boot Block Lockout Enable Timing Diagram CLK #RESET #LFRAM Memory Write 1st Start Cycle 1 Clock 1 Clock Data Address 0000b 011Xb A[31:28] A[27:24] A[23:20] A[19:16] LAD[3:0] X101b 0101b 0101b 0101b 1010b TAR 1010b Load Data "AA" in 2 Clocks Write the 1st command to the device in LPC mode. Load Address "5555" in 8 Clocks 1111b Tri-State 2 Clocks Start next command Sync 0000b TAR 1 Clock 1 Clock CLK #RESET #LFRAM Memory Write 2nd Start Cycle LAD[3:0] Address 0000b 011Xb A[31:28] A[27:24] A[23:20] A[19:16] 1 Clock 1 Clock Data X010b 1010b 1010b 1010b 0101b TAR 0101b Load Data "55" in 2 Clocks Write the 2nd command to the device in LPC mode. Load Address "2AAA" in 8 Clocks 1111b Tri-State 2 Clocks Start next command Sync 0000b TAR 1 Clocks 1 Clock CLK #RESET #LFRAM Memory Write 3rd Start Cycle LAD[3:0] 0000b 011Xb 1 Clock 1 Clock Data Address A[31:28] A[27:24] A[23:20] A[19:16] X101b 0101b 0101b 0101b 0000b TAR 1000b Load Data "80" in 2 Clocks Write the 3rd command to the device in LPC mode. Load Address "5555" in 8 Clocks 1111b Start next command Sync Tri-State 2 Clocks 0000b TAR 1 Clock 1 Clock CLK #RESET #LFRAM LAD[3:0] Memory Write 4th Start Cycle 0000b 011Xb 1 Clock 1 Clock Address A[31:28] A[27:24] A[23:20] A[19:16] Data X101b 0101b 0101b 0101b 1010b TAR 1010b Load Data "AA" in 2 Clocks Write the 4th command to the device in LPC mode. Load Address "5555" in 8 Clocks 1111b Tri-State 2 Clocks Start next command Sync 0000b TAR 1 Clock 1 Clock CLK #RESET #LFRAM Memory Write 5th Start Cycle LAD[3:0] 0000b 011Xb 1 Clock 1 Clock Data Address A[31:28] A[27:24] A[23:20] A[19:16] X010b 1010b 1010b 1010b 0101b TAR 0101b Load Data "55" in 2 Clocks Write the 5th command to the device in LPC mode. Load Address "2AAA" in 8 Clocks 1111b Start next command Sync Tri-State 2 Clocks 0000b TAR 1 Clock 1 Clock CLK #RESET #LFRAM Memory Write 6th Start Cycle Internal program start Address Data LAD[3:0] 0000b 011Xb A[31:28] A[27:24] A[23:20] A[19:16] 1 Clock 1 Clock X101b 0101 b 0101b 0101b 0000b Load Address "5555" 8 Clocks Write the 6th command to the device in LPC 0100b Load Data "40" in 2 Clocks mode. TAR 1111b Tri-State 2 Clocks Sync 0000b 1 Clock All the address loaded should be within the top 4MByte,FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E0000. - 26 - TAR Internal program start Preliminary W49V002A Timing Waveforms for LPC Interface Mode, continued Chip Erase Timing Diagram CLK #RESET #LFRAM LAD[3:0] 1st Start Memory Write Cycle 0000b 011Xb Data Address A[31:28] A[27:24] 1 Clock 1 Clock A[23:20] A[19:16] X101b 0101b 0101b 0101b 1010b TAR 1010b 1111b Load Data "AA" in 2 Clocks Load Address "5555" in 8 Clocks Tri-State 2 Clocks Start next command Sync 0000b TAR 1 Clock 1 Clock Write the 1st command to the device in LPC mode. CLK #RESET #LFRAM LAD[3:0] 2nd Start Memory Write Cycle 0000b 011Xb Address A[31:28] A[27:24] 1 Clock 1 Clock A[23:20] A[19:16] Data X010b 1010b 1010b 1010b 0101b TAR 0101b Load Data "55" in 2 Clocks Load Address "2AAA" in 8 Clocks 1111b Tri-State 2 Clocks Start next command Sync 0000b TAR 1 Clock 1 Clock Write the 2nd command to the device in LPC mode. CLK #RESET #LFRAM LAD[3:0] 3rd Start Memory Write Cycle 0000b 011Xb Data Address A[31:28] A[27:24] 1 Clock 1 Clock A[23:20] A[19:16] X101b 0101b 0101b 0101b 0000b TAR 1000b Load Data "80" in 2 Clocks Load Address "5555" in 8 Clocks Start next command Sync 1111b Tri-State 2 Clocks 0000b TAR 1 Clock 1 Clock Write the 3rd command to the device in LPC mode. CLK #RESET #LFRAM LAD[3:0] 4th Start Memory Write Cycle 0000b 011Xb Address A[31:28] A[27:24] 1 Clock 1 Clock A[23:20] A[19:16] Data X101b 0101b 0101b 0101b 1010b TAR 1010b Load Data "AA" in 2 Clocks Load Address "5555" in 8 Clocks 1111b Tri-State 2 Clocks Start next command Sync 0000b TAR 1 Clock 1 Clock Write the 4th command to the device in LPC mode. CLK #RESET #LFRAM LAD[3:0] 5th Start Memory Write Cycle 0000b 011Xb Data Address A[31:28] A[27:24] 1 Clock 1 Clock A[23:20] A[19:16] X010b 1010b 1010b 1010b 0101b TAR 0101b Load Data "55" in 2 Clocks Load Address "2AAA" in 8 Clocks 1111b Start next command Sync Tri-State 2 Clocks 0000b TAR 1 Clock 1 Clock Write the 5th command to the device in LPC mode. CLK #RESET #LFRAM Internal erase start 6th Start Memory Write Cycle 0000b 011Xb Address Data TAR Sync LAD[3:0] 1 Clock 1 Clock A[31:28] A[27:24] A[23:20] A[19:16] X101b 0101b 0101b Load Address "5555" in 8 Clocks 0101b 0000b 0001b Load Data "10" in 2 Clocks 1111b Tri-State 2 Clocks 0000b TAR Internal erase start 1 Clock Write the 6th command to the device in LPC mode. All the address loaded should be within the top 4MByte,FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E0000. - 27 - Publication Release Date: April 2001 Revision A1 Preliminary W49V002A Timing Waveforms for LPC Interface Mode, continued Sector Erase Timing Diagram CLK #RESET #LFRAM Memory Write 1st Start Cycle LAD[3:0] 0000b 011Xb 1 Clock 1 Clock Data Address A[31:28] A[27:24] A[23:20] A[19:16] X101b 0101b 0101b 0101b 1010b TAR 1010b Load Data "AA" in 2 Clocks Load Address "5555" in 8 Clocks 1111b Tri-State 2 Clocks Start next command Sync 0000b TAR 1 Clock 1 Clock Write the 1st command to the device in LPC mode. CLK #RESET #LFRAM Memory Write 2nd Start Cycle LAD[3:0] 0000b 011Xb 1 Clock 1 Clock Address A[31:28] A[27:24] A[23:20] A[19:16] Data X010b 1010b 1010b 1010b 0101b TAR 0101b Load Data "55" in 2 Clocks Load Address "2AAA" in 8 Clocks 1111b Tri-State 2 Clocks Start next command Sync 0000b TAR 1 Clock 1 Clock Write the 2nd command to the device in LPC mode. CLK #RESET #LFRAM Memory Write 3rd Start Cycle LAD[3:0] 0000b 011Xb 1 Clocks 1 Clocks Data Address A[31:28] A[27:24] A[23:20] A[19:16] X101b 0101b 0101b 0101b 0000b TAR 1000b Load Data "80" in 2 Clocks Load Address "5555" in 8 Clocks 1111b Tri-State 2 Clocks Start next command Sync 0000b TAR 1 Clocks 1 Clocks Write the 3rd command to the device in LPC mode. CLK #RESET #LFRAM LAD[3:0] Memory Write 4th Start Cycle 0000b 011Xb 1 Clock 1 Clock Data Address A[31:28] A[27:24] A[23:20] A[19:16] X101b 0101b 0101b 0101b 1010b TAR 1010b Load Data "AA" in 2 Clocks Load Address "5555" in 8 Clocks 1111b Tri-State 2 Clocks Start next command Sync 0000b TAR 1 Clock 1 Clock Write the 4th command to the device in LPC mode. CLK #RESET #LFRAM Memory Write 5th Start Cycle LAD[3:0] 0000b 011Xb 1 Clock 1 Clock Data Address A[31:28] A[27:24] A[23:20] A[19:16] X010b 1010b 1010b 1010b Load Address "2AAA" in 8 Clocks 0101b TAR 0101b Load Data "55" in 2 Clocks 1111b Tri-State 2 Clocks Start next command Sync 0000b TAR 1 Clock 1 Clock Write the 5th command to the device in LPC mode. CLK #RESET #LFRAM Memory Write 6th Start Cycle LAD[3:0] Internal erase start Address 0000b 011Xb A[31:28] A[27:24] A[23:20] A[19:16] 1 Clock 1 Clock Data SA[15:12] XXXXb XXXXb Load Sector Address in 8 Clocks XXXXb 0000b 0011b Load Din in 2 Clocks TAR 1111b Tri-State 2 Clocks Sync 0000b 1 Clock Write the 6th command(target sector to be erased) to the device in LPC mode. All the address loaded should be within the top 4MByte,FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E0000. - 28 - TAR Internal erase start Preliminary W49V002A Timing Waveforms for LPC Interface Mode, continued GPI Register Readout Timing Diagram CLK #RESET #LFRAM LAD[3:0] Start Memory Read Cycle 0000b 010Xb Address A[31:28] A[27:24] 1 Clock 1 Clock A[23:20] A[19:16] TAR 0000b 0001b 0000b 0000b Load Address "FFBC0100(hex)" in 8 Clocks 1111b Tri-State 2 Clocks Sync 0000b Data D[3:0] Next Start D[7:4] 1 Clock Data out 2 Clocks TAR 0000b 1 Clock Note: Read the DQ[4:0] to capture the states(High or Low) of the GPI[4:0] input pins. The DQ[7:5] are reserved pins. Reset Timing Diagram VDD TPRST CLK TKRST TRSTP #RESET TRST TRST F LAD[3:0] #LFRAM - 29 - Publication Release Date: April 2001 Revision A1 Preliminary W49V002A ORDERING INFORMATION PART NO. ACCESS TIME POWER SUPPLY CURRENT MAX. STANDBY VDD CURRENT MAX. PACKAGE (nS) (mA) (µ A) W49V002AP 11 25 20 32L PLCC W49V002AQ 11 25 20 32L STSOP Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. - 30 - Preliminary W49V002A PACKAGE DIMENSIONS 32L PLCC Symbol HE A A1 A2 b1 b c D E e GD GE HD HE L y θ E 4 1 32 30 5 29 GD D HD 21 13 Dimension in Inches Min. Dimension in mm Nom. Max. Min. Nom. 0.140 Max. 3.56 0.020 0.50 0.105 0.110 0.115 2.67 2.80 2.93 0.026 0.028 0.032 0.66 0.71 0.81 0.016 0.46 0.018 0.022 0.41 0.008 0.010 0.014 0.20 0.25 0.35 0.547 0.550 0.553 13.89 13.97 14.05 0.447 0.450 0.453 11.35 11.43 11.51 0.044 0.050 0.056 1.12 1.27 1.42 0.490 0.510 0.530 12.45 12.95 13.46 0.390 0.410 0.430 9.91 10.41 10.92 0.585 0.590 0.595 14.86 14.99 15.11 0.485 0.490 0.495 12.32 12.45 12.57 0.075 0.090 0.095 1.91 2.29 2.41 0.004 0 0.56 0.10 0 10 10 Notes: 14 20 1. 2. 3. 4. c L A2 θ e b b1 Seating Plane Dimensions D & E do not include interlead flash. Dimension b1 does not include dambar protrusion/intrusion. Controlling dimension: Inches General appearance spec. should be based on final visual inspection sepc. A A1 y GE 32L STSOP(8 x 14mm) HD D c Dimension in Inches Dimension in mm Symbol Min. e E b θ L L1 A1 2 A A - 31 - Y A A1 A2 b c D E HD e L L1 Y θ Nom. Max. Min. Nom. Max. 0.047 0.002 1.20 0.006 0.05 0.035 0.040 0.041 0.95 0.007 0.009 0.010 0.004 ----- 0.008 1.05 0.17 0.22 0.27 0.10 ----- 0.21 0.488 12.40 0.315 8.00 0.551 14.00 0.020 0.020 0.024 0.50 0.028 0.50 0.031 0.000 0 0.15 1.00 3 0.60 0.70 0.80 0.004 0.00 5 0 0.10 3 5 Publication Release Date: April 2001 Revision A1 Preliminary W49V002A VERSION HISTORY VERSION DATE PAGE A1 Apr. 2001 - Headquarters DESCRIPTION Initial Issued Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No. 4, Creation Rd. III, No. 378 Kwun Tong Rd; Science-Based Industrial Park, Hsinchu, Taiwan Kowloon, Hong Kong TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5792766 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006 Taipei Office 11F, No. 115, Sec. 3, Min -Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change withou t notice. - 32 - Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798