2 Megabit LPC Flash SST49LF020 Advance Information SST49LF0202 Mb LPC Flash FEATURES: • Standard LPC Interface – Conforms to Intel LPC Interface Specification 1.0 • Organized as 256K x8 • Flexible Erase Capability – Uniform 4 KByte sectors – Uniform 16 KByte overlay blocks – 16 KBytes Top boot block protection – Chip-Erase for PP Mode • Single 3.0-3.6V Read and Write Operations • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Low Power Consumption – Active Read Current: 10 mA (typical) – Standby Current: 10 µA (typical) • Fast Sector-Erase/Byte-Program Operation – Sector-Erase Time: 18 ms (typical) – Block-Erase Time: 18 ms (typical) – Chip-Erase Time: 70 ms (typical) – Byte-Program Time: 14 µs (typical) – Chip Rewrite Time: 4 seconds (typical) – Single-pulse Program or Erase – Internal timing generation • Two Operational Modes – Low Pin Count (LPC) Interface mode for in-system operation – Parallel Programming (PP) Mode for fast production programming • LPC Interface Mode – 5-signal communication interface supporting byte Read and Write – 33 MHz clock frequency operation – WP# and TBL# pins provide hardware write protect for entire chip and/or top boot block – Standard SDP Command Set – Data# Polling and Toggle Bit for End-of-Write detection – 5 GPI pins for system design flexibility • Parallel Programming (PP) Mode – 11 pin multiplexed address and 8 pin data I/O interface – Supports fast In-System or PROM programming for manufacturing • CMOS I/O Compatibility • Packages Available – 32-lead PLCC – 32-lead TSOP (8mm x 14mm) PRODUCT DESCRIPTION The SST49LF020 flash memory device is designed to interface with the LPC bus for PC and Internet Applicance applications. It provides protection for the storage and update of code and data in addition to adding system design flexibility through five General Purpose Inputs (GPI). The SST49LF020 is in compliance with Intel Low Pin Count (LPC) Interface Specification 1.0. Two interface modes are supported: LPC Mode for In-System programming and Parallel Programming (PP) Mode for fast factory programming. The SST49LF020 flash memory device is manufactured with SST’s proprietary, high performance SuperFlash Technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST49LF020 device significantly improves performance and reliability, while lowering power consumption. The SST49LF020 device writes (Program or Erase) with a single 3.0-3.6V power supply. It uses less energy during Erase and Program than alternative flash memory technologies. The total energy consumed is a function of the applied voltage, current and time of application. Since for any give voltage range, the SuperFlash technology uses ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 526 1 less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash memory technologies. The SST49LF020 product provides a maximum Byte-Program time of 20µsec. The entire memory can be erased and programmed byte-by-byte typically in 4 seconds, when using status detection features such as Toggle Bit or Data# Polling to indicate the completion of Program operation. The SuperFlash technology provides fixed Erase and Program time, independent of the number of Erase/Program cycles that have performed. Therefore the system software or hardware does not have to be calibrated or correlated to the cumulative number of Erase/Program cycles as is necessary with alternative flash memory technologies, whose Erase and Program time increase with accumulated Erase/Program cycles. To protect against inadvertent write, the SST49LF020 device has on-chip hardware and software data (SDP) protection schemes. It is offered with a typical endurance of 100,000 cycles. Data retention is rated at greater than 100 years. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc. Intel is a registered trademark of Intel Corporation. These specifications are subject to change without notice. 2 Megabit LPC Flash SST49LF020 Advance Information To meet high density, surface mount requirements, the SST49LF020 device is offered in 32-lead TSOP and 32lead PLCC packages. See Figures 1 and 2 for pinouts and Table 2 for pin descriptions. At the beginning of an operation, the host may hold the LFRAME# active for several clock cycles, and even change the Start value. The LAD[3:0] bus is latched every rising edge of the clock. On the cycle in which LFRAME# goes inactive, the last latched value is taken as the Start value. CE# must be asserted one cycle before the start cycle to select the SST49LF020 for Read and Write operations. Mode Selection and Description The SST49LF020 flash memory device operates in two distinct interface modes: the LPC mode and the Parallel Programming (PP) mode. The Mode pin is used to set the interface mode selection. If the Mode pin is set to logic High, the device is in PP mode; while if the Mode pin is set Low, the device is in the LPC mode. The Mode selection pin must be configured prior to device operation. Once the SST49LF020 identifies the operation as valid (a start value of all zeros), it next expects a nibble that indicates whether this is a memory read or program cycle. Once this is received, the device is now ready for the Address and Data cycles. For Program operation the Data cycle will follow the Address cycle, and for Read operation TAR and SYNC cycles occur between the Address and Data cycles. At the end of every operation, the control of the bus must be returned to the host by a 2 clock TAR cycle. In LPC mode, the device is configured to its host using standard LPC interface protocol. Communication between Host and the SST49LF020 occurs via the 4-bit I/O communication signals, LAD [3:0] and LFRAME#. Device Memory Hardware Write Protection In PP mode, the device is programmed via an 11-bit address and an 8-bit data I/O parallel signals. The address inputs are multiplexed in row and column selected by control signal R/C# pin. The row addresses are mapped to the higher internal addresses, and the column addresses are mapped to the lower internal addresses. See Device Memory Map for address assignments. The Top Boot Lock (TBL#) and Write Protect (WP#) pins are provided for hardware write protection of device memory in the SST49LF020. The TBL# pin is used to write protect four boot sectors (16 KBytes) at the highest memory address range. WP# pin write protects the remaining sectors in the flash memory. An active low signal at the TBL# pin prevents Program and Erase operations of the top boot sectors. When TBL# pin is held high, the write protection of the top boot sectors is disabled. The WP# pin serves the same function for the remaining sectors of the device memory. The TBL# and WP# pins write protection functions operate independently of one another. LPC MODE Device Operation The LPC mode uses a 5-signal communication interface, a 4-bit address/data bus, LAD[3:0], and a control line, LFRAME#, to control operations of the SST49LF020. Cycle type operations such as Memory Read and Memory Write are defined in Intel Low Pin Count Interface Specification, Revision 1.0. JEDEC Standard SDP (Software Data Protection) Program and Erase commands sequences are incorporated into the standard LPC memory cycles. See Figure 8 through Figure 13 timing diagrams for command sequences. Both TBL# and WP# pins must be set to their required protection states prior to starting a Program or Erase operation. A logic level change occurring at the TBL# or WP# pin during a Program or Erase operation could cause unpredictable results. Reset LPC operations are transmitted via the 4-bit Address/Data bus (LAD[3:0]), and follow a particular sequence, depending on whether they are Read or Write operations. The standard LPC memory cycle is defined in Table 13. A VIL on INIT# or RST# pins initiates a device reset. INIT# and RST# pins have same function internally. It is required to drive INIT# or RST# pins low during a system reset to ensure proper CPU initialization. Both LPC Read and Write operations start in a similar way as shown in Figures 6 and 7 timing diagrams. The host (which is the term used here to describe the device driving the memory) asserts LFRAME# for one or more clocks and drives a start value on the LAD[3:0] bus. During a Read operation, driving INIT# or RST# pins low deselects the device and places the output drivers, LAD[3:0], in a high-impedance state. The reset signal must be held low for a minimal duration of time TRSTP. A reset latency will occur if a reset procedure is performed during a Program or Erase operation. See Table 12, Reset Timing Parameters, for more information. A device reset during an active Program or Erase will abort the operation and mem- ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 2 526 2 Megabit LPC Flash SST49LF020 Advance Information LFRAME# ory contents may become invalid due to data being altered had been disrupted from an incomplete Erase or Program operation. The LFRAME# signifies the start of a frame or the termination of a broken frame. Asserting LFRAME# for one or more clock cycle and driving a valid START value on LAD[3:0] will initiate device operation. The device enters standby mode when LFRAME# and CE# are high and no internal operations is in progress. GENERAL PURPOSE INPUTS REGISTER Pin# Bit Function 7:5 4 3 Reserved GPI[4] Reads status of general purpose input pin GPI[3] Reads status of general purpose input pin 32-PLCC 32-TSOP - - 30 7 Abort Mechanism If LFRAME# is driven low for one or more clock cycles during a LPC cycle, the cycle will be terminated and the device will wait for the ABORT command. The host must drive the LAD[3:0] with ‘1111b’ (ABORT command) to return the device to the ready mode. If abort occurs during the internal write cycle, the data may be incorrectly programmed or erased. It is required to wait for the Write operation to complete prior to initiation of the abort command. It is recommended to check the write status with Data# Polling (DQ7) or Toggle Bit (DQ6) pins. One other option is to wait for the fixed write time to expire. 15 3 2 GPI[2] Reads status of general purpose input pin 4 16 1 GPI[1] Reads status of general purpose input pin 5 17 0 GPI[0] Reads status of general purpose input pin 6 18 Registers There is one register available on the SST49LF020. The General Purpose Inputs Register. This register appears at its respective address location in the 4 GByte system memory map. General Purpose Inputs Register The GPI_REG (General Purpose Inputs Register) passes the state of GPI[4:0] pins at power-up on the SST49LF020. It is recommended that the GPI[4:0] pins be in the desired state before LFRAME# is brought low for the beginning of the next bus cycle, and remain in that state until the end of the cycle. There is no default value since this is a pass-through register. The GPI register appears at FFBC0100H in the 4 GBytes system memory map. See General Purpose Inputs Register table for the GPI_REG bits and function. CE# The CE# pin, enables and disables the SST49LF020, controlling read and write access of the device. To enable the SST49LF020, the CE# pin must be driven low one cycle prior to LFRAME# being driven low. For write (erase or program) cycles, the CE# pin must remain low during the internal programming. When CE# is high, the SST49LF020 is placed in low-power standby-mode. ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 3 526 2 Megabit LPC Flash SST49LF020 Advance Information PARALLEL PROGRAMMING MODE Device Operation Block-Erase Operation Commands are used to initiate the memory operation functions of the device. The data portion of the software command sequence is latched on the rising edge of WE#. During the software command sequence the row address is latched on the falling edge of R/C# and the column address is latched on the rising edge of R/C#. The Block-Erase Operation allows the system to erase the device in 16 KByte uniform block size. The Block-Erase operation is initiated by executing a six-byte-command load sequence for Software Data Protection with BlockErase command (50H) and block address. The internal Block-Erase operation begins after the sixth WE# pulse. The End-of-Erase can be determined using either Data# Polling or Toggle Bit methods. See Figure 21 for BlockErase timing waveforms. Any commands written during the Block-Erase operation will be ignored. Read The Read operation of the SST49LF020 device is controlled by OE#. OE# is the output control and is used to gate data from the output pins. Refer to the Read cycle timing diagram, Figure 15, for further details. Chip-Erase The SST49LF020 device provides a Chip-Erase operation only in PP Mode, which allows the user to erase the entire memory array to the “1” state. This is useful when the entire device must be quickly erased. Reset Driving the RST# low will initiate a hardware reset of the SST49LF020. The Chip-Erase operation is initiated by executing a sixbyte Software Data Protection command sequence with Chip-Erase command (10H) with address 5555H in the last byte sequence. The internal Erase operation begins with the rising edge of the sixth WE#. During the internal Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 22 for Chip-Erase timing diagram, and Figure 34 for the flowchart. Any commands written during the Chip-Erase operation will be ignored. Byte-Program Operation The SST49LF020 device is programmed on a byte-by-byte basis. The Byte-Program operation is initiated by executing a four-byte-command load sequence for Software Data Protection with address (BA) and data in the last byte sequence. During the Byte-Program operation, the row address (A10-A0) is latched on the falling edge of R/C# and the column address (A21-A11) is latched on the rising edge of R/C#. The data bus is latched on the rising edge of WE#. The Program operation, once initiated, will be completed, within 20 µs. See Figures 7 and 19 for Program operation timing diagram and Figure 31 for its flowchart. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands written during the internal Program operation will be ignored. Write Operation Status Detection The SST49LF020 device provides two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE# which initiates the internal Program or Erase operation. Sector-Erase Operation The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The sector architecture is based on uniform sector size of 4 KByte. The Sector-Erase operation is initiated by executing a six-bytecommand load sequence for Software Data Protection with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase can be determined using either Data# Polling or Toggle Bit methods. See Figure 20 for Sector-Erase timing waveforms. Any commands written during the Sector-Erase operation will be ignored. ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 4 526 2 Megabit LPC Flash SST49LF020 Advance Information Data# Polling (DQ7) six byte load sequence. The SST49LF020 device is shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to read mode, within TRC. When the SST49LF020 device is in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. The device is then ready for the next operation. During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# pulse. See Figures 9 and 17 for Data# Polling timing diagram and Figure 33 for a flowchart. Electrical Specifications The AC and DC specifications for the LPC interface signals (LAD[3:0], LCLCK. LFRAME# and RST#) as defined in Section 4.2.2 of the “PCI Local Bus specification, Rev. 2.1”. Refer to Table 5 for the DC voltage and current specifications. Refer to Tables 11, 12, 14, and 15 for the AC timing specifications for Clock, Read, Program, Erase and Reset operations. Toggle Bit (DQ6) Product Identification Mode During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating “0” and “1”, i.e., toggling between “0” and “1”. When the internal Program or Erase operation is completed, the toggling will stop. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# pulse for Program operation. For Sector-, Block- or ChipErase, the Toggle Bit is valid after the rising edge of sixth WE# pulse. See Figures 10 and 18 for Toggle Bit timing diagram and Figure 32 for a flowchart. The product identification mode identifies the device as SST49LF020 and the manufacturer as SST. TABLE 1: PRODUCT IDENTIFICATION Address Data Manufacturer’s ID 00000H BFH Device ID SST49LF020 00001H 61H T1.4 526 Data Protection Design Considerations The SST49LF020 device provides both hardware and software features to protect nonvolatile data from inadvertent writes. SST recommends a high frequency 0.1 µF ceramic capacitor to be placed as close as possible between VDD and VSS less than 1 cm away from the VDD pin of the device. Additionally, a low frequency 4.7 µF electrolytic capacitor from VDD to VSS should be placed within 5 cm of the VDD pin. If you use a socket for programming purposes add an additional 1-10 µF next to each socket. Hardware Data Protection Noise/Glitch Protection: A WE# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. The RST# pin must remain stable at VIH for the entire duration of an Erase operation. WP# must remain stable at VIH for the entire duration of the Erase and Program operations for non-boot block sectors. To write data to the top boot block sectors, the TBL# pin must also remain stable at VIH for the entire duration of the Erase and Program operations. Write Inhibit Mode: Forcing OE# low, WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. Software Data Protection (SDP) The SST49LF020 provides the JEDEC approved Software Data Protection scheme for all data alteration operation, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three byte sequence. The three byte-load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 5 526 2 Megabit LPC Flash SST49LF020 Advance Information FUNCTIONAL BLOCK DIAGRAM TBL# WP# INIT# X-Decoder LAD[3:0] LCLK LFRAME# LPC Interface SuperFlash Memory Address Buffers & Latches Y-Decoder GPI[4:0] R/C# A[10:0] DQ[7:0] OE# WE# Control Logic I/O Buffers and Data Latches Programmer Interface MODE RST# CE# 526 ILL B1.1 ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 6 526 2 Megabit LPC Flash SST49LF020 Advance Information Block 15 TBL# Block 14 Block 13 Block 12 Block 11 Block 10 Block 9 3FFFFH Boot Block 3C000H 3BFFFH 38000H 37FFFH 34000H 33FFFH 30000H 2FFFFH 2C000H 2BFFFH 28000H 27FFFH 24000H 23FFFH Block 8 WP# for Block 0~14 20000H 1FFFFH Block 7 1C000H 1BFFFH Block 6 18000H 17FFFH Block 5 14000H 13FFFH Block 4 10000H 0FFFFH Block 3 0C000H 0BFFFH Block 2 Block 1 Block 0 (16 KByte) DEVICE MEMORY MAP FOR 08000H 07FFFH 04000H 03FFFH 300000 02FFFH 02000H 01FFFH 01000H 00FFFH 00000H 4 KByte Sector 3 4 KByte Sector 2 4 KByte Sector 1 4 KByte Sector 0 526 ILL F52.3 SST49LF020 ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 7 526 2 Megabit LPC Flash SST49LF020 Advance Information NC NC NC NC (CE#) MODE (MODE) A10 (GPI4) R/C# (LCLK) VDD (VDD) NC RST# (RST#) A9 (GPI3) A8 (GPI2) A7 (GPI1) A6 (GPI0) A5 (WP#) A4 (TBL#) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Standard Pinout Top View Die Up OE# (INIT#) WE# (LFRAME#) VDD (VDD) DQ7 (RES) DQ6 (RES) DQ5 (RES) DQ4 (RES) DQ3 (LAD3) VSS (VSS) DQ2 (LAD2) DQ1 (LAD1) DQ0 (LAD0) A0 (RES) A1 (RES) A2 (RES) A3 (RES) 526 ILL F01.2 ( ) Designates LPC Mode NC 2 1 14MM) A10 (GPI4) RST# (RST#) 3 X R/C# (LCLK) A9 (GPI3) 4 VDD (VDD) A8 (GPI2) FIGURE 1: PIN ASSIGNMENTS FOR 32-LEAD TSOP (8MM 32 31 30 29 5 A6 (GPI0) 6 28 NC (CE#) A5 (WP#) 7 27 NC A4 (TBL#) 8 26 NC A3 (RES) 9 25 VDD (VDD) A2 (RES) 10 24 OE# (INIT#) A1 (RES) 11 23 A0 (RES) 12 22 WE# (LFRAME#) NC DQ0 (LAD0) 13 21 14 15 16 17 18 19 20 DQ5 (RES) DQ4 (RES) DQ3 (LAD3) VSS (VSS) DQ2 (LAD2) DQ1 (LAD1) 32-lead PLCC Top View DQ6 (RES) A7(GPI1) MODE (MODE) DQ7 (RES) 526 ILL F02.2 ( ) Designates LPC Mode FIGURE 2: PIN ASSIGNMENTS FOR 32-LEAD PLCC ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 8 526 2 Megabit LPC Flash SST49LF020 Advance Information TABLE 2: PIN DESCRIPTION Interface Symbol Pin Name A10-A0 Address DQ7-DQ0 Data OE# WE# Type1 PP LPC Functions I X Inputs for low-order addresses during Read and Write operations. Addresses are internally latched during a Write cycle. For the programming interface, these addresses are latched by R/C# and share the same pins as the high-order address inputs. I/O X To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# is high. Output Enable I X To gate the data output buffers. Write Enable I X To control the Write operations. MODE Interface Mode Select I X INIT# Initialize GPI[4:0] X This pin determines which interface is operational. When held high, programmer mode is enabled and when held low, LPC mode is enabled. This pin must be setup at power-up or before return from reset and not change during device operation. This pin is internally pulled down with a resistor between 20-100KΩ. I X This is the second reset pin for in-system use. This pin is internally combined with the RST# pin; If this pin or RST# pin is driven low, identical operation is exhibited. General Purpose Inputs I X These individual inputs can be used for additional board flexibility. The state of these pins can be read through LPC registers. These inputs should be at their desired state before the start of the PCI clock cycle during which the read is attempted, and should remain in place until the end of the Read cycle. Unused GPI pins must not be floated. TBL# Top Block Lock I X When low, prevents programming boot block sectors at top of memory. When TBL# is high it disables hardware write protection for the top block sectors. LAD[3:0] Address and Data I/O X To provide LPC control signals, as well as addresses and Command Inputs/Outputs data. LCLK Clock I X To provide a clock input to the control unit LFRAME# Frame I X To indicate start of a data transfer operation; also used to abort an LPC cycle in progress. RST# Reset I X To reset the operation of the device WP# Write Protect I X When low, prevents programming to all but the highest addressable top boot blocks. When WP# is high it disables hardware write protection for these blocks. R/C# Row/Column Select I RES Reserved X X Select for the Programming interface, this pin determines whether the address pins are pointing to the row addresses, or to the column addresses. X These pins must be left unconnected. VDD Power Supply I X X To provide power supply (3.0-3.6V) Vss Ground I X X Circuit ground (OV reference) CE# Chip Enable I X This signal must be asserted to select the device. When CE# is low, the device is enabled. When CE# is high, the device is placed in low power standby mode. NC No Connection I X Unconnected pins. X T2.3 526 1. I=Input, O=Output ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 9 526 2 Megabit LPC Flash SST49LF020 Advance Information TABLE 3: OPERATION MODES SELECTION (PP MODE) Mode RST# OE# WE# DQ Address Read VIH VIH VIH VIL VIL DOUT AIN VIH VIH VIL DIN AIN VIL X1 Sector or Block address, XXH for Chip-Erase Program Erase Reset VIL X X High Z X Write Inhibit VIH VIL X VIH VIL X High Z/DOUT High Z/DOUT X X Product Identification VIH VIL VIL Manufacturer’s ID (BFH) Device ID2 A18-A1=VIL, A0=VIL A18-A1=VIL, A0=VIH T3.2 526 1. X can be VIL or VIH, but no other value. 2. Device ID = 61H TABLE 4: SOFTWARE COMMAND SEQUENCE Command Sequence 1st1 Write Cycle 2nd1 Write Cycle 3rd1 Write Cycle 4th1 Write Cycle 5th1 Write Cycle 6th1 Write Cycle Addr2 Addr2 Addr2 Data Addr2 Data Addr2 Data Addr2 Data Data AAH 2AAAH 55H SAx4 30H 50H 10H Data Data Byte-Program 5555H AAH 2AAAH 55H 5555H A0H BA3 Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H Block-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H BAx5 Chip-Erase6 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 2AAAH 55H 5555H 90H 2AAAH 55H 5555H F0H Entry7 5555H AAH Software ID Exit8 XXH F0H Software ID Exit8 5555H AAH Software ID T4.5 526 1. LPC Mode use consecutive Write cycles to complete a command sequence; PP Mode use consecutive bus cycles to complete a command sequence. 2. Address format A14-A0 (Hex), Addresses A15-A21 can be VIL or VIH, but no other value, for the Command sequence in PP Mode. 3. BA = Program Byte address 4. SAx for Sector-Erase Address 5. BAx for Block-Erase Address 6. Chip-Erase is supported in PP Mode only 7. With A17-A1=0; SST Manufacturer’s ID=BFH, is read with A0=0. SST49LF020 Device ID = 61H, is read with A0=1. 8. Both Software ID Exit operations are equivalent ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 10 526 2 Megabit LPC Flash SST49LF020 Advance Information Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD + 0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD + 1.0V Package Power Dissipation Capability (Ta=25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. Outputs shorted for no more than one second. No more than one output shorted at a time. OPERATING RANGE Range Commercial AC CONDITIONS Ambient Temp VDD 0°C to +85°C 3.0-3.6V OF TEST1 Input Rise/Fall Time . . . . . . . . . . . . . . . 3 ns Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF See Figures 25 and 26 1. LPC interface signals use PCI load condition. TABLE 5: DC OPERATING CHARACTERISTICS (ALL INTERFACES) Limits Symbol IDD Parameter Min Max Units Test Conditions Address input=VIL/VIH, at f=1/TRC Min, VDD=VDD Max (PP Mode) Power Supply Current Read 12 mA OE#=VIH, WE#=VIH 24 mA OE#=VIH, WE#=VIL, VDD=VDD Max (PP Mode) ISB Standby VDD Current (LPC Interface) 100 µA LFRAME#=VIH, f=33 MHz, CE#=VIH VDD=VDD Max, All other inputs ≥ 0.9 VDD or ≤ 0.1 VDD IRY1 Ready Mode VDD Current (LPC Interface) 10 mA LFRAME#=VIL, f=33 MHz, VDD=VDD Max All other inputs ≥ 0.9 VDD or ≤ 0.1 VDD II Input Current for IC Pin 200 µA VIN=GND to VDD, VDD=VDD Max ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max Write ILO Output Leakage Current VIHI INIT# Input High Voltage 1 µA VOUT=GND to VDD, VDD=VDD Max VDD+0.5 V VDD=VDD Max VILI INIT# Input Low Voltage VIL Input Low Voltage -0.5 0.4 V VDD=VDD Max -0.5 0.3 VDD V VDD=VDD Min VIH Input High Voltage 0.5 VDD VOL Output Low Voltage VDD+0.5 V VDD=VDD Max 0.1 VDD V IOL=1500 µA, VDD=VDD Min VOH Output High Voltage V IOH=-500 µA, VDD=VDD Min 1.0 0.9 VDD T5.5 526 1. The device is in Ready Mode when no activity is on the LPC bus. ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 11 526 2 Megabit LPC Flash SST49LF020 Advance Information TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter Minimum Units TPU-READ1 Power-up to Read Operation 100 µs Power-up to Write Operation 100 µs TPU-WRITE 1 T6.1 526 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter TABLE 7: PIN CAPACITANCE (VDD=3.3V, Ta=25 °C, f=1 Mhz, other pins open) Parameter Description Test Condition Maximum CI/O1 I/O Pin Capacitance VI/O=0V 12 pF Input Capacitance VIN=0V CIN 1 LPIN2 6 pF Pin Inductance 20 nH T7.0 526 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. Refer to PCI Spec. TABLE 8: RELIABILITY CHARACTERISTICS Symbol Parameter Minimum Specification Units Test Method NEND1 Endurance 10,000 Cycles JEDEC Standard A117 TDR1 Data Retention 100 Years JEDEC Standard A103 ILTH1 Latch Up 100 + IDD mA JEDEC Standard 78 T8.1 526 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 9: CLOCK TIMING PARAMETERS (LPC MODE) Symbol Parameter Min Max Units TCYC LCLK Cycle Time 30 ns THIGH LCLK High Time 11 ns TLOW LCLK Low Time 11 - LCLK Slew Rate (peak-to-peak) 1 - RST# or INIT# Slew Rate 50 ns 4 V/ns mV/ns T9.0 526 Tcyc Thigh 0.6 VDD Tlow 0.5 VDD 0.4 VDD p-to-p (minimum) 0.4 VDD 0.3 VDD 0.2 VDD 526 ILL F27.0 FIGURE 3: LCLK WAVEFORM ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 12 526 2 Megabit LPC Flash SST49LF020 Advance Information VTH CLK VTEST VTL TVAL LAD [3:0] (Valid Output Data) LAD [3:0] (Float Output Data) TON TOFF 526 ILL F49.1 FIGURE 4: OUTPUT TIMING PARAMETERS VTH VTEST CLK VTL TSU TDH LAD [3:0] (Valid Input Data) Inputs Valid VMAX 526 ILL F50.1 FIGURE 5: INPUT TIMING PARAMETERS TABLE 10: INTERFACE MEASUREMENT CONDITION PARAMETERS Value Units VTH1 Symbol 0.6 VDD V 1 0.2 VDD V VTEST 0.4 VDD V 1 0.4 VDD VTL VMAX Input Signal Edge Rate V 1 V/ns T10.2 526 1. The input test environment is done with 0.1 VDD of overdrive over VIH and VIL. Timing parameters must be met with no more overdrive than this. VMAX specifies the maximum peak-to-peak waveform allowed for measuring input timing. Production testing may use different voltage values, but must correlate results back to these parameters. ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 13 526 2 Megabit LPC Flash SST49LF020 Advance Information AC CHARACTERISTICS (LPC MODE) TABLE 11: READ/WRITE CYCLE TIMING PARAMETERS (LPC MODE), VDD=3.0-3.6V Symbol Parameter Min Max Units TCYC Clock Cycle Time 30 ns TSU Data Set Up Time to Clock Rising 7 ns TDH Clock Rising to Data Hold Time 0 TVAL Clock Rising to Data Valid 2 TBP Byte Programming Time 20 µs TSE Sector-Erase Time 25 ms TBE Block-Erase Time 25 ms ns 11 ns T11.1 526 TABLE 12: RESET TIMING PARAMETERS, VDD = 3.0-3.6V Symbol Parameter Min Max Units TPRST VDD stable to Reset Active 1 ms TKRST Clock Stable to Reset Active 100 µs TRSTP Reset Pulse Width 100 TRSTF Reset Active to Output Float 50 ns TRST Reset Inactive to Input Active 1 µs ns T12.1 526 TABLE 13: STANDARD LPC MEMORY CYCLE DEFINITION (LPC MODE) Field No. of Clocks Description START 1 “0000b” appears on LPC bus to indicate the start of cycle CYCTYPE + DIR 1 Cycle Type: Indicates the type of cycle. Bits 3:2 must be “01b” for memory cycle. Bit 2 indicates the type of transfer “0” for Read, “1” for write. DIR: Indicates the direction of the transfer. “0b” for Read, “1b” for Write. Bit 0 is reserved. “010Xb” indicates memory Read cycle; while “011xb” indicates memory Write cycle. TAR 2 The last component driving LAD[3:0] will drive it to “1111b” during the first clock, and tri-state it during the second clock. ADDR 8 Address Phase for Memory Cycle. LPC supports the 32-bit address protocol. The addresses transfer most significant nibble first and least significant nibble last. (i.e., Address[31:28] on LAD[3:0] first, and Address[3:0] on LAD[3:0] last.) Sync N Synchronize to host or peripheral by adding wait states. “0000b” means Ready, “0101b” means Short Wait, “0110b” means Long Wait, “1001b” for DMA only, “1010b” means error, other values are reserved. Data 2 Data Phase for Memory Cycle. The data transfer least significant nibble first and most significant nibble last. (i.e., DQ[3:0] on LAD[3:0] first, then DQ[7:4] on LAD[3:0] last.) T13.0 526 ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 14 526 2 Megabit LPC Flash SST49LF020 Advance Information TCYC LCLK CE# RST# LFRAME# LAD[3:0] TVAL Start Memory Read Cycle 0000b 010Xb Address xxxxb xxxxb 1 Clock 1 Clock xxxxb TAR A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] Load Address in 8 Clocks 1111b Sync 0000b Tri-State TSU TDH Data D[3:0] Next Start TAR D[7:4] 1 Clock Data Out 2 Clocks 2 Clocks 0000b 1 Clock 526 ILL F10.2 FIGURE 6: READ CYCLE TIMING DIAGRAM (LPC MODE) TCYC LCLK CE# RST# TSU TDH LFRAME# LAD[3:0] Start Memory Write Cycle 0000b 011Xb 1 Clock 1 Clock Address xxxxb xxxxb xxxxb A[19:16] A[15:12] Data A[11:8] A[7:4] A[3:0] D[3:0] D[7:4] Load Data in 2 Clocks Load Address in 8 Clocks TAR Sync 1111b Tri-State 0000b 2 Clocks 1 Clock Next Start TAR 0000b 1 Clock 526 ILL F46.2 FIGURE 7: WRITE CYCLE TIMING DIAGRAM (LPC MODE) ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 15 526 2 Megabit LPC Flash SST49LF020 Advance Information LCLK RST# CE# LFRAME# LAD[3:0] 1st Start Memory Write Cycle 0000b 011Xb Data Address xxxxb xxxxb 1 Clock 1 Clock xxxxb xxxxb X101b 0101b 0101b 0101b 1010b 1010b TAR 1111b Load Data "AA" in 2 Clocks Load Address "5555" in 8 Clocks Start next Command Sync Tri-State 0000b 2 Clocks 1 Clock TAR Sync TAR 1 Clock Write the 1st command to the device in LPC mode. LCLK RST# = VIH CE# = VIL LFRAME# LAD[3:0] Memory Write 2nd Start Cycle 0000b 011Xb Data Address xxxxb xxxxb 1 Clock 1 Clock xxxxb xxxxb X010b 1010b 1010b 1010b Load Address "2AAA" in 8 Clocks 0101b 0101b 1111b Load Data "55" in 2 Clocks Tri-State 2 Clocks 0000b Start next Command TAR 1 Clock 1 Clock Write the 2nd command to the device in LPC mode. LCLK RST# = VIH CE# = VIL LFRAME# LAD[3:0] 3rd Start 0000b Address 011Xb xxxxb xxxxb 1 Clock 1 Clock xxxxb xxxxb Data X010b 1010b 1010b Load Address "5555" in 8 Clocks 1010b 0101b TAR 0101b 1111b Load Data "A0" in 2 Clocks 2 Clocks Start next Command Sync Tri-State 0000b TAR 1 Clock 1 Clock Write the 3rd command to the device in LPC mode. LCLK RST# = VIH CE# = VIL LFRAME# LAD[3:0] Internal program start Memory Write 4th Start Cycle 0000b 011Xb 1 Clock 1 Clock Data Address xxxxb xxxxb xxxxb A[19:16] A[15:12] A[11:8] A[7:4] Load Ain in 8 Clocks A[3:0] D[3:0] TAR D[7:4] Load Data in 2 Clocks 1111b Sync Tri-State 0000b 2 Clocks 1 Clock TAR Internal program start Write the 4th command (target locations to be programmed) to the device in LPC mode. 526 ILL F18.3 FIGURE 8: PROGRAM CYCLE TIMING DIAGRAM (LPC MODE) ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 16 526 2 Megabit LPC Flash SST49LF020 Advance Information LCLK RST# CE# LFRAME# 1st Start LAD[3:0] Memory Write Cycle 0000b 011Xb Data Address xxxxb xxxxb 1 Clock 1 Clock xxxxb A[19:16] A[15:12] A[11:8] A[7:4] A3:0] D3:0] D[7:4] TAR Sync 1111b Tri-State 0000b Load Data "Dn" in 2 Clocks 2 Clocks Load Address "An" in 8 Clocks TAR Start next Command 0000b 1 Clock 1 Clock Write the last command (Program or Erase) to the device in LPC mode. LCLK RST# = VIH CE# = VIL LFRAME# LAD[3:0] Start 0000b Next start Memory Read Cycle 010Xb Address xxxxb xxxxb xxxxb A[19:16] TAR A[15:12] A[11:8] A[7:4] A3:0] 1111b Tri-State 2 Clocks Load Address in 8 Clocks Read the DQ7 to see if internal write complete or not. 1 Clock 1 Clock Sync 0000b 1 Clock Data XXXXb D7#,xxx TAR 0000b 1 Clock Data out 2 Clocks LCLK RST# = VIH CE# = VIL LFRAME# LAD[3:0] Start 0000b Memory Read Cycle 010Xb 1 Clock 1 Clock Next start Address xxxxb xxxxb xxxxb A[19:16] TAR A[15:12] A[11:8] A[7:4] A3:0] Load Address in 8 Clocks When internal write complete, the DQ7 will equal to D7. 1111b Tri-State 2 Clocks Sync 0000b Data XXXXb D7,xxx 1 Clock Data out 2 Clocks TAR 0000b 1 Clock 526 ILL F19.2 FIGURE 9: DATA# POLLING TIMING DIAGRAM (LPC MODE) ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 17 526 2 Megabit LPC Flash SST49LF020 Advance Information LCLK RST# CE# LFRAME# 1st Start LAD[3:0] 0000b Memory Write Cycle 011Xb Data Address xxxxb xxxxb 1 Clock 1 Clock xxxxb A[19:16] A[15:12] A[11:8] A[7:4] A3:0] D3:0] 1111b Tri-State D[7:4] Load Data "Dn" in 2 Clocks Load Address "An" in 8 Clocks Start next Command Sync TAR 2 Clocks 0000b TAR 0000b 1 Clock 1 Clock Write the last command (Program or Erase) to the device in LPC mode. LCLK RST# = VIH CE# = VIL LFRAME# LAD[3:0] Start 0000b Next start Memory Read Cycle 010Xb Address xxxxb xxxxb 1 Clock 1 Clock xxxxb A[19:16] TAR A[15:12] A[11:8] A[7:4] A3:0] Load Address in 8 Clocks 1111b Tri-State Sync 0000b 2 Clocks 1 Clock TAR Sync Data XXXXb X,D6#,XXb TAR 0000b 1 Clock Read the DQ6 to see if internal write complete or not. LCLK RST# = VIH CE# = VIL LFRAME# LAD[3:0] Start 0000b Memory Read Cycle 010Xb 1 Clock 1 Clock Next start Address xxxxb xxxxb xxxxb A[19:16] A[15:12] A[11:8] A[7:4] A3:0] Load Address in 8 Clocks When internal write complete, the DQ6 will stop toggle. 1111b Tri-State 2 Clocks 0000b Data XXXXb X,D6,XXb 1 Clock Data out 2 Clocks TAR 0000b 1 Clock 526 ILL F20.2 FIGURE 10: TOGGLE BIT TIMING DIAGRAM (LPC MODE) ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 18 526 2 Megabit LPC Flash SST49LF020 Advance Information LCLK RST# CE# LFRAME# 1st Start LAD[3:0] 0000b Memory Write Cycle 011Xb Data Address xxxxb xxxxb 1 Clock 1 Clock xxxxb xxxxb X101b 0101b 0101b 0101b 1010b Load Data "AA" in 2 Clocks Load Address "5555" in 8 Clocks Tri-State 0000b 2 Clocks Start next Command Sync TAR 1111b 1010b TAR 1 Clock 1 Clock Write the 1st command to the device in LPC mode. LCLK RST# = VIH CE# = VIL LFRAME# LAD[3:0] 2nd Start 0000b Memory Write Cycle 011Xb Data Address xxxxb 1 Clock 1 Clock xxxxb xxxxb xxxxb X010b 1010b 1010b 1010b 0101b TAR 0101b 1111b Load Data "55" in 2 Clocks Load Address "2AAA" in 8 Clocks 2 Clocks Start next Command Sync Tri-State 0000b TAR 1 Clock 1 Clock Write the 2nd command to the device in LPC mode. LCLK RST# = VIH CE# = VIL LFRAME# 3rd Start LAD[3:0] Memory Write Cycle 0000b 011Xb Data Address xxxxb xxxxb xxxxb 1 Clock 1 Clock xxxxb X101b 0101b 0101b 0101b 0000b TAR 1111b 1000b Load Data "80" in 2 Clocks Load Address "5555" in 8 Clocks Tri-State 2 Clocks Start next Command Sync 0000b TAR 1 Clock 1 Clock Write the 3rd command to the device in LPC mode. LCLK RST# = VIH CE# = VIL LFRAME# 4th Start LAD[3:0] Memory Write Cycle 0000b 011Xb Data Address xxxxb xxxxb xxxxb 1 Clock 1 Clock xxxxb X101b 0101b 0101b 0101b 1010b TAR 1111b 1010b Load Data "AA" in 2 Clocks Load Address "5555" in 8 Clocks Tri-State 2 Clocks Start next Command Sync 0000b TAR 1 Clock 1 Clock Write the 4th command to the device in LPC mode. LCLK RST# = VIH CE# = VIL LFRAME# 5th LAD[3:0] Memory Write Cycle 0000b 011Xb Data Address xxxxb 1 Clock 1 Clock xxxxb xxxxb xxxxb X010b 1010b 1010b 1010b 0101b 0101b Load Data "55" in 2 Clocks Load Address "2AAA" in 8 Clocks TAR Sync 1111b Tri-State 0000b 2 Clocks Start next Command TAR 1 Clock 1 Clock Write the 5th command to the device in LPC mode. LCLK RST# = VIH CE# = VIL Internal erase start LFRAME# 6th Start LAD[3:0] Memory Write Cycle 0000b 011Xb 1 Clock 1 Clock Data Address xxxxb xxxxb xxxxb A[19:16] SAX XXXXb XXXXb Load Sector Address in 8 Clocks XXXXb 0000b 0011b Load Data “30” in 2 Clocks Write the 6th command (target sector to be erased) to the device in LPC mode. SAX = Sector Address TAR 1111b Tri-State 2 Clocks Internal erase start Sync 0000b TAR 1 Clock 526 ILL F23.3 FIGURE 11: SECTOR-ERASE TIMING DIAGRAM (LPC MODE) ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 19 526 2 Megabit LPC Flash SST49LF020 Advance Information LCLK RST# CE# LFRAME# 1st Start LAD[3:0] 0000b Memory Write Cycle 011Xb Data Address xxxxb 1 Clock 1 Clock xxxxb xxxxb xxxxb X101b 0101b 0101b 0101b 1010b 1010b Load Data "AA" in 2 Clocks Load Address "5555" in 8 Clocks 1111b Start next Command Sync TAR Tri-State 0000b 2 Clocks 1 Clock TAR Sync TAR 1 Clock Write the 1st command to the device in LPC mode. LCLK RST# = VIH CE# = VIL LFRAME# 2nd Start LAD[3:0] 0000b Memory Write Cycle 011Xb Data Address xxxxb 1 Clock 1 Clock xxxxb xxxxb xxxxb X010b 1010b 1010b 1010b 0101b 0101b Load Data "55" in 2 Clocks Load Address "2AAA" in 8 Clocks 1111b Tri-State 2 Clocks 0000b Start next Command TAR 1 Clock 1 Clock Write the 2nd command to the device in LPC mode. LCLK RST# = VIH CE# = VIL LFRAME# 3rd Start LAD[3:0] 0000b Memory Write Cycle 011Xb Data Address xxxxb 1 Clock 1 Clock xxxxb xxxxb xxxxb X101b 0101b 0101b 0101b 0000b TAR 1000b Load Data "80" in 2 Clocks Load Address "5555" in 8 Clocks 1111b Tri-State 2 Clocks Start next Command Sync 0000b TAR 1 Clock 1 Clock Write the 3rd command to the device in LPC mode. LCLK RST# = VIH CE# = VIL LFRAME# 4th Start LAD[3:0] Memory Write Cycle 0000b 011Xb Data Address xxxxb 1 Clock 1 Clock xxxxb xxxxb xxxxb X101b 0101b 0101b 0101b 1010b 1010b Load Data "AA" in 2 Clocks Load Address "5555" in 8 Clocks TAR 1111b Tri-State 2 Clocks Start next Command Sync 0000b TAR 1 Clock 1 Clock Write the 4th command to the device in LPC mode. LCLK RST# = VIH CE# = VIL LFRAME# 5th LAD[3:0] 0000b Memory Write Cycle 011Xb Data Address xxxxb 1 Clock 1 Clock xxxxb xxxxb xxxxb X010b 1010b 1010b 1010b 0101b 0101b Load Data "55" in 2 Clocks Load Address "2AAA" in 8 Clocks TAR 1111b Tri-State 2 Clocks Start next Command Sync 0000b TAR 1 Clock 1 Clock Write the 5th command to the device in LPC mode. LCLK RST# = VIH CE# = VIL Internal erase start LFRAME# 6th Start LAD[3:0] 0000b Memory Write Cycle 011Xb 1 Clock 1 Clock Data Address xxxxb BAX XXXXb Load Block Address in 8 Clocks xxxxb xxxxb A[19:16] XXXXb XXXXb 0000b 0101b Load Data “50” in 2 Clocks Write the 6th command (target sector to be erased) to the device in LPC mode. BAX = Block Address TAR 1111b 2 Clocks Internal erase start Sync Tri-State 0000b TAR 1 Clock 526 ILL F47.3 FIGURE 12: BLOCK-ERASE TIMING DIAGRAM (LPC MODE) ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 20 526 2 Megabit LPC Flash SST49LF020 Advance Information LCLK RST# CE# LFRAME# Start LAD[3:0] 0000b Memory Read Cycle 010Xb 1 Clock 1 Clock Address 1111b 1111b 1011b 1100b TAR 0000b 0001b 0000b 0000b 1111b Tri-State 2 Clocks Load Address "FFBC0100(hex)" in 8 Clocks Sync 0000b 1 Clock Start next Data D[3:0] D[7:4] Data out 2 Clocks Note: Read the DQ[4:0] to capture the states (High or Low) of the GPI[4:0] input pins. The DQ[7:5] are reserved pins. TAR 0000b 1 Clock 526 ILL F24.1 FIGURE 13: GPI REGISTER READOUT TIMING DIAGRAM (LPC MODE) VDD TPRST LCLK TKRST TRSTP RST#/INIT# TRSTF TRST LAD[3:0] LFRAME# 526 ILL F25.0 FIGURE 14: RESET TIMING DIAGRAM (LPC MODE) ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 21 526 2 Megabit LPC Flash SST49LF020 Advance Information AC CHARACTERISTICS (PP MODE) TABLE 14: READ CYCLE TIMING PARAMETERS VDD=3.0-3.6V (PP MODE) Symbol Parameter Min Max TRC Read Cycle Time 270 ns TRST RST# High to Row Address Setup 1 µs TAS R/C# Address Set-up Time 45 ns TAH R/C# Address Hold Time 45 ns TAA Address Access Time 120 ns TOE Output Enable Access Time 60 ns TOLZ OE# Low to Active Output TOHZ OE# High to High-Z Output TOH Output Hold from Address Change 0 Units ns 35 ns 0 ns T14.1 526 TABLE 15: PROGRAM/ERASE CYCLE TIMING PARAMETERS VDD=3.0-3.6V (PP MODE) Symbol Parameter Min Max Units TRST RST# High to Row Address Setup 1 µs TAS R/C# Address Setup Time 50 ns TAH R/C# Address Hold Time 50 ns TCWH R/C# to Write Enable High Time 50 ns TOES OE# High Setup Time 20 ns TOEH OE# High Hold Time 20 ns TOEP OE# to Data# Polling Delay 40 ns TOET OE# to Toggle Bit Delay 40 ns TWP WE# Pulse Width 100 ns TWPH WE# Pulse Width High 100 ns TDS Data Setup Time 50 ns TDH Data Hold Time 5 ns TIDA Software ID Access and Exit Time 150 ns TBP Byte Programming Time 20 µs TSE Sector-Erase Time 25 ms TBE Block-Erase Time 25 ms TSCE Chip-Erase Time 100 ms T15.1 526 ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 22 526 2 Megabit LPC Flash SST49LF020 Advance Information RST# TRST TRC Row Address Addresses TAS Column Address TAH Row Address Column Address TAH TAS R/C# WE# VIH TAA TOH OE# TOE TOLZ DQ7-0 TOHZ High-Z Data Valid High-Z 526 ILL F28.0 FIGURE 15: READ CYCLE TIMING DIAGRAM (PP MODE) TRST RST# Addresses Row Address TAS Column Address TAH TAS TAH R/C# TCWH OE# TOEH TOES TWP TWPH WE# TDS DQ7-0 TDH Data Valid 526 ILL F29.0 FIGURE 16: WRITE CYCLE TIMING DIAGRAM (PP MODE) ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 23 526 2 Megabit LPC Flash SST49LF020 Advance Information Row Addresses Column R/C# WE# OE# TOEP DQ7 D D# D# D 526 ILL F54.2 FIGURE 17: DATA# POLLING TIMING DIAGRAM (PP MODE) Addresses Row Column R/C# WE# OE# TOET DQ6 D D 526 ILL F55.0 FIGURE 18: TOGGLE BIT TIMING DIAGRAM (PP MODE) ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 24 526 2 Megabit LPC Flash SST49LF020 Advance Information Four-Byte Code for Byte-Program Addresses 5555 2AAA 5555 BA R/C# OE# TBP TWP WE# TWPH SB0 SB1 AA DQ7-0 SB2 55 SB3 A0 Internal Program Starts Data BA = Byte-Program Address 526 ILL F51.0 FIGURE 19: BYTE-PROGRAM TIMING DIAGRAM (PP MODE) Six-Byte code for Sector-Erase Addresses 5555 2AAA 5555 5555 2AAA SAx R/C# OE# TWP WE# TSE TWPH SB0 AA DQ7-0 SB1 55 SB2 SB3 80 AA SB4 55 SB5 Internal Erase Starts 30 526 ILL F32.0 SAx = Sector Address FIGURE 20: SECTOR-ERASE TIMING DIAGRAM (PP MODE) ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 25 526 2 Megabit LPC Flash SST49LF020 Advance Information Six-Byte code for Block-Erase Addresses 5555 2AAA 5555 5555 2AAA BAx R/C# OE# TWP WE# TBE TWPH SB0 SB1 AA DQ7-0 SB2 55 SB3 80 SB4 AA SB5 55 Internal Erase Starts 50 526 ILL F48.0 BAx = Block Address FIGURE 21: BLOCK-ERASE TIMING DIAGRAM (PP MODE) Six-Byte code for Chip-Erase Addresses 5555 2AAA 5555 5555 2AAA 5555 R/C# OE# TWP WE# DQ7-0 TSCE TWPH SB0 SB1 SB2 SB3 SB4 SB5 AA 55 80 AA 55 10 Internal Erase Starts 526 ILL F33.0 FIGURE 22: CHIP-ERASE TIMING DIAGRAM (PP MODE) ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 26 526 2 Megabit LPC Flash SST49LF020 Advance Information Three-byte sequence for Software ID Entry Addresses 5555 2AAA 5555 0000 0001 R/C# OE# TIDA TWP WE# TAA TWPH DQ7-0 AA 55 90 SW0 SW1 SW2 FIGURE 23: SOFTWARE ID ENTRY AND BFH 61H 526 ILL F34.3 READ (PP MODE) Three-Byte Sequence for Software ID Exit and Reset Addresses 2AAA 5555 5555 TIDA R/C# OE# TWP WE# T WHP SW0 DQ7-0 AA SW1 55 SW2 F0 526 ILL F35.1 FIGURE 24: SOFTWARE ID EXIT AND RESET (PP MODE) ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 27 526 2 Megabit LPC Flash SST49LF020 Advance Information VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 526 ILL F06.1 AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points for inputs and outputs are VIT (0.4 VDD) and VOT (0.4 VDD). Input rise and fall times (10% ↔ 90%) are <3 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE 25: AC INPUT/OUTPUT REFERENCE WAVEFORMS (PP MODE) TO TESTER TO DUT CL 526 ILL F07.0 FIGURE 26: A TEST LOAD EXAMPLE ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 28 526 2 Megabit LPC Flash SST49LF020 Advance Information Address: 5555H Write Data: AAH Cycle: 1 Address: 2AAAH Write Data: 55H Cycle: 2 Read Command Sequence Address: AIN Read Data: DOUT Cycle: 1 Address: 5555H Write Data: A0H Cycle: 3 Available for Next Command Address: AIN Write Data: DIN Cycle: 4 526 ILL F40.0 Wait TBP Available for Next Byte 526 ILL F41.1 FIGURE 28: BYTE-PROGRAM ALGORITHM (LPC MODE) FIGURE 27: READ COMMAND SEQUENCE (LPC MODE) ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 29 526 2 Megabit LPC Flash SST49LF020 Advance Information Block-Erase Command Sequence Sector-Erase Command Sequence Address: 5555H Write Data: AAH Cycle: 1 Address: 5555H Write Data: AAH Cycle: 1 Address: 2AAAH Write Data: 55H Cycle: 2 Address: 2AAAH Write Data: 55H Cycle: 2 Address: 5555H Write Data: 80H Cycle: 3 Address: 5555H Write Data: 80H Cycle: 3 Address: 5555H Write Data: AAH Cycle: 4 Address: 5555H Write Data: AAH Cycle: 4 Address: 2AAAH Write Data: 55H Cycle: 5 Address: 2AAAH Write Data: 55H Cycle: 5 Address: BAX Write Data: 50H Cycle: 6 Address: SAX Write Data: 30H Cycle: 6 Wait TBE Wait TSE Block erased to FFH Sector erased to FFH Available for Next Command Available for Next Command 526 ILL F43.1 FIGURE 29: ERASE COMMAND SEQUENCES (LPC MODE) ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 30 526 2 Megabit LPC Flash SST49LF020 Advance Information Software Product ID Entry Command Sequence Software Product ID Exit & Reset Command Sequence Address: 5555H Write Data: AAH Cycle: 1 Address: 5555H Write Data: AAH Cycle: 1 Address: XXXXH Write Data: F0H Cycle: 1 Address: 2AAAH Write Data: 55H Cycle: 2 Address: 2AAAH Write Data: 55H Cycle: 2 Wait TIDA Address: 5555H Write Data: 90H Cycle: 3 Address: 5555H Write Data: F0H Cycle: 3 Available for Next Command Wait TIDA Wait TIDA Address: 0001H Read Data: BFH Cycle: 4 Available for Next Command 526 ILL F44.1 Address: 0002H Read Data: Cycle: 5 Available for Next Command FIGURE 30: SOFTWARE PRODUCT COMMAND FLOWCHARTS (LPC MODE) ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 31 526 2 Megabit LPC Flash SST49LF020 Advance Information Start Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: A0H Address: 5555H Load Byte Address/Byte Data Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed 526 ILL F36.1 FIGURE 31: BYTE-PROGRAM ALGORITHM (PP MODE) ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 32 526 2 Megabit LPC Flash SST49LF020 Advance Information Internal Timer Toggle Bit Data# Polling ByteProgram/Erase Initiated ByteProgram/Erase Initiated ByteProgram/Erase Initiated Wait TBP, TSCE, TBE, or TSE Read byte Read DQ7 Read same byte Program/Erase Completed No Is DQ7 = true data? Yes No Does DQ6 match? Program/Erase Completed Yes Program/Erase Completed 526 ILL F37.0 FIGURE 32: WAIT OPTIONS (PP MODE) ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 33 526 2 Megabit LPC Flash SST49LF020 Advance Information Software Product ID Entry Command Sequence Software Product ID Exit & Reset Command Sequence Write data: AAH Address: 5555H Write data: AAH Address: 5555H Write data: F0H Address: XXH Write data: 55H Address: 2AAAH Write data: 55H Address: 2AAAH Wait TIDA Write data: 90H Address: 5555H Write data: F0H Address: 5555H Return to normal operation Wait TIDA Wait TIDA Read Software ID Return to normal operation 526 ILL F38.1 FIGURE 33: SOFTWARE PRODUCT COMMAND FLOWCHARTS (PP MODE) ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 34 526 2 Megabit LPC Flash SST49LF020 Advance Information Chip-Erase Command Sequence Block-Erase Command Sequence Sector-Erase Command Sequence Write data: AAH Address: 5555H Write data: AAH Address: 5555H Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: 55H Address: 2AAAH Write data: 55H Address: 2AAAH Write data: 80H Address: 5555H Write data: 80H Address: 5555H Write data: 80H Address: 5555H Write data: AAH Address: 5555H Write data: AAH Address: 5555H Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: 55H Address: 2AAAH Write data: 55H Address: 2AAAH Write data: 10H Address: 5555H Write data: 50H Address: BAX Write data: 30H Address: SAX Wait TSCE Wait TBE Wait TSE Chip erased to FFH Block erased to FFH Sector erased to FFH 526 ILL F39.1 FIGURE 34: ERASE COMMAND SEQUENCE (PP MODE) ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 35 526 2 Megabit LPC Flash SST49LF020 Advance Information PRODUCT ORDERING INFORMATION Device Speed SST49LF0x0 - XXX Suffix1 - XX Suffix2 - XX Package Modifier H = 32 pins Package Type N = PLCC W = TSOP (die up) (8mm x 14mm) Operating Temperature C = Commercial = 0°C to +85°C Minimum Endurance 4 = 10,000 cycles Serial Access Clock Frequency 33 = 33 MHz Device Density 020 = 2 Mbit Voltage Range L = 3.0-3.6V Device Family SST49LF020 Valid combinations SST49LF020-33-4C-WH Example: SST49LF020-33-4C-NH Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 36 526 2 Megabit LPC Flash SST49LF020 Advance Information PACKAGING DIAGRAMS TOP VIEW Optional Pin #1 Identifier SIDE VIEW .485 .495 .447 .453 .042 .048 2 1 .106 .112 32 .020 R. MAX. .023 x 30˚ .029 .030 R. .040 .042 .048 .585 .595 BOTTOM VIEW .547 .553 .013 .021 .400 BSC .026 .032 .490 .530 .050 BSC. .015 Min. .075 .095 .050 BSC. .125 .140 Note: .026 .032 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 32.PLCC.NH-ILL.2 4. Coplanarity: 4 mils. 32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC) SST PACKAGE CODE: NH ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 37 526 2 Megabit LPC Flash SST49LF020 Advance Information 1.05 0.95 Pin # 1 Identifier .50 BSC .270 .170 8.10 7.90 0.15 0.05 12.50 12.30 0.70 0.50 14.20 13.80 32.TSOP-WH-ILL.4 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±.05) mm. 4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads. 32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM SST PACKAGE CODE: WH X 14MM Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 www.SuperFlash.com or www.ssti.com ©2001 Silicon Storage Technology, Inc. S71175-02-000 5/01 38 526