SST SST49LF040-33-4C-WH

4 Mbit LPC Flash
SST49LF040
SST49LF0404 Mb LPC Flash
Advance Information
FEATURES:
• LPC Interface Flash
– SST49LF040: 512K x8 (4 Mbit)
• Conforms to Intel LPC Interface Specification 1.0
• Flexible Erase Capability
– Uniform 4 KByte sectors
– Uniform 64 KByte overlay blocks
– 64 KByte Top boot block protection
– Chip-Erase for PP Mode Only
• Single 3.0-3.6V Read and Write Operations
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption
– Active Read Current: 6 mA (typical)
– Standby Current: 10 µA (typical)
• Fast Sector-Erase/Byte-Program Operation
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Chip Rewrite Time: 8 seconds (typical)
– Single-pulse Program or Erase
– Internal timing generation
• Two Operational Modes
– Low Pin Count (LPC) Interface mode for
in-system operation
– Parallel Programming (PP) mode for fast production
programming
• LPC Interface Mode
– 5-signal communication interface supporting
byte Read and Write
– 33 MHz clock frequency operation
– WP# and TBL# pins provide hardware write protect
for entire chip and/or top boot block
– Standard SDP Command Set
– Data# Polling and Toggle Bit for End-of-Write
detection
– 5 GPI pins for system design flexibility
– ID pins for multi-chip selection
– Decode both top and bottom regions of the
system memory map
• Parallel Programming (PP) Mode
– 11-pin multiplexed address and 8-pin data
I/O interface
– Supports fast programming In-System on programmer equipment
• CMOS and PCI I/O Compatibility
• Packages Available
– 32-lead PLCC
– 32-lead TSOP (8mm x 14mm)
PRODUCT DESCRIPTION
The SST49LF040 flash memory devices are designed to
interface with the LPC bus for PC and Internet Appliance
application in compliance with Intel Low Pin Count (LPC)
Interface Specification 1.0. Two interface modes are supported by the SST49LF040: LPC mode for In-System
operation and Parallel Programming (PP) mode to interface
with programmer equipment.
The SST49LF040 flash memory devices are manufactured
with SST’s proprietary, high performance SuperFlash Technology. The split-gate cell design and thick oxide tunneling
injector attain better reliability and manufacturability compared with alternate approaches. The SST49LF040 device
significantly improves performance and reliability, while lowering power consumption. The SST49LF040 device writes
(Program or Erase) with a single 3.0-3.6V power supply. It
uses less energy during Erase and Program than alternative flash memory technologies. The total energy consumed is a function of the applied voltage, current and time
of application. Since for any give voltage range, the SuperFlash technology uses less current to program and has a
©2001 Silicon Storage Technology, Inc.
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1
shorter erase time, the total energy consumed during any
Erase or Program operation is less than alternative flash
memory technologies. The SST49LF040 product provides
a maximum Byte-Program time of 20 µsec. The entire
memory can be erased and programmed byte-by-byte typically in 8 seconds when using status detection features
such as Toggle Bit or Data# Polling to indicate the completion of Program operation. The SuperFlash technology provides fixed Erase and Program time, independent of the
number of Erase/Program cycles that have performed.
Therefore the system software or hardware does not have
to be calibrated or correlated to the cumulative number of
erase cycles as is necessary with alternative flash memory
technologies, whose Erase and Program time increase
with accumulated Erase/Program cycles.
To meet high density, surface mount requirements, the
SST49LF040 device is offered in 32-lead TSOP and 32lead PLCC packages. See Figures 2 and 3 for pin assignments and Table 1 for pin descriptions.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
Intel is a registered trademark of Intel Corporation.
These specifications are subject to change without notice.
4 Mbit LPC Flash
SST49LF040
Advance Information
TABLE OF CONTENTS
PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
LIST OF TABLES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
FUNCTIONAL BLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
MODE SELECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
LPC MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CE# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
LFRAME# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Device Memory Hardware Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Abort Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write Operation Status Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data# Polling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Toggle Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
System Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Multiple Device Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
General Purpose Inputs Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
JEDEC ID Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PARALLEL PROGRAMMING MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Byte-Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sector-Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block-Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chip-Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
14
14
14
14
Write Operation Status Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Data# Polling (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Toggle Bit (DQ6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Hardware Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Software Data Protection (SDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
2
4 Mbit LPC Flash
SST49LF040
Advance Information
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Absolute Maximum Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
AC CHARACTERISTICS (LPC MODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
AC CHARACTERISTICS (PP MODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PRODUCT ORDERING INFORMATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Valid combinations for SST49LF040 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
PACKAGING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
3
4 Mbit LPC Flash
SST49LF040
Advance Information
LIST OF FIGURES
FIGURE 1: Device Memory Map for SST49LF040. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
FIGURE 2: Pin Assignments for 32-lead TSOP (8mm x 14mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
FIGURE 3: Pin Assignments for 32-lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
FIGURE 4: Boot Configuration from the Top of the 4 GByte System Memory Map. . . . . . . . . . . . . . . . . . . 11
FIGURE 5: Boot Configuration from the Bottom of the 4 GByte System Memory Map . . . . . . . . . . . . . . . . 12
FIGURE 6: LCLK Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
FIGURE 7: Reset Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
FIGURE 8: Output Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
FIGURE 9: Input Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
FIGURE 10: Read Cycle Timing Diagram (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
FIGURE 11: Write Cycle Timing Diagram (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
FIGURE 12: Program Cycle Timing Diagram (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
FIGURE 13: Data# Polling Timing Diagram (LPC Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
FIGURE 14: Toggle Bit Timing Diagram (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
FIGURE 15: Sector-Erase Timing Diagram (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
FIGURE 16: Block-Erase Timing Diagram (LPC Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
FIGURE 17: GPI Register Readout Timing Diagram (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
FIGURE 18: Reset Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
FIGURE 19: Read Cycle Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
FIGURE 20: Write Cycle Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
FIGURE 21: Data# Polling Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
FIGURE 22: Toggle Bit Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
FIGURE 23: Byte-Program Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
FIGURE 24: Sector-Erase Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
FIGURE 25: Block-Erase Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
FIGURE 26: Chip-Erase Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
FIGURE 27: Software ID Entry and Read (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
FIGURE 28: Software ID Exit and Reset (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
FIGURE 29: AC Input/Output Reference Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
FIGURE 30: A Test Load Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
FIGURE 31: Read Command Sequence (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
FIGURE 32: Byte-Program Algorithm (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
FIGURE 33: Erase Command Sequences (LPC Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
FIGURE 34: Software Product Command Flowcharts (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
FIGURE 35: Byte-Program Algorithm (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
FIGURE 36: Wait Options (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
FIGURE 37: Software Product Command Flowcharts (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
FIGURE 38: Erase Command Sequence (PP Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
4
4 Mbit LPC Flash
SST49LF040
Advance Information
LIST OF TABLES
TABLE 1: Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
TABLE 2: ID Strapping Values for SST49LF040 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
TABLE 3: General Purpose Inputs Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
TABLE 4: Memory Map Register Addresses (Top of the 4GB System Memory). . . . . . . . . . . . . . . . . . . . 13
TABLE 5: Memory Map Register Addresses (Bottom of the 4GB System Memory) . . . . . . . . . . . . . . . . . 13
TABLE 6: Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
TABLE 7: Operation Modes Selection (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
TABLE 8: Software Command Sequence (All Interfaces) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
TABLE 9: DC Operating Characteristics (All Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
TABLE 10: Recommended System Power-up Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
TABLE 11: Pin Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
TABLE 12: Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
TABLE 13: Clock Timing Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
TABLE 14: Reset Timing Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
TABLE 15: Read/Write Cycle Timing Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
TABLE 16: AC Input/Output Specifications (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
TABLE 17: Interface Measurement Condition Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
TABLE 18: Standard LPC Memory Cycle Definition (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
TABLE 19: Read Cycle Timing Parameters (PP Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
TABLE 20: Program/Erase Cycle Timing Parameters (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
TABLE 21: Reset Timing Parameters (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
5
4 Mbit LPC Flash
SST49LF040
Advance Information
FUNCTIONAL BLOCKS
FUNCTIONAL BLOCK DIAGRAM
TBL#
WP#
INIT#
SuperFlash
Memory
X-Decoder
LAD[3:0]
LCLK
LFRAME#
LPC
Interface
Address Buffers & Latches
Y-Decoder
ID[3:0]
GPI[4:0]
R/C#
A[10:0]
Control Logic
I/O Buffers and Data Latches
Programmer
Interface
DQ[7:0]
OE#
WE#
MODE RST# CE#
562 ILL B1.0
7FFFFH
TBL#
Boot Block
Block 7
70000H
6FFFFH
Block 6
60000H
5FFFFH
Block 5
50000H
4FFFFH
Block 4
40000H
3FFFFH
Block 3
30000H
2FFFFH
WP#
Block 2
20000H
1FFFFH
Block 1
Block 0
(64 KByte)
10000H
0F000H
0EFFFH
03000H
02000H
01000H
00000H
4 KByte Sector 15
4 KByte Sector 2
4 KByte Sector 1
4 KByte Sector 0
562 ILL F03.0
FIGURE 1: DEVICE MEMORY MAP
FOR
SST49LF040
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
6
4 Mbit LPC Flash
SST49LF040
Advance Information
PIN DESCRIPTION
NC
NC
NC
NC (CE#)
MODE (MODE)
A10 (GPI4)
R/C# (LCLK)
VDD (VDD)
NC
RST# (RST#)
A9 (GPI3)
A8 (GPI2)
A7 (GPI1)
A6 (GPI0)
A5 (WP#)
A4 (TBL#)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Standard Pinout
Top View
Die Up
OE# (INIT#)
WE# (LFRAME#)
VDD (VDD)
DQ7 (RES)
DQ6 (RES)
DQ5 (RES)
DQ4 (RES)
DQ3 (LAD3)
VSS (VSS)
DQ2 (LAD2)
DQ1 (LAD1)
DQ0 (LAD0)
A0 (ID0)
A1 (ID1)
A2 (ID2)
A3 (ID3)
562 ILL F03a.0
( ) Designates LPC Mode
NC
2
1
14MM)
A10 (GPI4)
RST# (RST#)
3
X
R/C# (LCLK)
A9 (GPI3)
4
VDD (VDD)
A8 (GPI2)
FIGURE 2: PIN ASSIGNMENTS FOR 32-LEAD TSOP (8MM
32 31 30
29
A7(GPI1)
5
A6 (GPI0)
6
28
NC (CE#)
A5 (WP#)
7
27
NC
A4 (TBL#)
8
26
NC
A3 (ID3)
9
25
VDD (VDD)
A2 (ID2)
10
24
OE# (INIT#)
A1 (ID1)
11
23
WE# (LFRAME#)
A0 (ID0)
12
22
NC
DQ0 (LAD0)
13
21
14 15 16 17 18 19 20
( ) Designates LPC Mode
DQ7 (RES)
DQ6 (RES)
DQ5 (RES)
DQ4 (RES)
DQ3 (LAD3)
VSS (VSS)
DQ2 (LAD2)
DQ1 (LAD1)
32-lead PLCC
Top View
MODE (MODE)
562 ILL F03b.0
FIGURE 3: PIN ASSIGNMENTS FOR 32-LEAD PLCC
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
7
4 Mbit LPC Flash
SST49LF040
Advance Information
TABLE 1: PIN DESCRIPTION
Interface
Type1 PP LPC Functions
I
X
Inputs for low-order addresses during Read and Write operations. Addresses are
internally latched during a Write cycle. For the programming interface, these
addresses are latched by R/C# and share the same pins as the high-order
address inputs.
DQ7-DQ0 Data
I/O
X
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle. The outputs are in tri-state when
OE# is high.
OE#
Output Enable
I
X
To gate the data output buffers.
WE#
Write Enable
I
X
To control the Write operations.
MODE
Interface
I
X
X
This pin determines which interface is operational. When held high, programmer
Mode Select
mode is enabled and when held low, LPC mode is enabled. This pin must be
setup at power-up or before return from reset and not change during device operation. This pin must be held high (VIH) for PP mode and low (VIL) for LPC mode.
INIT#
Initialize
I
X
This is the second reset pin for in-system use. This pin is internally combined
with the RST# pin; If this pin or RST# pin is driven low, identical operation is
exhibited.
ID[3:0]
Identification
I
X
These four pins are part of the mechanism that allows multiple parts to be attached
or
Inputs
to the same bus. These pins are internally pulled-down with a resistor between 20ID[3:1]
100 KΩ
GPI[4:0]
General
I
X
These individual inputs can be used for additional board flexibility. The state of
Purpose Inputs
these pins can be read through LPC registers. These inputs should be at their
desired state before the start of the PCI clock cycle during which the read is
attempted, and should remain in place until the end of the Read cycle. Unused
GPI pins must not be floated.
TBL#
Top Block Lock
I
X
When low, prevents programming to the boot block sectors at top of memory.
When TBL# is high it disables hardware write protection for the top block sectors.
This pin cannot be left unconnected.
LAD[3:0] Address and
I/O
X
To provide LPC control signals, as well as addresses and Command
Data
Inputs/Outputs data.
LCLK
Clock
I
X
To provide a clock input to the control unit
LFRAME# Frame
I
X
To indicate start of a data transfer operation; also used to abort an LPC cycle
in progress.
RST#
Reset
I
X
X
To reset the operation of the device
WP#
Write Protect
I
X
When low, prevents programming to all but the highest addressable blocks.
When WP# is high it disables hardware write protection for these blocks.
This pin cannot be left unconnected.
I
X
Select for the Programming interface, this pin determines whether the address
R/C#
Row/Column
Select
pins are pointing to the row addresses, or to the column addresses.
RES
Reserved
X
These pins must be left unconnected.
Power Supply
PWR X
X
To provide power supply (3.0-3.6V)
VDD
VSS
Ground
PWR X
X
Circuit ground (0V reference)
CE#
Chip Enable
I
X
This signal must be asserted to select the device. When CE# is low, the device
is enabled. CE# must remain low during internal Write (Program or Erase)
operations. When CE# is high, the device is placed in low power Standby mode.
NC
No Connection
I
X
X
Unconnected pins.
Symbol
A10-A0
Pin Name
Address
T1.4 562
1. I=Input, O=Output
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
8
4 Mbit LPC Flash
SST49LF040
Advance Information
MODE SELECTION
The SST49LF040 flash memory devices can operate in
two distinct interface modes: the LPC mode and the Parallel Programming (PP) mode. The mode pin is used to set
the interface mode selection. If the mode pin is set to logic
High, the device is in PP mode; while if the mode pin is set
Low, the device is in the LPC mode. The mode selection
pin must be configured prior to device operation. The mode
pin is internally pulled down if the pin is left unconnected. In
LPC mode, the device is configured to its host using standard LPC interface protocol. Communication between Host
and the SST49LF040 occurs via the 4-bit I/O communication signals, LAD [3:0] and LFRAME#. In PP mode, the
device is programmed via an 11-bit address and an 8-bit
data I/O parallel signals. The address inputs are multiplexed in row and column selected by control signal R/C#
pin. The row addresses are mapped to the higher internal
addresses, and the column addresses are mapped to the
lower internal addresses. See Figure 1, the Device Memory Map, for address assignments.
An active low signal at the TBL# pin prevents Program and
Erase operations of the top boot sectors. When TBL# pin is
held high, the write protection of the top boot sectors is disabled. The WP# pin serves the same function for the
remaining sectors of the device memory. The TBL# and
WP# pins write protection functions operate independently
of one another.
Both TBL# and WP# pins must be set to their required protection states prior to starting a Program or Erase operation. A logic level change occurring at the TBL# or WP# pin
during a Program or Erase operation could cause unpredictable results.
Reset
A VIL on INIT# or RST# pin initiates a device reset. INIT#
and RST# pins have the same function internally. It is
required to drive INIT# or RST# pins low during a system
reset to ensure proper CPU initialization. During a Read
operation, driving INIT# or RST# pins low deselects the
device and places the output drivers, LAD[3:0], in a highimpedance state. The reset signal must be held low for a
minimal duration of time TRSTP. A reset latency will occur if
a reset procedure is performed during a Program or Erase
operation. See Table 14, Reset Timing Parameters, for
more information. A device reset during an active Program
or Erase will abort the operation and memory contents may
become invalid due to data being altered or corrupted from
an incomplete Erase or Program operation.
LPC MODE
CE#
The CE# pin, enables and disables the SST49LF040, controlling Read and Write access of the device. To enable the
SST49LF040, the CE# pin must be driven low one clock
cycle prior to LFRAME# being driven low. CE# must
remain active low during internal Write (Erase or Program)
operations. The device will enter the Standby mode when
internal Write operations are completed and CE# is high.
Device Operation
The LPC mode uses a 5-signal communication interface, a
4-bit address/data bus, LAD[3:0], and a control line,
LFRAME#, to control operations of the SST49LF040.
Cycle type operations such as Memory Read and Memory
Write are defined in Intel Low Pin Count Interface Specification, Revision 1.0. JEDEC Standard SDP (Software
Data Protection) Program and Erase commands
sequences are incorporated into the standard LPC memory cycles. See Figure 12 through Figure 17 timing diagrams for command sequences.
LFRAME#
The LFRAME# signifies the start of a frame or the termination of a broken frame. Asserting LFRAME# for one or
more clock cycle and driving a valid START value on
LAD[3:0] will initiate device operation. The device will enter
the Standby mode when internal operations are completed
and LFRAME# is high.
Device Memory Hardware Write Protection
The Top Boot Lock (TBL#) and Write Protect (WP#) pins
are provided for hardware write protection of device memory in the SST49LF040. The TBL# pin is used to write protect 16 boot sectors (64 KByte) at the highest memory
address range for the SST49LF040. WP# pin write protects the remaining sectors in the flash memory.
LPC signals are transmitted via the 4-bit Address/Data bus
(LAD[3:0]), and follow a particular sequence, depending on
whether they are Read or Write operations. The standard
LPC memory cycle is defined in Table 18.
Both LPC Read and Write operations start in a similar way
as shown in Figures 10 and 11 timing diagrams. The host
(which is the term used here to describe the device driving
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
9
4 Mbit LPC Flash
SST49LF040
Advance Information
Data# Polling
the memory) asserts LFRAME# for one or more clocks
and drives a start value on the LAD[3:0] bus.
When the SST49LF040 device is in the internal Program
operation, any attempt to read D[7] will produce the complement of the true data. Once the Program operation is
completed, D[7] will produce true data. Note that even
though D[7] may have valid data immediately following the
completion of an internal Write operation, the remaining
data outputs may still be invalid: valid data on the entire
data bus will appear in subsequent successive Read
cycles. During internal Erase operation, any attempt to
read D[7] will produce a ‘0’. Once the internal Erase operation is completed, D[7] will produce a ‘1’. Proper status will
not be given using Data# Polling if the address is in the
invalid range.
At the beginning of an operation, the host may hold the
LFRAME# active for several clock cycles, and even change
the Start value. The LAD[3:0] bus is latched every rising
edge of the clock. On the cycle in which LFRAME# goes
inactive, the last latched value is taken as the Start value.
CE# must be asserted one cycle before the start cycle to
select the SST49LF040 for Read and Write operations.
Once the SST49LF040 identifies the operation as valid (a
start value of all zeros), it next expects a nibble that indicates whether this is a memory Read or Write cycle. Once
this is received, the device is now ready for the Address
and Data cycles. For Write operation the Data cycle will follow the Address cycle, and for Read operation TAR and
SYNC cycles occur between the Address and Data cycles.
At the end of every operation, the control of the bus must
be returned to the host by a 2-clock TAR cycle.
Toggle Bit
During the internal Program or Erase operation, any consecutive attempts to read D[6] will produce alternating 0s and
1s, i.e., toggling between 0 and 1. When the internal Program or Erase operation is completed, the toggling will stop.
Abort Mechanism
If LFRAME# is driven low for one or more clock cycles during a LPC cycle, the cycle will be terminated and the device
will wait for the ABORT command. The host must drive the
LAD[3:0] with ‘1111b’ (ABORT command) to return the
device to the ready mode. If abort occurs during the internal write cycle, the data may be incorrectly programmed or
erased. It is required to wait for the Write operation to complete prior to initiation of the abort command. It is recommended to check the write status with Data# Polling D[7] or
Toggle Bit D[6]. One other option is to wait for the fixed write
time to expire.
System Memory Mapping
The LPC address sequence is 32 bits long. The
SST49LF040 will respond to addresses mapped into the
top of the 4GB memory space from FFFF FFFFH to
FF00 0000H or bottom of the 4GB memory space from
00000 000H to 00FF FFFFFH. Address bits A18-A0 are
decoded as memory addresses for SST49LF040, A22-A19
are device ID strapping bits, A23 directs Reads and Writes
to memory locations (A23 = 1) or to register access locations (A23 = 0).
Refer to Multiple Device Selection for more detail in device
ID strapping decoding. Refer to Figures 4 and 5 for System
Memory Boot Configuration.
Write Operation Status Detection
The SST49LF040 device provides two software means to
detect the completion of a Write (Program or Erase) cycle,
in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling D[7]
and Toggle Bit D[6]. The End-of-Write detection mode is
incorporated into the LPC Read Cycle. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read
may be simultaneous with the completion of the Write
cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either
D[7] or D[6]. In order to prevent spurious rejection, if an
erroneous result occurs, the software routine should
include a loop to read the accessed location an additional
two (2) times. If both Reads are valid, then the device has
completed the Write cycle, otherwise the rejection is valid.
Multiple Device Selection
Multiple LPC Flash devices may be strapped to increase
memory densities in a system. The four ID strapping pins,
ID[3:0], allow up to 16 devices to be attached to the same
bus by using different ID strapping in a system. Equal density must be used with multiple devices. BIOS support, bus
loading or the attaching bridge may limit this number. The
maximum “window” of the LPC array visible at one time is
16 MByte.
Applications that boot from the top address of the 4 GByte
system memory map; the ID strapping is sequentially
incremented downward as shown in Figure 4. For applications that boot from the bottom address of the 4 GByte system memory map, the ID strapping increments upward but
non-sequentially as shown in Figure 5.
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
10
4 Mbit LPC Flash
SST49LF040
Advance Information
With hardware strapping, ID bits in the address field is
included in every LPC address memory cycle. The address
bits [A22: A19] are used to select the device with proper
IDs. The ID strapping bits in the address field will be
decoded depending on where the device is mapped on the
4 GByte system memory map. See Table 2 for ID address
bits decoding. The device will compare these bits with
ID[3:0]’s strapping values. If there is a mismatch, the device
will ignore the remainder of the cycle.
(Boot Block)
FFFF FFFFH
Boot Device #0
(Boot Block)
Device #1
(Boot Block)
TABLE 2: ID STRAPPING VALUES
Hardware
Strapping
Device #
FOR
SST49LF040
Device #2
Address Bits [A22-A19]
Decoding1
4 GByte System Memory
ID[3:0]
Top
Bottom
0 (Boot device)
0000
1111b
0001b
1
0001
1110b
0000b
2
0010
1101b
0011b
3
0011
1100b
0010b
4
0100
1011b
0101b
5
0101
1010b
0100b
6
0110
1001b
0111b
7
0111
1000b
0110b
8
1000
0111b
1001b
9
1001
0110b
1000b
10
1010
0101b
1011b
11
1011
0100b
1010b
12
1100
0011b
1101b
13
1101
0010b
1100b
14
1110
0001b
1111b
15
1111
0000b
1110b
(Boot Block)
8 MByte
Memory Access
Device #3
(Boot Block)
Device #14
(Boot Block)
Device #15
FF80 0000H
FF7F FFFFH
Device #0
Device #1
Device #2
T2.3 562
1. Address bits A22-A19 decoding for multiple device selection
depends on whether the device is mapped from the top of the
4GB system memory map or from the bottom of the 4GB
system memory map.
Device #3
8 MByte
Register Access
Device #14
Device #15
FF00 0000H
562 ILL F01.1
FIGURE 4: BOOT CONFIGURATION FROM THE TOP
OF THE 4 GBYTE SYSTEM MEMORY MAP
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
11
4 Mbit LPC Flash
SST49LF040
Advance Information
Registers
There are two registers available on the SST49LF040, the
General Purpose Inputs Registers (GPI_REG) and the
JEDEC ID Registers. Since multiple LPC memory devices
may be used to increase memory densities, these registers
appear at its respective address location in the 4 GByte
system memory map. Unused register locations will read
as 00H. Any attempt to read registers during internal Write
operation will respond as “Write Operation Status Detection” (Data# Polling or Toggle Bit). Tables 4 and 5 list
GPI_REG and JEDEC ID address locations for
SST49LF040 with its respective device strapping.
00FF FFFFH
Device #14
Device #15
Device #2
8 MByte
Register Access
TABLE 3: GENERAL PURPOSE INPUTS REGISTER
Device #3
Pin #
Device #0
Bit
Function
32-PLCC
32-TSOP
7:5
Reserved
-
-
4
GPI[4]
Reads status of general
purpose input pin
30
6
3
GPI[3]
Reads status of general
purpose input pin
3
11
2
GPI[2]
Reads status of general
purpose input pin
4
12
1
GPI[1]
Reads status of general
purpose input pin
5
13
0
GPI[0]
Reads status of general
purpose input pin
6
14
Device #1
(Boot Block)
0080 0000H
007F FFFFH
Device #14
(Boot Block)
Device #15
(Boot Block)
Device #2
(Boot Block)
8 MByte
Memory Access
T3.1 562
Device #3
General Purpose Inputs Register
The GPI_REG (General Purpose Inputs Register) passes
the state of GPI[4:0] pins at power-up on the SST49LF040.
It is recommended that the GPI[4:0] pins be in the desired
state before LFRAME# is brought low for the beginning of
the next bus cycle, and remain in that state until the end of
the cycle. There is no default value since this is a passthrough register. See Table 3, General Purpose Inputs
Register, for the GPI_REG bits and functions and Tables 4
and 5 for memory address location for its respective device
strapping.
(Boot Block)
Boot Device #0
(Boot Block)
Device #1
0000 0000H
562 ILL F02.3
FIGURE 5: BOOT CONFIGURATION FROM THE
BOTTOM OF THE 4 GBYTE SYSTEM
MEMORY MAP
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
12
4 Mbit LPC Flash
SST49LF040
Advance Information
JEDEC ID Registers
tive JEDEC ID location. Register is not available for Read
when the device is in Erase/Program operation. Unused
register locations will read as 00H.
The JEDEC ID registers identify the device as
SST49LF040 and manufacturer as SST in LPC mode. See
Tables 4 and 5 for memory address location for its respecTABLE 4: MEMORY MAP REGISTER ADDRESSES (TOP
OF THE
4GB SYSTEM MEMORY)
JEDEC ID
Device #
GPI_REG
Manufacturer
Device
0
FF7C 0100H
FF7C 0000H
FF7C 0001H
1
FF74 0100H
FF74 0000H
FF74 0001H
2
FF6C 0100H
FF6C 0000H
FF6C 0001H
3
FF64 0100H
FF64 0000H
FF64 0001H
4
FF5C 0100H
FF5C 0000H
FF5C 0001H
5
FF54 0100H
FF54 0000H
FF54 0001H
6
FF4C 0100H
FF4C 0000H
FF4C 0001H
7
FF44 0100H
FF44 0000H
FF44 0001H
8
FF3C 0100H
FF3C 0000H
FF3C 0001H
9
FF34 0100H
FF34 0000H
FF34 0001H
10
FF2C 0100H
FF2C 0000H
FF2C 0001H
11
FF24 0100H
FF24 0000H
FF24 0001H
12
FF1C 0100H
FF1C 0000H
FF1C 0001H
13
FF14 0100H
FF14 0000H
FF14 0001H
14
FF0C 0100H
FF0C 0000H
FF0C 0001H
15
FF04 0100H
FF04 0000H
FF04 0001H
T4.5 554
TABLE 5: MEMORY MAP REGISTER ADDRESSES (BOTTOM
OF THE
4GB SYSTEM MEMORY)
JEDEC ID
Device #
GPI_REG
Manufacturer
Device
0
008C 0100H
008C 0000H
008C 0001H
1
0084 0100H
0084 0000H
0084 0001H
2
009C 0100H
009C 0000H
009C 0001H
3
0094 0100H
0094 0000H
0094 0001H
4
00AC 0100H
00AC 0000H
00AC 0001H
5
00A4 0100H
00A4 0000H
00A4 0001H
6
00BC 0100H
00BC 0000H
00BC 0001H
7
00B4 0100H
00B4 0000H
00B4 0001H
8
00CC 0100H
00CC 0000H
00CC 0001H
9
00C4 0100H
00C4 0000H
00C4 0001H
10
00DC 0100H
00DC 0000H
00DC 0001H
11
00D4 0100H
00D4 0000H
00D4 0001H
12
00EC 0100H
00EC 0000H
00EC 0001H
13
00E4 0100H
00E4 0000H
00E4 0001H
14
00FC 0100H
00FC 0000H
00FC 0001H
15
00F4 0100H
00F4 0000H
00F4 0001H
T5.5 554
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
13
4 Mbit LPC Flash
SST49LF040
Advance Information
PARALLEL PROGRAMMING MODE
Block-Erase Operation
The Block-Erase Operation allows the system to erase the
device in 64 KByte uniform block size. The Block-Erase
operation is initiated by executing a six-byte command load
sequence for Software Data Protection with Block-Erase
command (50H) and block address. The internal BlockErase operation begins after the sixth WE# pulse. The
End-of-Erase can be determined using either Data# Polling
or Toggle Bit methods. See Figure 25 for Block-Erase timing waveforms. Any commands written during the BlockErase operation will be ignored.
Reset
Driving the RST# low will initiate a hardware reset of the
SST49LF040.
Device Operation
Commands are used to initiate the memory operation functions of the device. The data portion of the software command sequence is latched on the rising edge of WE#.
During the software command sequence the row address
is latched on the falling edge of R/C# and the column
address is latched on the rising edge of R/C#.
Chip-Erase Operation
The SST49LF040 device provides a Chip-Erase operation,
which allows the user to erase the entire memory array to
the “1s” state. This is useful when the entire device must be
quickly erased.
Read
The Read operation of the SST49LF040 device is controlled by OE#. OE# is the output control and is used to
gate data from the output pins. Refer to the Read cycle timing diagram, Figure 19, for further details.
The Chip-Erase operation is initiated by executing a sixbyte Software Data Protection command sequence with
Chip-Erase command (10H) with address 5555H in the last
byte sequence. The internal Erase operation begins with
the rising edge of the sixth WE#. During the internal Erase
operation, the only valid read is Toggle Bit or Data# Polling.
See Table 8 for the command sequence, Figure 26 for
Chip-Erase timing diagram, and Figure 38 for the flowchart.
Any commands written during the Chip-Erase operation
will be ignored.
Byte-Program Operation
The SST49LF040 device is programmed on a byte-by-byte
basis. Before programming, one must ensure that the sector in which the byte is programmed is fully erased. The
Byte-Program operation is initiated by executing a fourbyte-command load sequence for Software Data Protection with address (BA) and data in the last byte sequence.
During the Byte-Program operation, the row address (A10A0) is latched on the falling edge of R/C# and the column
address (A21-A11) is latched on the rising edge of R/C#.
The data bus is latched on the rising edge of WE#. The
Program operation, once initiated, will be completed, within
20 µs. See Figure 23 for Program operation timing diagram
and Figure 35 for its flowchart. During the Program operation, the only valid reads are Data# Polling and Toggle Bit.
During the internal Program operation, the host is free to
perform additional tasks. Any commands written during the
internal Program operation will be ignored.
Write Operation Status Detection
The SST49LF040 device provides two software means to
detect the completion of a Write (Program or Erase) cycle,
in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling
(DQ7) and Toggle Bit (DQ6). The End-of-Write detection
mode is enabled after the rising edge of WE# which initiates the internal Program or Erase operation.
The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the Write cycle, otherwise the rejection is valid.
Sector-Erase Operation
The Sector-Erase operation allows the system to erase the
device on a sector-by-sector basis. The sector architecture
is based on uniform sector size of 4 KByte. The SectorErase operation is initiated by executing a six-byte command load sequence for Software Data Protection with
Sector-Erase command (30H) and sector address (SA) in
the last bus cycle. The internal Erase operation begins after
the sixth WE# pulse. The End-of-Erase can be determined
using either Data# Polling or Toggle Bit methods. See Figure 24 for Sector-Erase timing waveforms. Any commands
written during the Sector-Erase operation will be ignored.
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
14
4 Mbit LPC Flash
SST49LF040
Advance Information
Data# Polling (DQ7)
Software Data Protection (SDP)
When the SST49LF040 device is in the internal Program
operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is
completed, DQ7 will produce true data. Note that even
though DQ7 may have valid data immediately following the
completion of an internal Write operation, the remaining
data outputs may still be invalid: valid data on the entire
data bus will appear in subsequent successive Read
cycles after an interval of 1 µs. During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the
internal Erase operation is completed, DQ7 will produce a
‘1’. The Data# Polling is valid after the rising edge of fourth
WE# pulse for Program operation. For Sector-, Block-, or
Chip-Erase, the Data# Polling is valid after the rising edge
of sixth WE# pulse. See Figure 21 for the Data# Polling timing diagram and Figure 36 for a flowchart. Proper status will
not be given using Data# Polling if the address is in the
invalid range.
The SST49LF040 provides the JEDEC approved Software
Data Protection scheme for all data alteration operation,
i.e., Program and Erase. Any Program operation requires
the inclusion of a series of three-byte sequence. The threebyte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write
operations, e.g., during the system power-up or powerdown. Any Erase operation requires the inclusion of a sixbyte load sequence. The SST49LF040 device is shipped
with the Software Data Protection permanently enabled.
See Table 8 for the specific software command codes. During SDP command sequence, invalid commands will abort
the device to Read mode, within TRC.
Electrical Specifications
The AC and DC specifications for the LPC interface signals (LA0[3:0], LFRAME, LCLCK and RST#) as defined
in Section 4.2.2.4 of the PCI local Bus specification, Rev.
2.1. Refer to Table 9 for the DC voltage and current specifications. Refer to Tables 13 through 16 and Tables 19
through 21 for the AC timing specifications for Clock,
Read, Write, and Reset operations.
Toggle Bit (DQ6)
During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 0s
and 1s, i.e., toggling between 0 and 1. When the internal
Program or Erase operation is completed, the toggling will
stop. The device is then ready for the next operation. The
Toggle Bit is valid after the rising edge of fourth WE# pulse
for Program operation. For Sector-, Block-, or Chip-Erase,
the Toggle Bit is valid after the rising edge of sixth WE#
pulse. See Figure 22 for the Toggle Bit timing diagram and
Figure 36 for a flowchart.
Product Identification
The Product Identification mode identifies the device as the
SST49LF040 and manufacturer as SST.
TABLE 6: PRODUCT IDENTIFICATION
Manufacturer’s ID
Data Protection
Address
Data
0000H
BFH
0001H
51H
Device ID
The SST49LF040 device provides both hardware and software features to protect nonvolatile data from inadvertent
writes.
SST49LF040
T6.1 562
Design Considerations
Hardware Data Protection
SST recommends a high frequency 0.1 µF ceramic capacitor to be placed as close as possible between VDD and
VSS less than 1 cm away from the VDD pin of the device.
Additionally, a low frequency 4.7 µF electrolytic capacitor
from VDD to VSS should be placed within 5 cm of the VDD
pin. If you use a socket for programming purposes add an
additional 1-10 µF next to each socket.
Noise/Glitch Protection: A WE# pulse of less than 5 ns will
not initiate a Write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, WE# high will inhibit
the Write operation. This prevents inadvertent writes during
power-up or power-down.
The RST# pin must remain stable at VIH for the entire duration of an Erase operation. WP# must remain stable at VIH
for the entire duration of the Erase and Program operations
for non-boot block sectors. To write data to the top boot
block sectors, the TBL# pin must also remain stable at VIH
for the entire duration of the Erase and Program operations.
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
15
4 Mbit LPC Flash
SST49LF040
Advance Information
TABLE 7: OPERATION MODES SELECTION (PP MODE)
Mode
RST#
OE#
WE#
DQ
Address
Read
VIH
VIH
VIH
VIL
VIH
DOUT
AIN
VIH
VIH
VIL
DIN
AIN
VIL
X1
Sector or Block address,
XXH for Chip-Erase
Program
Erase
Reset
VIL
X
X
High Z
X
Write Inhibit
VIH
VIL
X
High Z/DOUT
X
X
X
X
VIH
VIL
VIH
VIH
High Z/DOUT
Product Identification
Manufacturer’s ID (BFH)
Device ID2
See Table 8
T7.2 562
1. X can be VIL or VIH, but no other value.
2. Device ID 51H for SST49LF040
TABLE 8: SOFTWARE COMMAND SEQUENCE (ALL INTERFACES)
Command
Sequence
1st1
Cycle
2nd1
Cycle
3rd1
Cycle
4th1
Cycle
5th1
Cycle
Addr2
Data
Addr2
Data
Addr2
Data
Addr2
Data
ByteProgram
YYYY 5555H
AAH
YYYY 2AAAH
55H
YYYY 5555H
A0H
PA3
Data
SectorErase
YYYY 5555H
AAH
YYYY 2AAAH
55H
YYYY 5555H
80H
YYYY 5555H
Block-Erase
YYYY 5555H
AAH
YYYY 2AAAH
55H
YYYY 5555H
80H
Chip-Erase6
YYYY 5555H
AAH
YYYY 2AAAH
55H
YYYY 5555H
80H
Software
ID Entry
YYYY 5555H
AAH
Software
ID Exit8
XXXX XXXXH
F0H
Software
ID Exit8
YYYY 5555H
AAH
YYYY 2AAAH
55H
YYYY 5555H
90H
YYYY 2AAAH
55H
YYYY 5555H
F0H
6th1
Cycle
Addr2
Data
Addr2
Data
AAH
YYYY 2AAAH
55H
SAx4
30H
YYYY 5555H
AAH
YYYY 2AAAH
55H
BAx5
50H
YYYY 5555H
AAH
YYYY 2AAAH
55H
YYYY 5555H
10H
Read
ID7
T8.3 562
1. LPC mode uses consecutive Write cycles to complete a command sequence; PP mode uses consecutive bus cycles to complete a
command sequence.
2. YYYY = A[31:16]
In LPC mode, during SDP command sequence, YYYY must be within memory address range specified in Figures 4 and 5.
In PP mode, YYYY can be VIL or VIH.
3. PA = Program Byte address
4. SAx for Sector-Erase Address
5. BAx for Block-Erase Address
6. Chip-Erase is supported in PP mode only
7. SST Manufacturer’s ID = BFH, is read with A0 = 0.
With A18-A1 = 0; 49LF040 Device ID = 51H, is read with A0 = 1.
8. Both Software ID Exit operations are equivalent
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
16
4 Mbit LPC Flash
SST49LF040
Advance Information
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this
datasheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D.C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Package Power Dissipation Capability (Ta=25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE
Range
Commercial
AC CONDITIONS
Ambient Temp
VDD
0°C to +85°C
3.0-3.6V
OF
TEST
Input Rise/Fall Time . . . . . . . . . . . . . . . 3 ns
Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figures 29 and 30
TABLE 9: DC OPERATING CHARACTERISTICS (ALL INTERFACE)
Limits
Symbol Parameter
IDD
Min
Max
Units Test Conditions1
Address input=VIL/VIH, at f=1/TRC Min,
VDD=VDD Max
Active VDD Current
Read
12
Write2
mA
OE#=VIL, WE#=VIH, All I/Os open
24
mA
OE#=VIH, VDD=VDD Max
ISB
Standby VDD Current
(LPC Interface)
100
µA
LFRAME#=VIH, f=33 MHz, CE#=VIH
VDD=VDD Max,
All other inputs ≥ 0.9 VDD or ≤ 0.1 VDD
IRY3
Ready Mode VDD Current (LPC Interface)
10
mA
LFRAME#=VIL, f=33 MHz, VDD=VDD Max
All other inputs ≥ 0.9 VDD or ≤ 0.1 VDD
II
Input Current for IC:
ID[3:0] pins for SST49LF040
ID[3:1] pins for SST49LF080A
200
µA
VIN=GND to VDD, VDD=VDD Max
ILI
Input Leakage Current
1
µA
VIN=GND to VDD, VDD=VDD Max
ILO
Output Leakage Current
1
µA
VOUT=GND to VDD, VDD=VDD Max
VIHI
INIT# Input High Voltage
1.1
VDD+0.5
V
VDD=VDD Max
VILI
INIT# Input Low Voltage
-0.5
0.4
V
VDD=VDD Max
VIL
Input Low Voltage
-0.5
0.3 VDD
V
VDD=VDD Min
VIH
Input High Voltage
0.5 VDD
VDD+0.5
V
VDD=VDD Max
VOL
Output Low Voltage
0.1 VDD
V
IOL=1500µA, VDD=VDD Min
VOH
Output High Voltage
V
IOH=-500 µA, VDD=VDD Min
0.9 VDD
T9.1 562
1. Test conditions apply to PP mode.
2. IDD active while Erase or Program is in progress.
3. The device is in Ready Mode when no activity is on the LPC bus.
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
17
4 Mbit LPC Flash
SST49LF040
Advance Information
TABLE 10: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Minimum
Units
TPU-READ1
Power-up to Read Operation
100
µs
Power-up to Write Operation
100
µs
TPU-WRITE
1
T10.0 562
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter
TABLE 11: PIN CAPACITANCE
(VDD=3.3V, Ta=25 °C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
Maximum
CI/O1
I/O Pin Capacitance
VI/O=0V
12 pF
Input Capacitance
VIN=0V
6 pF
CIN
1
T11.0 562
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 12: RELIABILITY CHARACTERISTICS
Symbol
NEND
1
Parameter
Minimum
Specification
Units
Endurance
10,000
Cycles
JEDEC Standard A117
100
Years
JEDEC Standard A103
100 + IDD
mA
TDR1
Data Retention
ILTH1
Latch Up
Test Method
JEDEC Standard 78
T12.0 562
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 13: CLOCK TIMING PARAMETERS (LPC MODE)
Symbol
Parameter
Min
Max
Units
TCYC
LCLK Cycle Time
30
ns
THIGH
LCLK High Time
11
ns
TLOW
LCLK Low Time
11
-
LCLK Slew Rate (peak-to-peak)
1
-
RST# or INIT# Slew Rate
50
ns
4
V/ns
mV/ns
T13.0 562
Tcyc
Thigh
0.6 VDD
Tlow
0.5 VDD
0.4 VDD p-to-p
(minimum)
0.4 VDD
0.3 VDD
0.2 VDD
562 ILL F05.0
FIGURE 6: LCLK WAVEFORM
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
18
4 Mbit LPC Flash
SST49LF040
Advance Information
TABLE 14: RESET TIMING PARAMETERS (LPC MODE), VDD=3.0-3.6V
Symbol
Parameter
Min
TPRST
VDD stable to Reset Low
TKRST
TRSTP
TRSTF
RST# Low to Output Float
TRST1
RST# High to LFRAME# Low
TRSTE
RST# Low to reset during Sector-/Block-Erase or Program
Max
Units
1
ms
Clock Stable to Reset Low
100
µs
RST# Pulse Width
100
ns
48
1
ns
µs
10
µs
T14.0 562
1. There will be a latency of TRSTE if a reset procedure is performed during a programming or erase operation,
VDD
TPRST
CLK
TKRST
TRSTP
RST#/INIT#
TRSTE
TRSTF
TRST
Sector-/Block-Erase
or Program operation
aborted
LAD[3:0]
LFRAME#
562 ILL F06.0
FIGURE 7: RESET TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
19
4 Mbit LPC Flash
SST49LF040
Advance Information
AC CHARACTERISTICS (LPC MODE)
TABLE 15: READ/WRITE CYCLE TIMING PARAMETERS (LPC MODE), VDD=3.0-3.6V
Symbol
Parameter
Min
Max
Units
TCYC
Clock Cycle Time
30
ns
TSU
Data Set Up Time to Clock Rising
7
ns
TDH
Clock Rising to Data Hold Time
0
TVAL1
Clock Rising to Data Valid
2
TBP
Byte Programming Time
20
µs
TSE
Sector-Erase Time
25
ms
TBE
Block-Erase Time
25
ms
TON
Clock Rising to Active (Float to Active Delay)
TOFF
Clock Rising to Inactive (Active to Float Delay)
ns
11
ns
2
ns
28
ns
T15.0 562
1. Minimum and maximum times have different loads. See PCI spec
TABLE 16: AC INPUT/OUTPUT SPECIFICATIONS (LPC MODE)
Symbol
IOH(AC)
Parameter
Switching Current High
Min
Max
Units
0 < VOUT ≤ 0.3VDD
0.3VDD < VOUT < 0.9VDD
0.7VDD < VOUT < VDD
-32 VDD
mA
VOUT = 0.7VDD
Equation D1
mA
mA
VDD >VOUT ≥ 0.6VDD
0.6VDD > VOUT > 0.1VDD
0.18VDD > VOUT > 0
38 VDD
mA
VOUT = 0.18VDD
mA
-3 < VIN ≤-1
Equation C1
(Test Point)
IOL(AC)
Switching Current Low
16 VDD
26.7 VOUT
(Test Point)
ICL
Low Clamp Current
-25+(VIN+1)/0.015
25+(VIN-VDD-1)/0.015
Conditions
mA
mA
-12 VDD
-17.1(VDD-VOUT)
ICH
High Clamp Current
mA
VDD+4 > VIN ≥ VDD+1
slewr2
Output Rise Slew Rate
1
4
V/ns
0.2VDD-0.6VDD load
slewf2
Output Fall Slew Rate
1
4
V/ns
0.6VDD-0.2VDD load
T16.0 562
1. See PCI spec.
2. PCI specification output load is used.
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
20
4 Mbit LPC Flash
SST49LF040
Advance Information
VTH
LCLK
VTEST
VTL
TVAL
LAD [3:0]
(Valid Output Data)
LAD [3:0]
(Float Output Data)
TON
TOFF
562 ILL F07.0
FIGURE 8: OUTPUT TIMING PARAMETERS
VTH
VTEST
LCLK
VTL
TSU
TDH
LAD [3:0]
(Valid Input Data)
Inputs
Valid
VMAX
562 ILL F08.0
FIGURE 9: INPUT TIMING PARAMETERS
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
21
4 Mbit LPC Flash
SST49LF040
Advance Information
TABLE 17: INTERFACE MEASUREMENT CONDITION PARAMETERS
Symbol
Value
Units
VTH1
0.6 VDD
V
1
0.2 VDD
V
VTEST
0.4 VDD
V
1
0.4 VDD
V
VTL
VMAX
Input Signal Edge Rate
1 V/ns
T17.0 562
1. The input test environment is done with 0.1 VDD of overdrive over VIH and VIL. Timing parameters must be met with no more overdrive than this. VMAX specified the maximum peak-to-peak waveform allowed for measuring input timing. Production testing may use
different voltage values, but must correlate results back to these parameters
TABLE 18: STANDARD LPC MEMORY CYCLE DEFINITION (LPC MODE)
Field
No. of Clocks
START
1
Description
“0000b” appears on LPC bus to indicate the start of cycle
CYCTYPE + DIR
1
Cycle Type: Indicates the type of cycle. Bits 3:2 must be “01b” for memory cycle. Bit 1
indicates the type of transfer “0” for Read, “1” for write. DIR: Indicates the direction of the
transfer. “0b” for Read, “1b” for Write. Bit 0 is reserved. “010Xb” indicates memory Read
cycle; while “011xb” indicates memory Write cycle.
TAR
2
The last component driving LAD[3:0] will drive it to “1111b” during the first clock, and tristate it during the second clock.
ADDR
8
Address Phase for Memory Cycle. LPC supports the 32-bit address protocol. The
addresses transfer most significant nibble first and least significant nibble last. (i.e.,
Address[31:28] on LAD[3:0] first, and Address[3:0] on LAD[3:0] last.)
Sync
N
Synchronize to host or peripheral by adding wait states. “0000b” means Ready, “0101b”
means Short Wait, “0110b” means Long Wait, “1001b” for DMA only, “1010b” means
error, other values are reserved. The SST49LF040 only supports “Ready” sync.
Data
2
Data Phase for Memory Cycle.
The data transfer least significant nibble first and most significant nibble last.
(i.e., DQ[3:0] on LAD[3:0] first, then DQ[7:4] on LAD[3:0] last.)
T18.1 562
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
22
4 Mbit LPC Flash
SST49LF040
Advance Information
TCYC
LCLK
CE#
RST#
LFRAME#
TVAL
LAD[3:0]
Start
Memory
Read
Cycle
0000b
010Xb
1 Clock 1 Clock
Address
TAR
A[31:28] A[27:24] A[23:20] A[19:16] A[15:12]
A[11:8]
A[7:4]
A[3:0]
Load Address in 8 Clocks
1111b
Tri-State
2 Clocks
Sync
0000b
TSU TDH
Data
D[3:0]
Next Start
D[7:4]
TAR
1 Clock Data Out 2 Clocks
0000b
1 Clock
562 ILL F09.0
FIGURE 10: READ CYCLE TIMING DIAGRAM (LPC MODE)
TCYC
LCLK
CE#
RST#
TSU TDH
LFRAME#
LAD[3:0]
Start
Memory
Write
Cycle
0000b
011Xb
1 Clock 1 Clock
Address
Data
A[31:28] A[27:24] A[23:20] A[19:16] A[15:12]
A[11:8]
Load Address in 8 Clocks
A[7:4]
A[3:0]
D[3:0]
D[7:4]
Load Data in 2 Clocks
TAR
Sync
1111b Tri-State
0000b
2 Clocks
1 Clock
Next Start
TAR
0000b
1 Clock
562 ILL F10.0
FIGURE 11: WRITE CYCLE TIMING DIAGRAM (LPC MODE)
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
23
4 Mbit LPC Flash
SST49LF040
Advance Information
LCLK
RST#
CE#
LFRAME#
LAD[3:0]
1st Start
Memory
Write
Cycle
0000b
011Xb
1 Clock 1 Clock
Address1
A[31:28] A[27:24] A[23:20] A[19:16]
Data
0101b
0101b
0101b
Load Address "YYYY 5555H" in 8 Clocks
0101b
1010b
1010b
TAR
1111b
Tri-State 0000b
Load Data "AAH" in 2 Clocks 2 Clocks
Start next
Command
Sync
TAR
1 Clock
1 Clock
Write the 1st command to the device in LPC mode.
LCLK
RST# = VIH
CE# = VIL
LFRAME#
LAD[3:0]
2nd Start
Memory
Write
Cycle
0000b
011Xb
1 Clock 1 Clock
Address1
A[31:28] A[27:24] A[23:20] A[19:16]
Data
0010b
1010b
1010b
Load Address "YYYY 2AAAH" in 8 Clocks
1010b
0101b
TAR
0101b
1111b
Load Data "55H" in 2 Clocks 2 Clocks
Start next
Command
Sync
Tri-State 0000b
TAR
1 Clock
1 Clock
Write the 2nd command to the device in LPC mode.
LCLK
RST# = VIH
CE# = VIL
LFRAME#
Address1
3rd Start
LAD[3:0]
0000b
011Xb
1 Clock 1 Clock
A[31:28] A[27:24] A[23:20] A[19:16]
Data
0101b
0101b
0101b
Load Address "YYYY 5555H" in 8 Clocks
0101b
0000b
TAR
1010b
1111b
Tri-State 0000b
Load Data "A0H" in 2 Clocks 2 Clocks
Start next
Command
Sync
TAR
1 Clock
1 Clock
Write the 3rd command to the device in LPC mode.
LCLK
RST# = VIH
CE# = VIL
LFRAME#
LAD[3:0]
4th Start
Memory
Write
Cycle
0000b
011Xb
1 Clock 1 Clock
Internal
program start
Address1
Data
A[31:28] A[27:24] A[23:20] A[19:16] A[15:12] A[11:8]
Load Ain in 8 Clocks
A[7:4]
A[3:0]
D[3:0]
TAR
D[7:4]
Load Data in 2 Clocks
1111b
Sync
Tri-State 0000b
2 Clocks
1 Clock
TAR
Internal
program start
Write the 4th command (target locations to be programmed) to the device in LPC mode.
562 ILL F11.1
Note 1: YYYYH must be within memory address range specified in Figures 4 and 5.
FIGURE 12: PROGRAM CYCLE TIMING DIAGRAM (LPC MODE)
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
24
4 Mbit LPC Flash
SST49LF040
Advance Information
LCLK
RST#
CE#
LFRAME#
1st Start
LAD[3:0]
Memory
Write
Cycle
0000b 011Xb
1 Clock 1 Clock
Address1
A[31:28] A[27:24] A[23:20]
A[19:16]
Data
A[15:12]
A[11:8]
A[7:4]
A[3:0]
D[3:0]
Dn[7:4]
Load Data in 2 Clocks
Load Address in 8 Clocks
TAR
Sync
1111b Tri-State
0000b
2 Clocks
1 Clock
TAR
Start next
Command
0000b
1 Clock
Write the last command (Program or Erase) to the device in LPC mode.
LCLK
RST# = VIH
CE# = VIL
LFRAME#
Start
LAD[3:0]
0000b
Next start
Memory
Read
Cycle
010Xb
1 Clock 1 Clock
Address1
A[31:28] A[27:24] A[23:20]
A[19:16]
TAR
A[15:12]
A[11:8]
A[7:4]
A[3:0]
1111b
Sync
Tri-State 0000b
2 Clocks
Load Address in 8 Clocks
Read the DQ7 to see if internal write complete or not.
1 Clock
Data
XXXXb
D7#,xxx
TAR
0000b
1 Clock
Data out 2 Clocks
LCLK
RST# = VIH
CE# = VIL
LFRAME#
Start
LAD[3:0]
0000b
Memory
Read
Cycle
010Xb
1 Clock 1 Clock
Next start
Address1
A[31:28] A[27:24] A[23:20]
A[19:16]
TAR
A[15:12]
A[11:8]
A[7:4]
A[3:0]
Load Address in 8 Clocks
1111b Tri-State
2 Clocks
Sync
0000b
Data
XXXXb
D7,xxx
1 Clock Data out 2 Clocks
TAR
0000b
1 Clock
When internal write complete, the DQ7 will equal to D7.
562 ILL F12.1
Note: YYYY must be within memory address range specified in Figures 4 and 5.
FIGURE 13: DATA# POLLING TIMING DIAGRAM (LPC MODE)
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
25
4 Mbit LPC Flash
SST49LF040
Advance Information
LCLK
RST#
CE#
LFRAME#
LAD[3:0]
1st Start
Memory
Write
Cycle
0000b
011Xb
1 Clock 1 Clock
Address1
A[31:28] A[27:24]
A[23:20]
A[19:16]
Data
A[15:12]
A[11:8]
A[7:4]
Load Address in 8 Clocks
A[3:0]
D[3:0]
D[7:4]
Load Data in 2 Clocks
TAR
Start next
Command
Sync
1111b Tri-State
2 Clocks
0000b
TAR
0000b
1 Clock
1 Clock
Write the last command (Program or Erase) to the device in LPC mode.
LCLK
RST# = VIH
CE# = VIL
LFRAME#
Start
LAD[3:0]
0000b
Next start
Memory
Read
Cycle
010Xb
1 Clock 1 Clock
Address1
A[31:28] A[27:24] A[23:20]
A[19:16]
TAR
A[15:12]
A[11:8]
A[7:4]
A[3:0]
1111b
Load Address in 8 Clocks
Sync
Tri-State 0000b
Data
XXXXb
X,D6#,XXb
2 Clocks
1 Clock
Data out 2 Clocks
TAR
Sync
Data
TAR
0000b
1 Clock
Read the DQ6 to see if internal write complete or not.
LCLK
RST# = VIH
CE# = VIL
LFRAME#
Start
LAD[3:0]
0000b
Memory
Read
Cycle
010Xb
1 Clock 1 Clock
Next start
Address1
A[31:28] A[27:24] A[23:20]
A[19:16]
A[15:12]
A[11:8]
A[7:4]
A[3:0]
1111b
Load Address in 8 Clocks
When internal write complete, the DQ6 will stop toggle.
Note: YYYY must be within memory address range specified in Figures 4 and 5.
Tri-State 0000b
2 Clocks
XXXXb
X,D6,XXb
1 Clock Data out 2 Clocks
TAR
0000b
1 Clock
562 ILL F13.2
FIGURE 14: TOGGLE BIT TIMING DIAGRAM (LPC MODE)
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
26
4 Mbit LPC Flash
SST49LF040
Advance Information
LCLK
RST#
CE#
LFRAME#
1st Start
LAD[3:0]
0000b
Memory
Write
Cycle
011Xb
1 Clock 1 Clock
Address1
A[31:28] A[27:24] A[23:20] A[19:16]
Data
0101b
0101b
0101b
Load Address "YYYY 5555H" in 8 Clocks
0101b
1010b
TAR
1010b
1111b
Load Data "AAH" in 2 Clocks 2 Clocks
Start next
Command
Sync
Tri-State 0000b
TAR
1 Clock
1 Clock
Write the 1st command to the device in LPC mode.
LCLK
RST# = VIH
CE# = VIL
LFRAME#
2nd Start
LAD[3:0]
0000b
Memory
Write
Cycle
011Xb
1 Clock 1 Clock
Address1
A[31:28] A[27:24] A[23:20] A[19:16]
Data
0010b
1010b
1010b
1010b
0101b
TAR
0101b
1111b
Load Data "55H" in 2 Clocks 2 Clocks
Load Address "YYYY 2AAAH" in 8 Clocks
Start next
Command
Sync
Tri-State 0000b
TAR
1 Clock
1 Clock
Write the 2nd command to the device in LPC mode.
LCLK
RST# = VIH
CE# = VIL
LFRAME#
3rd Start
Memory
Write
Cycle
0000b 011Xb
LAD[3:0]
1 Clock 1 Clock
Address1
A[31:28] A[27:24] A[23:20] A[19:16]
Data
0101b
0101b
0101b
Load Address "YYYY 5555H" in 8 Clocks
0101b
0000b
TAR
1000b
1111b
Tri-State
Load Data "80H" in 2 Clocks 2 Clocks
Start next
Command
Sync
0000b
TAR
1 Clock
1 Clock
Write the 3rd command to the device in LPC mode.
LCLK
RST# = VIH
CE# = VIL
LFRAME#
4th Start
Memory
Write
Cycle
0000b 011Xb
LAD[3:0]
1 Clock 1 Clock
Address1
A[31:28] A[27:24] A[23:20] A[19:16]
Data
0101b
0101b
0101b
Load Address "YYYY 5555H" in 8 Clocks
0101b
1010b
1010b
TAR
1111b
Tri-State
Load Data "AAH" in 2 Clocks 2 Clocks
Start next
Command
Sync
0000b
TAR
1 Clock
1 Clock
Write the 4th command to the device in LPC mode.
LCLK
RST# = VIH
CE# = VIL
LFRAME#
5th
LAD[3:0]
Memory
Write
Cycle
0000b 011Xb
1 Clock 1 Clock
Address1
A[31:28] A[27:24] A[23:20] A[19:16]
Data
0010b
1010b
1010b
Load Address "YYYY 2AAA" in 8 ClocksH
1010b
0101b
0101b
TAR
Sync
1111b Tri-State
0000b
Load Data "55H" in 2 Clocks 2 Clocks
Start next
Command
TAR
1 Clock
1 Clock
Write the 5th command to the device in LPC mode.
LCLK
RST# = VIH
CE# = VIL
Internal
erase start
LFRAME#
6th Start
LAD[3:0]
0000b
Memory
Write
Cycle
011Xb
1 Clock 1 Clock
Address1
A[31:28] A[27:24] A[23:20] A[19:16]
Data
SAX
XXXXb XXXXb
Load Sector Address in 8 Clocks
XXXXb
0000b
0011b
Load Data “30” in 2 Clocks
TAR
1111b
Tri-State
2 Clocks
Internal
erase start
Sync
0000b
TAR
1 Clock
Write the 6th command (target sector to be erased) to the device in LPC mode.
SAX = Sector Address
Note: YYYY must be within memory address range specified in Figures 4 and 5.
562 ILL F14.1
FIGURE 15: SECTOR-ERASE TIMING DIAGRAM (LPC MODE)
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
27
4 Mbit LPC Flash
SST49LF040
Advance Information
LCLK
RST#
CE#
LFRAME#
1st Start
LAD[3:0]
0000b
Memory
Write
Cycle
011Xb
1 Clock 1 Clock
Address1
Data
A[31:28] A[27:24] A[23:20] A[19:16] 0101b
0101b
0101b
0101b
1010b
1010b
Tri-State 0000b
Load Data "AAH" in 2 Clocks 2 Clocks
Load Address "YYYY 5555H" in 8 Clocks
Write the 1st command to the device in LPC mode.
Start next
Command
Sync
TAR
1111b
TAR
1 Clock
1 Clock
LCLK
RST# = VIH
CE# = VIL
LFRAME#
LAD[3:0]
2nd Start
Memory
Write
Cycle
0000b
011Xb
1 Clock 1 Clock
Address1
A[31:28] A[27:24] A[23:20] A[19:16]
Data
0010b
1010b
1010b
Load Address "YYYY 2AAAH" in 8 Clocks
1010b
0101b
0101b
TAR
1111b Tri-State
Load Data "55H" in 2 Clocks 2 Clocks
Start next
Command
Sync
0000b
TAR
1 Clock
1 Clock
Write the 2nd command to the device in LPC mode.
LCLK
RST# = VIH
CE# = VIL
LFRAME#
3rd Start
LAD[3:0]
0000b
Memory
Write
Cycle
011Xb
1 Clock 1 Clock
Address1
A[31:28] A[27:24] A[23:20] A[19:16]
Data
0101b
0101b
0101b
0101b
0000b
TAR
1000b
1111b Tri-State
Load Data "80H" in 2 Clocks 2 Clocks
Load Address "YYYY 5555H" in 8 Clocks
Start next
Command
Sync
0000b
TAR
1 Clock
1 Clock
Write the 3rd command to the device in LPC mode.
LCLK
RST# = VIH
CE# = VIL
LFRAME#
4th Start
LAD[3:0]
Memory
Write
Cycle
0000b 011Xb
1 Clock 1 Clock
Address1
Data
A[31:28] A[27:24] A[23:20] A[19:16] 0101b
0101b
0101b
0101b
1010b
1010b
TAR
1111b
Tri-State
Load Data "AAH" in 2 Clocks 2 Clocks
Load Address "YYYY 5555H" in 8 Clocks
Write the 4th command to the device in LPC mode.
Start next
Command
Sync
0000b
TAR
1 Clock
1 Clock
LCLK
RST# = VIH
CE# = VIL
LFRAME#
5th
LAD[3:0]
0000b
Memory
Write
Cycle
011Xb
1 Clock 1 Clock
Address1
A[31:28] A[27:24] A[23:20] A[19:16]
Data
0010b
1010b
1010b
Load Address "YYYY 2AAAH" in 8 Clocks
1010b
0101b
0101b
TAR
1111b
Tri-State
Load Data "55H" in 2 Clocks 2 Clocks
Start next
Command
Sync
0000b
TAR
1 Clock
1 Clock
Write the 5th command to the device in LPC mode.
LCLK
RST# = VIH
CE# = VIL
Internal
erase start
LFRAME#
6th Start
LAD[3:0]
0000b
Memory
Write
Cycle
Address1
011Xb
A[31:28] A[27:24] A[23:20] A[19:16]
1 Clock 1 Clock
Data
BAX
Load Block Address in 8 Clocks
XXXXb XXXXb
Write the 6th command (target sector to be erased) to the device in LPC mode.
BAX = Block Address
Note: YYYY must be within memory address range specified in Figures 4 and 5.
XXXXb
0000b
0101b
Load Data “50” in 2 Clocks
TAR
1111b
2 Clocks
Internal
erase start
Sync
Tri-State 0000b
TAR
1 Clock
562 ILL F15.1
FIGURE 16: BLOCK-ERASE TIMING DIAGRAM (LPC MODE)
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
28
4 Mbit LPC Flash
SST49LF040
Advance Information
LCLK
RST#
CE#
LFRAME#
Start
LAD[3:0]
0000b
Memory
Read
Cycle
010Xb
Address1
TAR
A[31:28] A[27:24] A[23:20] A[19:16] A[15:12] A[11:8]
1 Clock 1 Clock
A[7:4]
A[3:0]
Load Address in 8 Clocks
1111b
Tri-State
2 Clocks
Sync
0000b
1 Clock
Start next
Data
D[3:0]
D[7:4]
Data out 2 Clocks
TAR
0000b
1 Clock
562 ILL F16.2
Note: See Tables 4 and 5 Register Addresses
FIGURE 17: GPI REGISTER READOUT TIMING DIAGRAM (LPC MODE)
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
29
4 Mbit LPC Flash
SST49LF040
Advance Information
AC CHARACTERISTICS (PP MODE)
TABLE 19: READ CYCLE TIMING PARAMETERS (PP MODE), VDD=3.0-3.6V
Symbol
Parameter
Min
Max
Units
TRC
Read Cycle Time
270
ns
TRST
RST# High to Row Address Setup
1
µs
TAS
R/C# Address Set-up Time
45
ns
TAH
R/C# Address Hold Time
45
ns
TAA
Address Access Time
120
ns
TOE
Output Enable Access Time
60
ns
TOLZ
OE# Low to Active Output
TOHZ
OE# High to High-Z Output
TOH
Output Hold from Address Change
0
ns
35
0
ns
ns
T19.0 562
TABLE 20: PROGRAM/ERASE CYCLE TIMING PARAMETERS (PP MODE), VDD=3.0-3.6V
Symbol
Parameter
Min
Max
Units
TRST
RST# High to Row Address Setup
1
µs
TAS
R/C# Address Setup Time
50
ns
TAH
R/C# Address Hold Time
50
ns
TCWH
R/C# to Write Enable High Time
50
ns
TOES
OE# High Setup Time
20
ns
TOEH
OE# High Hold Time
20
ns
TOEP
OE# to Data# Polling Delay
40
ns
TOET
OE# to Toggle Bit Delay
40
ns
TWP
WE# Pulse Width
100
ns
TWPH
WE# Pulse Width High
100
ns
TDS
Data Setup Time
50
ns
TDH
Data Hold Time
5
ns
TIDA
Software ID Access and Exit Time
150
ns
TBP
Byte Programming Time
20
µs
TSE
Sector-Erase Time
25
ms
TBE
Block-Erase Time
25
ms
TSCE
Chip-Erase Time
100
ms
T20.0 562
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
30
4 Mbit LPC Flash
SST49LF040
Advance Information
TABLE 21: RESET TIMING PARAMETERS (PP MODE), VDD=3.0-3.6V
Symbol
Parameter
Min
TPRST
VDD stable to Reset Low
TRSTP
RST# Pulse Width
TRSTF
RST# Low to Output Float
TRST1
RST# High to Row Address Setup
TRSTE
TRSTC
Max
Units
1
ms
100
ns
48
ns
RST# Low to reset during Sector-/Block-Erase or Program
10
µs
RST# Low to reset during Chip-Erase
50
µs
1
µs
T21.0 562
1. There will be a reset latency of TRSTE or TRSTC if a reset procedure is performed during a programming or erase operational.
VDD
TPRST
Addresses
Row Address
R/C#
TRSTP
RST#
Sector-/Block-Erase
or Program operation
aborted
TRSTE
TRSTC
TRSTF
TRST
Chip-Erase
aborted
DQ7-0
562 ILL F18.0
FIGURE 18: RESET TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
31
4 Mbit LPC Flash
SST49LF040
Advance Information
RST#
TRST
TRC
Row Address
Addresses
TAS
TAH
Column Address
Row Address
Column Address
TAH
TAS
R/C#
WE#
VIH
TAA
TOH
OE#
TOE
TOLZ
DQ7-0
TOHZ
High-Z
Data Valid
High-Z
562 ILL F19.0
FIGURE 19: READ CYCLE TIMING DIAGRAM (PP MODE)
TRST
RST#
Addresses
Row Address
TAS
Column Address
TAH
TAS
TAH
R/C#
TCWH
OE#
TOES
TWP
TOEH
TWPH
WE#
TDH
TDS
Data Valid
DQ7-0
562 ILL F20.0
FIGURE 20: WRITE CYCLE TIMING DIAGRAM (PP MODE)
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
32
4 Mbit LPC Flash
SST49LF040
Advance Information
Row
Addresses
Column
R/C#
WE#
OE#
TOEP
DQ7
D
D#
D#
D
562 ILL F21.0
FIGURE 21: DATA# POLLING TIMING DIAGRAM (PP MODE)
Addresses
Row
Column
R/C#
WE#
OE#
TOET
DQ6
D
D
562 ILL F22.0
FIGURE 22: TOGGLE BIT TIMING DIAGRAM (PP MODE)
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
33
4 Mbit LPC Flash
SST49LF040
Advance Information
Four-Byte Code for Byte-Program
Addresses
5555
2AAA
5555
BA
R/C#
OE#
TBP
TWP
WE#
TWPH
Internal Program Starts
AA
DQ7-0
55
A0
Data
562 ILL F23.0
BA = Byte-Program Address
FIGURE 23: BYTE-PROGRAM TIMING DIAGRAM (PP MODE)
Six-Byte code for Sector-Erase
Addresses
5555
2AAA
5555
5555
2AAA
SAx
R/C#
OE#
TWP
WE#
TSE
TWPH
Internal Erase Starts
AA
DQ7-0
55
80
AA
55
30
562 ILL F24.0
SAx = Sector Address
FIGURE 24: SECTOR-ERASE TIMING DIAGRAM (PP MODE)
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
34
4 Mbit LPC Flash
SST49LF040
Advance Information
Six-Byte code for Block-Erase
Addresses
5555
2AAA
5555
5555
2AAA
BAx
R/C#
OE#
TWP
WE#
TBE
TWPH
Internal Erase Starts
AA
DQ7-0
55
80
AA
55
50
562 ILL F25.0
BAx = Block Address
FIGURE 25: BLOCK-ERASE TIMING DIAGRAM (PP MODE)
Six-Byte code for Chip-Erase
Addresses
5555
2AAA
5555
5555
2AAA
5555
R/C#
OE#
TWP
WE#
TSCE
TWPH
Internal Erase Starts
DQ7-0
AA
55
80
AA
55
10
562 ILL F26.0
FIGURE 26: CHIP-ERASE TIMING DIAGRAM (PP MODE)
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
35
4 Mbit LPC Flash
SST49LF040
Advance Information
Three-byte sequence for
Software ID Entry
ADDRESS A14-0
5555
2AAA
5555
0000
0001
R/C#
OE#
TIDA
TWP
WE#
TAA
TWPH
DQ7-0
AA
55
BF
90
Device ID
562 ILL F27.0
Device ID = 51H for SST49LF040A and 5BH for SST49LF080A
FIGURE 27: SOFTWARE ID ENTRY
READ (PP MODE)
AND
Three-Byte Sequence for
Software ID Exit and Reset
ADDRESS A14-0
2AAA
5555
5555
TIDA
R/C#
OE#
TWP
WE#
T WHP
DQ7-0
AA
55
F0
562 ILL F28.0
FIGURE 28: SOFTWARE ID EXIT AND RESET (PP MODE)
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
36
4 Mbit LPC Flash
SST49LF040
Advance Information
VIHT
INPUT
VIT
REFERENCE POINTS
VOT
OUTPUT
VILT
562 ILL F29.0
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference
points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.
Note: VIT - VINPUT Test
VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
FIGURE 29: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TO TESTER
TO DUT
CL
562 ILL F30.0
FIGURE 30: A TEST LOAD EXAMPLE
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
37
4 Mbit LPC Flash
SST49LF040
Advance Information
Address: 5555H
Write Data: AAH
Cycle: 1
Address: 2AAAH
Write Data: 55H
Cycle: 2
Read
Command Sequence
Address: AIN
Read Data: DOUT
Cycle: 1
Address: 5555H
Write Data: A0H
Cycle: 3
Available for
Next Command
Address: AIN
Write Data: DIN
Cycle: 4
562 ILL F31.0
Wait TBP
Available for
Next Byte
562 ILL F32.0
FIGURE 32: BYTE-PROGRAM ALGORITHM
(LPC MODE)
FIGURE 31: READ COMMAND SEQUENCE
(LPC MODE)
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
38
4 Mbit LPC Flash
SST49LF040
Advance Information
Block-Erase
Command Sequence
Sector-Erase
Command Sequence
Address: 5555H
Write Data: AAH
Cycle: 1
Address: 5555H
Write Data: AAH
Cycle: 1
Address: 2AAAH
Write Data: 55H
Cycle: 2
Address: 2AAAH
Write Data: 55H
Cycle: 2
Address: 5555H
Write Data: 80H
Cycle: 3
Address: 5555H
Write Data: 80H
Cycle: 3
Address: 5555H
Write Data: AAH
Cycle: 4
Address: 5555H
Write Data: AAH
Cycle: 4
Address: 2AAAH
Write Data: 55H
Cycle: 5
Address: 2AAAH
Write Data: 55H
Cycle: 5
Address: BAX
Write Data: 50H
Cycle: 6
Address: SAX
Write Data: 30H
Cycle: 6
Wait TBE
Wait TSE
Block erased
to FFH
Sector erased
to FFH
Available for
Next Command
Available for
Next Command
562 ILL F33.0
FIGURE 33: ERASE COMMAND SEQUENCES (LPC MODE)
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
39
4 Mbit LPC Flash
SST49LF040
Advance Information
Software Product ID Entry
Command Sequence
Software Product ID Exit &
Reset Command Sequence
Address: 5555H
Write Data: AAH
Cycle: 1
Address: 5555H
Write Data: AAH
Cycle: 1
Address: XXXXH
Write Data: F0H
Cycle: 1
Address: 2AAAH
Write Data: 55H
Cycle: 2
Address: 2AAAH
Write Data: 55H
Cycle: 2
Wait TIDA
Address: 5555H
Write Data: 90H
Cycle: 3
Address: 5555H
Write Data: F0H
Cycle: 3
Available for
Next Command
Wait TIDA
Wait TIDA
Address: 0001H
Read Data: BFH
Cycle: 4
Available for
Next Command
Address: 0002H
Read Data:
Cycle: 5
Available for
Next Command
Note: X can be VIL or VIH, but no other value.
562 ILL F34.0
FIGURE 34: SOFTWARE PRODUCT COMMAND FLOWCHARTS (LPC MODE)
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
40
4 Mbit LPC Flash
SST49LF040
Advance Information
Start
Write data: AAH
Address: 5555H
Write data: 55H
Address: 2AAAH
Write data: A0H
Address: 5555H
Load Byte
Address/Byte
Data
Wait for end of
Program (TBP,
Data# Polling
bit, or Toggle bit
operation)
Program
Completed
562 ILL F35.0
FIGURE 35: BYTE-PROGRAM ALGORITHM (PP MODE)
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
41
4 Mbit LPC Flash
SST49LF040
Advance Information
Internal Timer
Toggle Bit
Data# Polling
ByteProgram/Erase
Initiated
ByteProgram/Erase
Initiated
ByteProgram/Erase
Initiated
Wait TBP,
TSCE, TBE,
or TSE
Read byte
Read DQ7
Read same
byte
Program/Erase
Completed
No
Is DQ7 =
true data?
Yes
No
Does DQ6
match?
Program/Erase
Completed
Yes
Program/Erase
Completed
562 ILL F36.0
FIGURE 36: WAIT OPTIONS (PP MODE)
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
42
4 Mbit LPC Flash
SST49LF040
Advance Information
Software Product ID Entry
Command Sequence
Software Product ID Exit &
Reset Command Sequence
Write data: AAH
Address: 5555H
Write data: AAH
Address: 5555H
Write data: F0H
Address: XXH
Write data: 55H
Address: 2AAAH
Write data: 55H
Address: 2AAAH
Wait TIDA
Write data: 90H
Address: 5555H
Write data: F0H
Address: 5555H
Return to normal
operation
Wait TIDA
Wait TIDA
Read Software ID
Return to normal
operation
562 ILL F37.0
FIGURE 37: SOFTWARE PRODUCT COMMAND FLOWCHARTS (PP MODE)
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4 Mbit LPC Flash
SST49LF040
Advance Information
Chip-Erase
Command Sequence
Block-Erase
Command Sequence
Sector-Erase
Command Sequence
Write data: AAH
Address: 5555H
Write data: AAH
Address: 5555H
Write data: AAH
Address: 5555H
Write data: 55H
Address: 2AAAH
Write data: 55H
Address: 2AAAH
Write data: 55H
Address: 2AAAH
Write data: 80H
Address: 5555H
Write data: 80H
Address: 5555H
Write data: 80H
Address: 5555H
Write data: AAH
Address: 5555H
Write data: AAH
Address: 5555H
Write data: AAH
Address: 5555H
Write data: 55H
Address: 2AAAH
Write data: 55H
Address: 2AAAH
Write data: 55H
Address: 2AAAH
Write data: 10H
Address: 5555H
Write data: 50H
Address: BAX
Write data: 30H
Address: SAX
Wait TSCE
Wait TBE
Wait TSE
Chip erased
to FFH
Block erased
to FFH
Sector erased
to FFH
562 ILL F38.0
FIGURE 38: ERASE COMMAND SEQUENCE (PP MODE)
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4 Mbit LPC Flash
SST49LF040
Advance Information
PRODUCT ORDERING INFORMATION
Device
SST49LF0x0
Speed
- XXX
Suffix1
-
XX
Suffix2
-
XX
Package Modifier
H = 32 pins
Package Type
N = PLCC
W = TSOP (type 1, die up, 8mm x 14mm)
Operating Temperature
C = Commercial = 0°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Serial Access Clock Frequency
33 = 33 MHz
Device Density
040 = 4 Mbit
Voltage Range
L = 3.0-3.6V
Device Family
Valid combinations for SST49LF040
SST49LF040-33-4C-WH
Note:
SST49LF040-33-4C-NH
Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
©2001 Silicon Storage Technology, Inc.
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4 Mbit LPC Flash
SST49LF040
Advance Information
PACKAGING DIAGRAMS
TOP VIEW
Optional
Pin #1 Identifier
SIDE VIEW
.495
.485
.453
.447
.048
.042
2
1
.112
.106
32
.020 R.
MAX.
.029
x 30˚
.023
.040
R.
.030
.042
.048
.595
.585
BOTTOM VIEW
.553
.547
.021
.013
.400
BSC
.032
.026
.530
.490
.050
BSC
.015 Min.
.095
.075
.050
BSC
.140
.125
.032
.026
Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in inches (max/min).
3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.
4. Coplanarity: 4 mils.
32-plcc-NH-ILL.2
32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC)
SST PACKAGE CODE: NH
©2001 Silicon Storage Technology, Inc.
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4 Mbit LPC Flash
SST49LF040
Advance Information
1.05
0.95
Pin # 1 Identifier
0.50
BSC
8.10
7.90
0.27
0.17
0.15
0.05
12.50
12.30
DETAIL
1.20
max.
0.70
0.50
14.20
13.80
0˚- 5˚
32-tsop-WH-ILL.6
Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions,
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
1mm
3. Coplanarity: 0.1 (±.05) mm.
4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM
SST PACKAGE CODE: WH
X
©2001 Silicon Storage Technology, Inc.
0.70
0.50
14MM
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4 Mbit LPC Flash
SST49LF040
Advance Information
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.ssti.com
©2001 Silicon Storage Technology, Inc.
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