ADS1278-HT www.ti.com SBAS447B – MARCH 2009 – REVISED MARCH 2010 OCTAL SIMULTANEOUS-SAMPLING 24-BIT ANALOG-TO-DIGITAL CONVERTER Check for Samples: ADS1278-HT FEATURES APPLICATIONS • • • • • • • • • 1 23 • • • • • • • • • SUPPORTS EXTREME TEMPERATURE APPLICATIONS • • • • • • • • (1) Down-Hole Drilling High Temperature Environments Vibration/Modal Analysis Multi-Channel Data Acquisition Acoustics/Dynamic Strain Gauges Pressure Sensors 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 • Simultaneously Measure Eight Channels Up to 128-kSPS Data Rate AC Performance: 62-kHz Bandwidth 111-dB SNR (High-Resolution Mode) –108-dB THD DC Accuracy: 0.8-mV/°C Offset Drift 1.3-ppm/°C Gain Drift Selectable Operating Modes: High-Speed: 128 kSPS, 106 dB SNR High-Resolution: 52 kSPS, 111 dB SNR Low-Power: 52 kSPS, 31 mW/ch Low-Speed: 10 kSPS, 7 mW/ch Linear Phase Digital Filter SPI™ or Frame-Sync Serial Interface Low Sampling Aperture Error Modulator Output Option (digital filter bypass) Analog Supply: 5 V Digital Core: 1.8 V I/O Supply: 1.8 V to 3.3 V Currently Available in an 84-Pin HFQ Package and a KGD Chiptray Option Controlled Baseline One Assembly/Test Site One Fabrication Site Available in Extreme (–55°C/210°C) Temperature Range (1) Extended Product Life Cycle Extended Product-Change Notification Product Traceability Texas Instruments High Temperature Products Utilize Highly Optimized Silicon (Die) Solutions With Dsign and Process Enhancements to Maximize Performance Over Extended Temperatures DESCRIPTION Based on the single-channel ADS1271, the ADS1278 (octal) is a 24-bit, delta-sigma (ΔΣ) analog-to-digital converter (ADC) with data rates up to 128 k samples per second (SPS), allowing simultaneous sampling of eight channels. Traditionally, industrial delta-sigma ADCs offering good drift performance use digital filters with large passband droop. As a result, they have limited signal bandwidth and are mostly suited for dc measurements. High-resolution ADCs in audio applications offer larger usable bandwidths, but the offset and drift specifications are significantly weaker than respective industrial counterparts. The ADS1278 combines these types of converters, allowing high-precision industrial measurement with excellent dc and ac specifications. The high-order, chopper-stabilized modulator achieves very low drift with low in-band noise. The onboard decimation filter suppresses modulator and signal out-of-band noise. These ADCs provide a usable signal bandwidth up to 90% of the Nyquist rate with less than 0.005 dB of ripple. Four operating modes allow for optimization of speed, resolution, and power. All operations are controlled directly by pins; there are no registers to program. The device is fully specified over the extended industrial range (–55°C to 210°C) and is available in an 84-pin HFQ package and a KGD chiptray option. Custom temperature ranges available 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI is a trademark of Motorola, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009–2010, Texas Instruments Incorporated ADS1278-HT SBAS447B – MARCH 2009 – REVISED MARCH 2010 www.ti.com VREFP VREFN AVDD DS Input2 DS Input3 DS Input4 DS Input5 DS Input6 DS Input7 DS Input8 DS IOVDD SPI and FrameSync Interface DRDY/FSYNC SCLK DOUT[8:1] DIN Control Logic TEST[1:0] FORMAT[2:0] CLK SYNC PWDN[8:1] CLKDIV MODE[1:0] Eight Digital Filters 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Input1 DVDD AGND DGND ADS1278 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Table 1. ORDERING INFORMATION (1) TA –55°C to 210°C (1) (2) 2 PACKAGE (2) ORDERABLE PART NUMBER HFQ ADS1278SHFQ CHIPTRAY (bare die) ADS1278SKGDA For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT ADS1278-HT www.ti.com SBAS447B – MARCH 2009 – REVISED MARCH 2010 PIN OUT 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 84 22 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 23 83 24 82 25 81 26 80 27 79 28 78 29 77 30 76 31 75 32 74 33 73 34 72 35 71 36 70 37 69 38 68 39 67 40 66 41 65 42 64 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT 3 ADS1278-HT SBAS447B – MARCH 2009 – REVISED MARCH 2010 www.ti.com BARE DIE INFORMATION DIE THICKNESS BACKSIDE FINISH BACKSIDE POTENTIAL BOND PAD METALLIZATION COMPOSITION 15 mils Silicon with backgrind GND AlCu Origin a c 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 b d Table 2. Bond Pad Coordinates in Microns - Rev A (1) (1) 4 DISCRIPTION PAD NUMBER a b c d Do not connect 1 5.00 4455.65 70.00 4520.65 AINP2 2 5.00 4355.65 70.00 4420.65 AINN2 3 5.00 4255.65 70.00 4320.65 Do not connect 4 5.00 4155.65 70.00 4220.65 Do not connect 5 5.00 4038.30 70.00 4103.30 AINP1 6 5.00 3938.30 70.00 4003.30 AINN1 7 5.00 3838.30 70.00 3903.30 Do not connect 8 5.00 3738.30 70.00 3803.30 AVDD 9 5.00 3373.30 70.00 3678.30 AGND 10 5.00 3033.30 70.00 3338.30 Do not connect 11 5.00 2853.30 70.00 2998.30 DGND 12 5.00 1911.65 70.00 1976.65 TEST0 13 5.00 1760.45 70.00 1825.45 Do not connect 14 5.00 1648.95 70.00 1713.95 TEST1 15 5.00 1536.60 70.00 1601.60 CLKDIV 16 5.00 1385.40 70.00 1450.40 SYNC 17 5.00 1234.20 70.00 1299.20 DIN 18 5.00 1083.00 70.00 1148.00 DOUT8 19 5.00 780.60 70.00 845.60 DOUT7 20 5.00 629.40 70.00 694.40 DOUT6 21 5.00 478.20 70.00 543.20 DOUT5 22 5.00 275.80 70.00 340.80 DOUT4 23 275.80 5.00 340.80 70.00 DOUT3 24 745.40 5.00 810.40 70.00 DOUT2 25 1099.30 5.00 1164.30 70.00 DOUT1 26 1250.50 5.00 1315.50 70.00 DGND 27 1525.25 5.00 1590.25 70.00 IOVDD 28 1691.00 5.00 1756.00 70.00 For singal descriptions see the Pin Descriptions table. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT ADS1278-HT www.ti.com SBAS447B – MARCH 2009 – REVISED MARCH 2010 Table 2. Bond Pad Coordinates in Microns - Rev A (1) (continued) DISCRIPTION PAD NUMBER a b c d IOVDD 29 1842.20 5.00 1907.20 70.00 IOVDD 30 2068.10 5.00 2133.10 70.00 IOVDD 31 2292.45 5.00 2597.45 70.00 DGND 32 2632.45 5.00 2697.45 70.00 DGND 33 2732.45 5.00 3277.45 70.00 DGND 34 3312.45 5.00 3457.45 70.00 DVDD 35 3492.45 5.00 3797.45 70.00 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 CLK 36 3869.40 5.00 3934.40 70.00 SCLK 37 4201.90 5.00 4266.90 70.00 DRDY/FSYNC 38 4423.90 5.00 4488.90 70.00 FORMAT2 39 4866.90 5.00 4931.90 70.00 FORMAT1 40 5199.40 5.00 5264.40 70.00 FORMAT0 41 5669.00 5.00 5734.00 70.00 MODE1 42 5939.80 275.80 6004.80 340.80 MODE0 43 5939.80 478.20 6004.80 543.20 PWDN8 44 5939.80 629.40 6004.80 694.40 PWDN7 45 5939.80 780.60 6004.80 845.60 PWDN6 46 5939.80 1083.00 6004.80 1148.00 PWDN5 47 5939.80 1234.20 6004.80 1299.20 PWDN4 48 5939.80 1385.40 6004.80 1450.40 PWDN3 49 5939.80 1536.60 6004.80 1601.60 Do not connect 50 5939.80 1648.95 6004.80 1713.95 PWDN2 51 5939.80 1760.45 6004.80 1825.45 PWDN1 52 5939.80 1911.65 6004.80 1976.65 Do not connect 53 5939.80 2853.30 6004.80 2998.30 AGND 54 5939.80 3033.30 6004.80 3338.30 AVDD 55 5939.80 3373.30 6004.80 3678.30 Do not connect 56 5939.80 3738.30 6004.80 3803.30 AINP8 57 5939.80 3838.30 6004.80 3903.30 AINN8 58 5939.80 3938.30 6004.80 4003.30 Do not connect 59 5939.80 4038.30 6004.80 4103.30 Do not connect 60 5939.80 4155.65 6004.80 4220.65 AINP7 61 5939.80 4255.65 6004.80 4320.65 AINN7 62 5939.80 4355.65 6004.80 4420.65 Do not connect 63 5939.80 4455.65 6004.80 4520.65 Do not connect 64 5664.20 4726.45 5729.20 4791.45 AINP6 65 5564.20 4726.45 5629.20 4791.45 AINN6 66 5464.20 4726.45 5529.20 4791.45 Do not connect 67 5364.20 4726.45 5429.20 4791.45 Do not connect 68 4925.95 4726.45 4990.95 4791.45 AINP5 69 4825.95 4726.45 4890.95 4791.45 AINN5 70 4725.95 4726.45 4790.95 4791.45 Do not connect 71 4625.95 4726.45 4690.95 4791.45 AVDD 72 4337.40 4726.45 4402.40 4791.45 AVDD 73 4077.40 4726.45 4302.40 4791.45 AGND 74 3817.40 4726.45 4042.40 4791.45 Do not connect 75 3717.40 4726.45 3782.40 4791.45 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT 5 ADS1278-HT SBAS447B – MARCH 2009 – REVISED MARCH 2010 www.ti.com Table 2. Bond Pad Coordinates in Microns - Rev A (1) (continued) DISCRIPTION PAD NUMBER a b c d VCOM 76 3617.40 4726.45 3682.40 4791.45 Do not connect 77 3517.40 4726.45 3582.40 4791.45 VCOM 78 3417.40 4726.45 3482.40 4791.45 Do not connect 79 3317.40 4726.45 3382.40 4791.45 VREFP 80 3022.40 4726.45 3247.40 4791.45 VREFN 81 2762.40 4726.45 2987.40 4791.45 AGND 82 2537.40 4726.45 2602.40 4791.45 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 6 AGND 83 2277.40 4726.45 2502.40 4791.45 AGND 84 1967.40 4726.45 2192.40 4791.45 AVDD 85 1707.40 4726.45 1932.40 4791.45 AVDD 86 1607.40 4726.45 1672.40 4791.45 Do not connect 87 1318.85 4726.45 1383.85 4791.45 AINP4 88 1218.85 4726.45 1283.85 4791.45 AINN4 89 1118.85 4726.45 1183.85 4791.45 Do not connect 90 1018.85 4726.45 1083.85 4791.45 Do not connect 91 580.60 4726.45 645.60 4791.45 AINP3 92 480.60 4726.45 545.60 4791.45 AINN3 93 380.60 4726.45 445.60 4791.45 Do not connect 94 280.60 4726.45 345.60 4791.45 Do not connect 95 5939.80 377.00 6004.80 442.00 Do not connect 96 5939.80 175.80 6004.80 240.80 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT ADS1278-HT - - SBAS447B – MARCH 2009 – REVISED MARCH 2010 - www.ti.com - 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 - - - - Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT 7 ADS1278-HT SBAS447B – MARCH 2009 – REVISED MARCH 2010 www.ti.com ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range, unless otherwise noted (1) UNIT AVDD to AGND –0.3 to 6.0 V DVDD, IOVDD to DGND –0.3 to 3.6 V AGND to DGND –0.3 to 0.3 V Momentary 100 mA Continuous 10 mA –0.3 to AVDD + 0.3 V Input current Analog input to AGND 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Digital input or output to DGND –0.3 to DVDD + 0.3 V Operating temperature range –55 to 210 °C Storage temperature range –60 to 150 °C (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. ELECTRICAL CHARACTERISTICS All specifications at TA = –55°C to 210°C, AVDD = 5 V, DVDD = 1.8 V, IOVDD = 3.3 V, fCLK = 27 MHz, VREFP = 2.5 V, VREFN = 0 V, and all channels active, unless otherwise noted. TA = 210°C (1) TA = –55°C to 125°C PARAMETER Analog Inputs Full-scale input voltage (FSR (2)) TEST CONDITIONS VIN = (AINP – AINN) Absolute input voltage AINP or AINN to AGND Common-mode input voltage (VCM) VCM = (AINP + AINN)/2 Differential input impedance MIN TYP MAX MIN AVDD + 0.1 AGND – 0.1 ±VREF AGND – 0.1 TYP MAX ±VREF UNIT V AVDD + 0.1 V 2.5 2.5 V High-Speed mode 14 14 kΩ High-Resolution mode 14 14 kΩ Low-Power mode 28 28 kΩ Low-Speed mode 140 140 kΩ fCLK = 32.768MHz (3) 128,000 128,000 SPS fCLK = 27MHz 105,469 105,469 SPS (4) High-Resolution mode 52,734 52,734 SPS Low-Power mode 52,734 52,734 SPS Low-Speed mode 10,547 10,547 SPS DC Performance Resolution No missing codes High-Speed mode Data rate (fDATA) Integral nonlinearity (INL) Offset error Offset drift Gain error Gain drift Noise (1) (2) (3) (4) (5) 8 (5) Differential input, VCM = 2.5V 24 Bits ±0.0003 ±0.0012 ±0.0014 0.25 2 2 0.8 0.1 0.5 % FSR (2) mV mV/°C 0.5 1.3 % FSR ppm/°C High-Speed mode Shorted input 8.5 21 21 mV, rms High-Resolution mode Shorted input 5.5 13 13 mV, rms Low-Power mode Shorted input 8.5 21 21 mV, rms Low-Speed mode Shorted input 8.0 21 21 mV, rms Minimum and maximum parameters are characterized for operation at TA = 210°C but may not be production tested at that temperature. Production test limits with statistical guardbands are used to ensure high temperature performance. FSR = full-scale range = 2VREF. fCLK = 32.768MHz max for High-Speed mode, and 27MHz max for all other modes. When fCLK > 27MHz, operation is limited to Frame-Sync mode and VREF ≤ 2.6V. SPS = samples per second. Best fit method. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT ADS1278-HT www.ti.com SBAS447B – MARCH 2009 – REVISED MARCH 2010 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = –55°C to 210°C, AVDD = 5 V, DVDD = 1.8 V, IOVDD = 3.3 V, fCLK = 27 MHz, VREFP = 2.5 V, VREFN = 0 V, and all channels active, unless otherwise noted. TA = 210°C (1) TA = –55°C to 125°C PARAMETER TEST CONDITIONS Common-mode rejection fCM = 60Hz MIN TYP 90 108 AVDD Power-supply rejection DVDD fPS = 60Hz IOVDD VCOM output voltage No load MAX MIN TYP MAX 90 UNIT dB 80 80 dB 85 85 dB 105 102 dB AVDD/2 AVDD/2 V 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 AC Performance Crosstalk f = 1kHz, –0.5dBFS (6) High-Speed mode Signal-to-noise ratio (SNR) (7) (unweighted) High-Resolution mode VREF = 2.5V –107 106 96 dB 101 110 101 dB VREF = 3V 111 Low-Power mode 98 106 97 Low-Speed mode 98 107 98 Total harmonic distortion (THD) (8) VIN = 1kHz, –0.5dBFS –108 Spurious-free dynamic range Passband ripple Passband –3dB Bandwidth Stop band attenuation Stop band Group delay Settling time (latency) High-Resolution mode dB 98 –96 dB dB dB -96 dB ±0.005 dB 0.453 fDATA Hz 0.49 fDATA Hz 95 All other modes dB 109 dB 100 High-Resolution mode 0.547 fDATA 127.453 fDATA Hz All other modes 0.547 fDATA 63.453 fDATA Hz High-Resolution mode 39/fDATA s All other modes 38/fDATA s High-Resolution mode Complete settling 78/fDATA s All other modes Complete settling 76/fDATA s Voltage Reference Inputs fCLK = 27MHz 0.5 2.5 3.1 0.5 2.5 3.1 V fCLK = 32.768MHz (9) 0.5 2.5 2.6 0.5 2.5 2.6 V Negative reference input (VREFN) AGND – 0.1 AGND + 0.1 AGND – 0.1 AGND + 0.1 V Positive reference input (VREFP) VREFN + 0.5 AVDD + 0.1 VREFN + 0.5 AVDD + 0.1 V Reference input voltage (VREF) (VREF = VREFP – VREFN) Reference Input impedance High-Speed mode 0.65 0.65 kΩ High-Resolution mode 0.65 0.65 kΩ Low-Power mode 1.3 1.3 kΩ Low-Speed mode 6.5 6.5 kΩ Digital Input/Output (IOVDD = 1.8V to 3.6V) VIH 0.7 IOVDD IOVDD 0.7 IOVDD IOVDD V VIL DGND 0.3 IOVDD DGND 0.3 IOVDD V 0.8 IOVDD IOVDD 0.8 IOVDD IOVDD V VOH (6) (7) (8) (9) IOH = 4mA Worst-case channel crosstalk between one or more channels. Minimum SNR is ensured by the limit of the DC noise specification. THD includes the first nine harmonics of the input signal; Low-Speed mode includes the first five harmonics. fCLK = 32.768MHz max for High-Speed mode, and 27MHz max for all other modes. When fCLK > 27MHz, operation is limited to Frame-Sync mode and VREF ≤ 2.6V. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT 9 ADS1278-HT SBAS447B – MARCH 2009 – REVISED MARCH 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = –55°C to 210°C, AVDD = 5 V, DVDD = 1.8 V, IOVDD = 3.3 V, fCLK = 27 MHz, VREFP = 2.5 V, VREFN = 0 V, and all channels active, unless otherwise noted. TA = 210°C (1) TA = –55°C to 125°C PARAMETER VOL TEST CONDITIONS DVDD IOVDD AVDD current DVDD current Power dissipation MAX UNIT 0.1 32.768 DGND 0.2 IOVDD V 0.1 32.768 MHz Other modes 0.1 27 0.1 27 MHz ±10 mA 4.75 5 5.25 4.75 5 5.25 1.65 1.8 1.95 1.65 1.8 1.95 V 3.6 1.65 3.6 V V AVDD 1 10 65 mA DVDD 1 50 200 mA IOVDD 1 11 25 High-Speed mode 97 145 135 185 mA High-Resolution mode 97 145 135 185 mA Low-Power mode 44 64 60 84 mA mA Low-Speed mode 9 14 12 22 mA High-Speed mode 23 30 24 31 mA High-Resolution mode 16 20 17 20 mA Low-Power mode 12 17 13 17 mA Low-Speed mode 2.5 4.5 3 5 mA High-Speed mode IOVDD current TYP High-Speed mode (9) 1.65 Power-down current MIN 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 AVDD MAX DGND 0 < VIN DIGITAL < IOVDD Master clock rate (fCLK) Power Supply TYP 0.2 IOVDD IOL = 4mA Input leakage MIN 0.25 1 0.3 1.15 mA High-Resolution mode 0.125 0.6 0.2 0.75 mA Low-Power mode 0.125 0.6 0.2 0.75 mA Low-Speed mode 0.035 0.3 0.1 0.45 mA High-Speed mode 530 785 985 mW High-Resolution mode 515 765 985 mW Low-Power mode 245 355 455 mW Low-Speed mode 50 80 120 mW PIN DESCRIPTIONS PIN NAME AGND AINP1 AINP2 AINP3 AINP4 AINP5 AINP6 10 FUNCTION Analog ground DESCRIPTION Analog ground; connect to DGND using a single plane. Analog input Analog input Analog input Analog input Analog input AINP[8:1] Positive analog input, channels 8 through 1. Analog input AINP7 Analog input AINP8 Analog input Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT ADS1278-HT www.ti.com SBAS447B – MARCH 2009 – REVISED MARCH 2010 PIN DESCRIPTIONS (continued) FUNCTION AINN1 Analog input AINN2 Analog input AINN3 Analog input AINN4 Analog input AINN5 Analog input AINN6 Analog input AINN7 Analog input AINN8 AVDD VCOM VREFN VREFP CLK CLKDIV DGND DIN DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 DOUT7 DOUT8 DRDY/ FSYNC DVDD FORMAT0 FORMAT1 FORMAT2 IOVDD MODE0 MODE1 PWDN1 PWDN2 PWDN3 PWDN4 PWDN5 PWDN6 PWDN7 DESCRIPTION AINN[8:1] Negative analog input, channels 8 through 1. 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 PIN NAME Analog input Analog power supply Analog output Analog power supply (4.75V to 5.25V). AVDD/2 Unbuffered voltage output. Analog input Negative reference input. Analog input Positive reference input. Digital input Master clock input. Digital input Digital ground Digital input Digital output CLK input divider control: 1 = 32.768MHz (High-Speed mode only) / 27MHz 0 = 13.5MHz (low-power) / 5.4MHz (low-speed) Digital ground power supply. Daisy-chain data input. DOUT1 is TDM data output (TDM mode). Digital output Digital output Digital output Digital output DOUT[8:1] Data output for channels 8 through 1. Digital output Digital output Digital output Digital input/output Digital power supply Frame-Sync protocol: frame clock input; SPI protocol: data ready output. Digital core power supply (+1.65V to +1.95V). Digital input Digital input FORMAT[2:0] Selects Frame-Sync/SPI protocol, TDM/discrete data outputs, fixed/dynamic position TDM data, and modulator mode/normal operating mode. Digital input Digital power supply Digital input Digital input I/O power supply (+1.65V to +3.6V). MODE[1:0] Selects High-Speed, High-Resolution, Low-Power, or Low-Speed mode operation. Digital input Digital input Digital input Digital input Digital input PWDN[8:1] Power-down control for channels 8 through 1. Digital input Digital input PWDN8 Digital input SCLK Digital input/output Serial clock input, Modulator clock output. SYNC Digital input Synchronize input (all channels). TEST0 Digital input TEST[1:0] Test mode select: TEST1 Digital input 00 = Normal operation 11 = Test mode 01 = Do not use 10 = Do not use Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT 11 ADS1278-HT SBAS447B – MARCH 2009 – REVISED MARCH 2010 www.ti.com TIMING CHARACTERISTICS: SPI FORMAT tCLK tCPW CLK · · · tCPW tCD tCONV DRDY tSD tDS tSCLK tSPW 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 SCLK tSPW tMSBPD DOUT Bit 23 (MSB) tDOPD tDOHD Bit 22 tDIST Bit 21 tDIHD DIN TIMING REQUIREMENTS: SPI FORMAT (1) For TA = –40°C to 105°C, IOVDD = 1.65 V to 3.6 V, and DVDD = 1.65 V to 1.95 V. SYMBOL tCPW (4) tDS (4) Falling edge of DRDY to rising edge of first SCLK to retrieve data tSCLK (5) tDOHD (4) (6) tDOPD (4) tDIST 12 (6) SCLK period UNIT ns ns 2560 22 tCLK ns 1 Falling edge of SCLK to rising edge of DRDY tSPW tDIHD 15 DRDY falling edge to DOUT MSB valid (propagation delay) (4) MAX 10,000 256 Falling edge of CLK to falling edge of DRDY tMSBPD TYP 37 Conversion period (1/fDATA) (3) tCD (1) (2) (3) (4) (5) (6) MIN CLK positive or negative pulse width tCONV tSD PARAMETER CLK period (1/fCLK) (2) tCLK tCLK 16 18 ns ns 1 tCLK SCLK positive or negative pulse width 0.4 tCLK SCLK falling edge to new DOUT invalid (hold time) 10 SCLK falling edge to new DOUT valid (propagation delay) ns 32 ns New DIN valid to falling edge of SCLK (setup time) 6 ns Old DIN valid to falling edge of SCLK (hold time) 6 ns Timing parameters are characerized or guranteed by design for specified temperature but not production tested. fCLK = 27MHz maximum. Depends on MODE[1:0] and CLKDIV selection. See Table 8 (fCLK/fDATA). Load on DRDY and DOUT = 20pF. For best performance, limit fSCLK/fCLK to ratios of 1, 1/2, 1/4, 1/8, etc. tDOHD (DOUT hold time) and tDIHD (DIN hold time) are specified under opposite worst-case conditions (digital supply voltage and ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is >4ns. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT ADS1278-HT www.ti.com SBAS447B – MARCH 2009 – REVISED MARCH 2010 TIMING CHARACTERISTICS: FRAME-SYNC FORMAT tCPW tCLK CLK tCPW tCS tFRAME tFPW tFPW FSYNC tFS tSCLK tSPW tSF 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 SCLK tSPW tMSBPD DOUT tDOHD Bit 23 (MSB) Bit 22 tDIST tDOPD Bit 21 tDIHD DIN TIMING REQUIREMENTS: FRAME-SYNC FORMAT (1) For TA = –40°C to 105°C, IOVDD = 1.65 V to 3.6 V, and DVDD = 1.65 V to 1.95 V. SYMBOL PARAMETER MIN All modes 37 TYP MAX UNIT 10,000 ns tCLK CLK period (1/fCLK) tCPW CLK positive or negative pulse width tCS Falling edge of CLK to falling edge of SCLK tFRAME Frame period (1/fDATA) (2) tFPW FSYNC positive or negative pulse width 1 tSCLK tFS Rising edge of FSYNC to rising edge of SCLK 5 ns tSF Rising edge of SCLK to rising edge of FSYNC 5 ns tSCLK SCLK period (3) 1 tCLK SCLK positive or negative pulse width 0.4 tCLK SCLK falling edge to old DOUT invalid (hold time) 10 ns tSPW tDOHD (4) tDOPD (5) (5) High-Speed mode only 30.5 ns 12 ns –0.25 0.25 256 2560 tCLK tCLK SCLK falling edge to new DOUT valid (propagation delay) 31 ns tMSBPD FSYNC rising edge to DOUT MSB valid (propagation delay) 31 ns tDIST New DIN valid to falling edge of SCLK (setup time) 6 ns Old DIN valid to falling edge of SCLK (hold time) 6 ns tDIHD (1) (2) (3) (4) (5) (4) Timing parameters are characerized or guranteed by design for specified temperature but not production tested. Depends on MODE[1:0] and CLKDIV selection. See Table 8 (fCLK/fDATA). SCLK must be continuously running and limited to ratios of 1, 1/2, 1/4, and 1/8 of fCLK. tDOHD (DOUT hold time) and tDIHD (DIN hold time) are specified under opposite worst-case conditions (digital supply voltage and ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is >4 ns. Load on DOUT = 20 pF. THERMAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS RqJA Junction-to-free air thermal resistance Board mounted, per JESD 51-5 methodology RqJC Junction-to-case thermal resistance MIL-STD-883 test method 1012 TYP UNIT 21.813 °C/W 0.849 °C/W Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT 13 ADS1278-HT SBAS447B – MARCH 2009 – REVISED MARCH 2010 www.ti.com ADS1278 Operating Life Derating Chart 1000000 100000 Hours in Estimated Life 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 10000 1000 100 10 1 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 Continuous TJ (°C) Figure 1. Notes: 1. See datasheet for absolute maximum and minimum recommended operating conditions. 2. Sillicon operating life design goal is 10 years at 110°C junction temperature. 14 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT ADS1278-HT www.ti.com SBAS447B – MARCH 2009 – REVISED MARCH 2010 TYPICAL CHARACTERISTICS At TA = 25°C, High-Speed mode, AVDD = 5 V, DVDD = 1.8 V, IOVDD = 3.3 V, fCLK = 27 MHz, VREFP = 2.5 V, and VREFN = 0 V, unless otherwise noted. OUTPUT SPECTRUM 0 OUTPUT SPECTRUM 0 High-Speed Mode fIN = 1kHz, -0.5dBFS 32,768 Points -20 -40 Amplitude (dB) -40 -60 -80 -100 -120 -60 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 -80 -100 -120 -140 -140 -160 -160 10 100 1k Frequency (Hz) 10k 100k 10 100 1k Frequency (Hz) Figure 2. OUTPUT SPECTRUM 0 -60 -80 -100 -120 -140 -160 Number of Occurrences High-Speed Mode Shorted Input 262,144 Points 20k 15k 10k 5k -20 35 High-Resolution Mode fIN = 1kHz, -20dBFS 32,768 Points -40 Amplitude (dB) Amplitude (dB) OUTPUT SPECTRUM 0 High-Resolution Mode fIN = 1kHz, -0.5dBFS 32,768 Points -40 28 Figure 5. OUTPUT SPECTRUM -20 21 Output (mV) Figure 4. 0 14 100k 7 10k 0 100 1k Frequency (Hz) -14 10 -21 1 -28 0 -180 -35 Amplitude (dB) -40 100k NOISE HISTOGRAM 25k High-Speed Mode Shorted Input 262,144 Points -20 10k Figure 3. -7 Amplitude (dB) High-Speed Mode fIN = 1kHz, -20dBFS 32,768 Points -20 -60 -80 -100 -60 -80 -100 -120 -120 -140 -140 -160 -160 10 100 1k Frequency (Hz) 10k 100k 10 Figure 6. 100 1k Frequency (Hz) 10k 100k Figure 7. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT 15 ADS1278-HT SBAS447B – MARCH 2009 – REVISED MARCH 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = 25°C, High-Speed mode, AVDD = 5 V, DVDD = 1.8 V, IOVDD = 3.3 V, fCLK = 27 MHz, VREFP = 2.5 V, and VREFN = 0 V, unless otherwise noted. OUTPUT SPECTRUM NOISE HISTOGRAM 25k Output (mV) Figure 8. Figure 9. OUTPUT SPECTRUM 0 Low-Power Mode fIN = 1kHz, -20dBFS 32,768 Points -20 -40 Amplitude (dB) -40 Amplitude (dB) OUTPUT SPECTRUM 0 Low-Power Mode fIN = 1kHz, -0.5dBFS 32,768 Points -20 -60 -80 -100 -120 -60 -80 -100 -120 -140 -140 -160 -160 10 100 1k Frequency (Hz) 10k 100k 10 100 1k Frequency (Hz) Figure 10. Number of Occurrences -40 -60 -80 -100 -120 100k NOISE HISTOGRAM 25k Low-Power Mode Shorted Input 262,144 Points -20 10k Figure 11. OUTPUT SPECTRUM 0 Amplitude (dB) 24.5 100k 17.5 10k 3.5 100 1k Frequency (Hz) 7.0 10 0 1 -7.0 0 -180 -3.5 5k -10.5 -160 -14.0 -140 10k -17.5 -120 -21.0 -100 15k 21.0 -80 14.0 -60 20k 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Amplitude (dB) -40 High-Resolution Mode Shorted Input 262,144 Points 10.5 Number of Occurrences High-Resolution Mode Shorted Input 262,144 Points -20 -24.5 0 -140 20k Low-Power Mode Shorted Input 262,144 Points 15k 10k 5k 37 32 21 26 16 5 11 0 Output (mV) Figure 12. 16 -5 100k -11 10k -21 100 1k Frequency (Hz) -26 10 -32 1 -37 0 -180 -16 -160 Figure 13. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT ADS1278-HT www.ti.com SBAS447B – MARCH 2009 – REVISED MARCH 2010 TYPICAL CHARACTERISTICS (continued) At TA = 25°C, High-Speed mode, AVDD = 5 V, DVDD = 1.8 V, IOVDD = 3.3 V, fCLK = 27 MHz, VREFP = 2.5 V, and VREFN = 0 V, unless otherwise noted. OUTPUT SPECTRUM 0 OUTPUT SPECTRUM 0 Low-Speed Mode fIN = 100Hz, -0.5dBFS 32,768 Points -20 -40 Amplitude (dB) -40 -60 -80 -100 -120 -60 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 -80 -100 -120 -140 -140 -160 -160 1 10 100 Frequency (Hz) 1k 10k 1 10 100 Frequency (Hz) Figure 14. OUTPUT SPECTRUM 0 -80 -100 -120 -140 -160 THD, THD+N (dB) 15k 10k 5k -60 35 28 21 14 7 Output (mV) Figure 16. Figure 17. TOTAL HARMONIC DISTORTION vs FREQUENCY TOTAL HARMONIC DISTORTION vs INPUT AMPLITUDE 0 High-Speed Mode VIN = -0.5dBFS -40 0 10k -14 1k -21 10 100 Frequency (Hz) -28 1 -35 0.1 -20 20k Low-Speed Mode Shorted Input 262,144 Points 0 -180 0 Number of Occurrences -60 -20 THD, THD+N (dB) Amplitude (dB) -40 10k NOISE HISTOGRAM 25k Low-Speed Mode Shorted Input 262,144 Points -20 1k Figure 15. -7 Amplitude (dB) Low-Speed Mode fIN = 100Hz, -20dBFS 32,768 Points -20 -80 THD+N -100 High-Speed Mode fIN = 1kHz -40 -60 -80 THD+N -100 THD -120 -120 THD -140 10 100 1k Frequency (Hz) 10k 100k -140 -120 Figure 18. -100 -80 -60 -40 Input Amplitude (dBFS) -20 0 Figure 19. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT 17 ADS1278-HT SBAS447B – MARCH 2009 – REVISED MARCH 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = 25°C, High-Speed mode, AVDD = 5 V, DVDD = 1.8 V, IOVDD = 3.3 V, fCLK = 27 MHz, VREFP = 2.5 V, and VREFN = 0 V, unless otherwise noted. TOTAL HARMONIC DISTORTION vs FREQUENCY -40 -60 -80 THD+N -100 THD -120 -140 10 -20 100 1k Frequency (Hz) 10k -60 -80 -60 -80 -100 THD+N -120 THD -100 TOTAL HARMONIC DISTORTION vs FREQUENCY TOTAL HARMONIC DISTORTION vs INPUT AMPLITUDE 0 -20 10 100 1k Frequency (Hz) 0 -20 0 -40 -60 -80 THD+N THD THD -140 -20 Low-Power Mode fIN = 1kHz -100 -120 -120 10k 100k -140 -120 Figure 22. 18 -80 -60 -40 Input Amplitude (dBFS) Figure 21. THD+N -100 -40 Figure 20. Low-Power Mode VIN = -0.5dBFS -40 High-Resolution Mode fIN = 1kHz -140 -120 100k THD, THD+N (dB) 0 THD, THD+N (dB) -20 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 THD, THD+N (dB) -20 0 High-Resolution Mode VIN = -0.5dBFS THD, THD+N (dB) 0 TOTAL HARMONIC DISTORTION vs INPUT AMPLITUDE -100 -80 -60 -40 Input Amplitude (dBFS) Figure 23. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT ADS1278-HT www.ti.com SBAS447B – MARCH 2009 – REVISED MARCH 2010 TYPICAL CHARACTERISTICS (continued) At TA = 25°C, High-Speed mode, AVDD = 5 V, DVDD = 1.8 V, IOVDD = 3.3 V, fCLK = 27 MHz, VREFP = 2.5 V, and VREFN = 0 V, unless otherwise noted. TOTAL HARMONIC DISTORTION vs FREQUENCY 0 0 Low-Speed Mode VIN = -0.5dBFS -40 -80 THD+N -100 -40 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 -60 Low-Speed Mode -20 THD, THD+N (dB) -20 THD, THD+N (dB) TOTAL HARMONIC DISTORTION vs INPUT AMPLITUDE -60 -80 THD+N -100 THD -120 THD -120 -140 10 100 1k -140 -120 10k -100 Frequency (Hz) Figure 24. 250 200 150 100 50 700 600 500 400 300 200 100 Outliers: T < -20°C -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 0 25 units based on 20°C intervals over the range -40°C to +105°C. 800 Number of Occurrences Number of Occurrences 300 Offset Drift (mV/°C) Gain Drift (ppm/°C) Figure 26. Figure 27. OFFSET WARMUP DRIFT RESPONSE BAND 40 GAIN WARMUP DRIFT RESPONSE BAND 40 ADS1274/78 High-Speed and High-Resolution Modes Normalized Gain Error (ppm) ADS1278 High-Speed and High-Resolution Modes 30 Normalized Offset (mV) 0 GAIN DRIFT HISTOGRAM 900 Multi-lot data based on 20°C intervals over the range -40°C to +105°C. 350 -20 Figure 25. OFFSET DRIFT HISTOGRAM 400 -80 -60 -40 Input Amplitude (dBFS) ADS1278 Low-Power Mode 20 10 0 -10 -20 ADS1278 Low-Speed Mode -30 30 ADS1278 Low-Power Mode 20 10 0 -10 -20 ADS1278 Low-Speed Mode -30 ADS1274 High-Speed and High-Resolution Modes -40 -40 0 50 100 150 200 250 Time (s) 300 350 400 0 50 Figure 28. 100 150 200 250 Time (s) 300 350 400 Figure 29. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT 19 ADS1278-HT SBAS447B – MARCH 2009 – REVISED MARCH 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = 25°C, High-Speed mode, AVDD = 5 V, DVDD = 1.8 V, IOVDD = 3.3 V, fCLK = 27 MHz, VREFP = 2.5 V, and VREFN = 0 V, unless otherwise noted. OFFSET ERROR HISTOGRAM High-Speed Mode 25 Units 80 30 25 10 5 0 70 60 50 40 30 20 10 0 Offset (mV) -4000 -3600 -3200 -2800 -2400 -2000 -1600 -1200 -800 -400 0 400 800 1200 1600 2000 2400 2800 3200 3600 4000 15 -1000 -900 -800 -700 -600 -500 -400 -300 -200 -100 0 100 200 300 400 500 600 700 800 900 1000 20 High-Speed Mode 25 Units 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Number of Occurrences 35 GAIN ERROR HISTOGRAM 90 Number of Occurrences 40 Gain Error (ppm) Figure 30. Figure 31. CHANNEL GAIN MATCH HISTOGRAM 70 60 50 40 30 20 10 0 60 High-Speed Mode 10 Units 50 40 30 20 10 Channel Gain Match (ppm) 0 - 1500 - 1400 - 1300 - 1200 - 1100 - 1000 - 900 - 800 - 700 - 600 - 500 - 400 - 300 - 200 - 100 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 80 High-Speed Mode 10 Units Number of Occurrences Number of Occurrences 90 CHANNEL OFFSET MATCH HISTOGRAM 70 -1500 -1400 -1300 -1200 -1100 -1000 -900 -800 -700 -600 -500 -400 -300 -200 -100 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 100 Figure 32. 20 Channel Offset Match (mV) Figure 33. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT ADS1278-HT www.ti.com SBAS447B – MARCH 2009 – REVISED MARCH 2010 TYPICAL CHARACTERISTICS (continued) At TA = 25°C, High-Speed mode, AVDD = 5 V, DVDD = 1.8 V, IOVDD = 3.3 V, fCLK = 27 MHz, VREFP = 2.5 V, and VREFN = 0 V, unless otherwise noted. OFFSET AND GAIN vs TEMPERATURE 50 250 18 0 200 150 -50 Gain -100 100 50 -150 0 -200 -250 Number of Occurrences Offset Normalized Gain Error (ppm) 20 -50 16 14 0 -20 20 40 60 Temperature (°C) 80 100 12 10 8 6 4 2 -100 120 125 0 2.40 2.41 2.42 2.43 2.44 2.45 2.46 2.47 2.48 2.49 2.50 2.51 2.52 2.53 2.54 2.55 2.56 2.57 2.58 2.59 2.60 -300 -40 AVDD = 5V 25 Units, No Load 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Normalized Offset (mV) VCOM VOLTAGE OUTPUT HISTOGRAM 300 100 700 650 550 600 500 400 0 450 Reference Input Impedance (kW) 5 300 10 350 15 200 20 250 25 30 units over 3 production lots, inter-channel combinations. 150 30 SAMPLING MATCH ERROR HISTOGRAM REFERENCE INPUT DIFFERENTIAL IMPEDANCE vs TEMPERATURE 50 Number of Occurrences 35 Figure 35. 100 40 Figure 34. 0.68 6.8 0.67 6.7 0.66 6.6 0.65 0.64 High-Speed and High-Resolution Modes 6.5 Low-Speed Mode 0.63 0.62 -40 -20 Sampling Match Error (ps) Figure 36. 0 20 40 60 Temperature (°C) 80 6.4 6.3 100 Reference Input Impedance (kW) VCOM Voltage Output (V) 6.2 120 125 Figure 37. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT 21 ADS1278-HT SBAS447B – MARCH 2009 – REVISED MARCH 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = 25°C, High-Speed mode, AVDD = 5 V, DVDD = 1.8 V, IOVDD = 3.3 V, fCLK = 27 MHz, VREFP = 2.5 V, and VREFN = 0 V, unless otherwise noted. ANALOG INPUT DIFFERENTIAL IMPEDANCE vs TEMPERATURE 155 28.6 150 14.2 28.4 14.1 28.2 14.0 28.0 13.9 27.8 High-Speed and High-Resolution Modes 13.8 13.7 27.6 27.4 13.6 27.2 Low-Power Mode 13.5 13.4 -40 10 Analog Input Impedance (kW) 28.8 14.3 Analog Input Impedance (kW) 14.4 Low-Speed Mode 145 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Analog Input Impedance (kW) ANALOG INPUT DIFFERENTIAL IMPEDANCE vs TEMPERATURE -20 0 20 40 60 Temperature (°C) 80 100 27.0 26.8 120 125 140 135 130 125 120 115 -40 -20 0 20 40 60 Temperature (°C) Figure 38. Figure 39. INTEGRAL NONLINEARITY vs TEMPERATURE LINEARITY ERROR vs INPUT LEVEL 80 100 120 125 10 8 6 4 2 6 Linearity Error (ppm) INL (ppm of FSR) 8 4 2 0 -2 -4 -6 T = -40°C T = +125°C -8 0 -40 -20 0 20 40 60 Temperature (°C) 80 100 120 125 -10 -2.5 -2.0 -1.5 -1.0 -0.5 Figure 40. 22 T = +105°C T = +25°C 0 0.5 VIN (V) 1.0 1.5 2.0 2.5 Figure 41. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT ADS1278-HT www.ti.com SBAS447B – MARCH 2009 – REVISED MARCH 2010 TYPICAL CHARACTERISTICS (continued) At TA = 25°C, High-Speed mode, AVDD = 5 V, DVDD = 1.8 V, IOVDD = 3.3 V, fCLK = 27 MHz, VREFP = 2.5 V, and VREFN = 0 V, unless otherwise noted. 14 14 12 -104 12 12 10 -108 10 -112 6 -116 4 Linearity 2 0 0.5 12 1.0 1.5 2.0 VREF (V) 2.5 3.0 8 4 -124 2 2 -128 0 -0.5 0 3.5 4 Figure 43. NOISE vs TEMPERATURE NOISE vs REFERENCE VOLTAGE 12 Low-Power 10 High-Speed High-Speed Mode 8 Low-Speed 6 4 High-Resolution High-Resolution Mode 2 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Input Common-Mode Voltage (V) Figure 42. Low-Speed Mode 6 6 Linearity 4 Noise (mV) RMS Noise (mV) 8 8 6 Low-Power Mode 10 10 Noise -120 See Electrical Characteristics for VREF Operating Range. 0 THD (dB) THD 8 RMS Noise (mV) -100 THD: fIN = 1kHz, VIN = -0.5dBFS 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Linearity (ppm) 14 NOISE AND LINEARITY vs INPUT COMMON-MODE VOLTAGE INL (ppm of FSR) LINEARITY AND TOTAL HARMONIC DISTORTION vs REFERENCE VOLTAGE 2 See Electrical Characteristics for VREF Operating Range. 0 0 -40 -20 0 20 40 60 Temperature (°C) 80 100 120 125 0 0.5 Figure 44. 1.0 1.5 2.0 VREF (V) 2.5 3.0 3.5 Figure 45. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT 23 ADS1278-HT SBAS447B – MARCH 2009 – REVISED MARCH 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = 25°C, High-Speed mode, AVDD = 5 V, DVDD = 1.8 V, IOVDD = 3.3 V, fCLK = 27 MHz, VREFP = 2.5 V, and VREFN = 0 V, unless otherwise noted. TOTAL HARMONIC DISTORTION AND NOISE vs CLK -20 10 8 -60 Noise 6 -80 THD 4 -100 2 -120 -140 10k 100k 1M CLK (Hz) 0 100M 10M -40 -60 -80 -100 -120 10 100 Figure 47. POWER-SUPPLY REJECTION vs POWER-SUPPLY FREQUENCY AVDD CURRENT vs TEMPERATURE 100k 1M 100 120 125 140 120 -20 -40 -60 AVDD -80 100 High-Speed and High-Resolution Modes 80 60 Low-Power Mode 40 DVDD 20 -100 IOVDD -120 10 100 1k 10k 100k Power-Supply Modulation Frequency (Hz) 1M 0 -40 Low-Speed Mode -20 Figure 48. 24 1k 10k Input Frequency (Hz) Figure 46. AVDD Current (mA) Power-Supply Rejection (dB) 0 -20 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 THD (dB) 12 Noise RMS (mV) -40 0 14 High-Speed Mode fCLK > 32.768MHz: VREF = 2.048V, DVDD = 2.1V THD: AIN = fCLK/5120, -0.5dBFS Noise: Shorted Input Common-Mode Rejection (dB) 0 COMMON-MODE REJECTION vs INPUT FREQUENCY 0 20 40 60 Temperature (°C) 80 Figure 49. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT ADS1278-HT www.ti.com SBAS447B – MARCH 2009 – REVISED MARCH 2010 TYPICAL CHARACTERISTICS (continued) At TA = 25°C, High-Speed mode, AVDD = 5 V, DVDD = 1.8 V, IOVDD = 3.3 V, fCLK = 27 MHz, VREFP = 2.5 V, and VREFN = 0 V, unless otherwise noted. DVDD CURRENT vs TEMPERATURE IOVDD CURRENT vs TEMPERATURE 30 0.4 IOVDD Current (mA) 20 High-Speed Mode 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 DVDD Current (mA) 25 0.5 High-Resolution Mode 15 10 5 0 -40 Low-Power Mode 0.3 High-Speed Mode 0.2 Low-Power Mode 0.1 Low-Speed Mode -20 0 High-Resolution Mode 20 40 60 Temperature (°C) 80 100 120 125 0 -40 0 -20 Figure 50. Low-Speed Mode 20 40 60 Temperature (°C) 80 100 120 125 Figure 51. POWER DISSIPATION vs TEMPERATURE 800 Power Dissipation (mW) 700 600 High-Speed Mode 500 400 300 High-Resolution Mode Low-Power Mode 200 100 Low-Speed Mode 0 -40 -20 0 20 40 60 Temperature (°C) 80 100 120 125 Figure 52. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT 25 ADS1278-HT SBAS447B – MARCH 2009 – REVISED MARCH 2010 www.ti.com OVERVIEW High-Speed, High-Resolution, Low-Power, and Low-Speed. Table 3 summarizes the performance of each mode. The ADS1278 is an octal 24-bit, delta-sigma ADC based on the single-channel ADS1271. It offers the combination of outstanding dc accuracy and superior ac performance. Figure 53 shows the block diagram. The converter is comprised of eight advanced, 6th-order, chopper-stabilized, delta-sigma modulators followed by low-ripple, linear phase FIR filters. The modulators measure the differential input signal, VIN = (AINP – AINN), against the differential reference, VREF = (VREFP – VREFN). The digital filters receive the modulator signal and provide a low-noise digital output. To allow tradeoffs among speed, resolution, and power, four operating modes are supported: 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 In High-Speed mode, the maximum data rate is 128 kSPS (when operating at 128 kSPS, Frame-Sync format must be used). In High-Resolution mode, the SNR = 111dB (VREF = 3.0 V); in Low-Power mode, the power dissipation is 31 mW/channel; and in Low-Speed mode, the power dissipation is only 7 mW/channel at 10.5 kSPS. The digital filters can be bypassed, enabling direct access to the modulator output. VREFP AVDD DVDD VREFN IOVDD Mod 1 Mod 2 S R The ADS1278 is configured by simply setting the appropriate I/O pins—there are no registers to program. Data are retrieved over a serial interface that supports both SPI and Frame-Sync formats. The ADS1278 has a daisy-chainable output and the ability to synchronize externally, so it can be used conveniently in systems requiring more than eight channels. Modulator Output VCOM VREF R AINP1 S VIN1 AINN1 AINP2 S VIN2 AINN2 Mod 8 DS Modulator1 Digital Filter1 DS Modulator2 DRDY/FSYNC SPI and Frame-Sync Interface SCLK DOUT [8:1] DIN Digital Filter2 TEST[1:0] FORMAT[2:0] CLK Control Logic AINP8 AINN8 S VIN4/8 DS Modulator8 SYNC PWDN [8:1] Digital Filter8 CLKDIV MODE[1:0] AGND DGND Figure 53. Block Diagram Table 3. Operating Mode Performance Summary 26 MODE MAX DATA RATE (SPS) PASSBAND (kHz) SNR (dB) NOISE (mVRMS) POWER/CHANNEL (mW) High-Speed 128,000 57,984 106 8.5 70 High-Resolution 52,734 23,889 110 5.5 64 Low-Power 52,734 23,889 106 8.5 31 Low-Speed 10,547 4,798 107 8.0 7 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT ADS1278-HT www.ti.com SBAS447B – MARCH 2009 – REVISED MARCH 2010 FUNCTIONAL DESCRIPTION SAMPLING APERTURE MATCHING The ADS1278 is a delta-sigma ADC consisting of eight independent converters that digitize eight input signals in parallel. The ADS1278 converter operates from the same CLK input. The CLK input controls the timing of the modulator sampling instant. The converter is designed such that the sampling skew, or modulator sampling aperture match between channels, is controlled. Furthermore, the digital filters are synchronized to start the convolution phase at the same modulator clock cycle. This design results in excellent phase match among the ADS1278 channels. 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 The converter is composed of two main functional blocks to perform the ADC conversions: the modulator and the digital filter. The modulator samples the input signal together with sampling the reference voltage to produce a 1s density output stream. The density of the output stream is proportional to the analog input level relative to the reference voltage. The pulse stream is filtered by the internal digital filter where the output conversion result is produced. In operation, the input signal is sampled by the modulator at a high rate (typically 64x higher than the final output data rate). The quantization noise of the modulator is moved to a higher frequency range where the internal digital filter removes it. Oversampling results in very low levels of noise within the signal passband. Since the input signal is sampled at a very high rate, input signal aliasing does not occur until the input signal frequency is at the modulator sampling rate. This architecture greatly relaxes the requirement of external antialiasing filters because of the high modulator sampling rate. Figure 36 shows the inter-device channel sample matching for the ADS1278. FREQUENCY RESPONSE The digital filter sets the overall frequency response. The filter uses a multi-stage FIR topology to provide linear phase with minimal passband ripple and high stop band attenuation. The filter coefficients are identical to the coefficients used in the ADS1271. The oversampling ratio of the digital filter (that is, the ratio of the modulator sampling to the output data rate, or fMOD/fDATA) is a function of the selected mode, as shown in Table 4. Table 4. Oversampling Ratio versus Mode MODE SELECTION OVERSAMPLING RATIO (fMOD/fDATA) High-Speed 64 High-Resolution 128 Low-Power 64 Low-Speed 64 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT 27 ADS1278-HT SBAS447B – MARCH 2009 – REVISED MARCH 2010 www.ti.com High-Speed, Low-Power, and Low-Speed Modes Amplitude (dB) -2 -3 -4 -5 -6 -7 -8 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 The digital filter configuration is the same in High-Speed, Low-Power, and Low-Speed modes with the oversampling ratio set to 64. Figure 54 shows the frequency response in High-Speed, Low-Power, and Low-Speed modes normalized to fDATA. Figure 55 shows the passband ripple. The transition from passband to stop band is shown in Figure 56. The overall frequency response repeats at 64x multiples of the modulator frequency fMOD, as shown in Figure 57. 0 -1 -9 -10 0.45 0 0.47 0.49 0.51 0.53 0.55 Normalized Input Frequency (fIN/fDATA) Amplitude (dB) -20 Figure 56. Transition Band Response for High-Speed, Low-Power, and Low-Speed Modes -40 -60 -80 20 0 -100 -20 -120 0 0.2 0.6 0.4 0.8 1.0 Normalized Input Frequency (fIN/fDATA) Figure 54. Frequency Response for High-Speed, Low-Power, and Low-Speed Modes Gain (dB) -40 -140 -60 -80 -100 -120 -140 -160 0.02 0 16 32 48 64 Input Frequency (fIN/fDATA) Amplitude (dB) 0 Figure 57. Frequency Response Out to fMOD for High-Speed, Low-Power, and Low-Speed Modes -0.02 -0.04 -0.06 -0.08 -0.10 0 0.1 0.2 0.3 0.4 0.5 0.6 Normalized Input Frequency (fIN/fDATA) Figure 55. Passband Response for High-Speed, Low-Power, and Low-Speed Modes 28 These image frequencies, if present in the signal and not externally filtered, will fold back (or alias) into the passband, causing errors. The stop band of the ADS1278 provides 100 dB attenuation of frequencies that begin just beyond the passband and continue out to fMOD. Placing an antialiasing, low-pass filter in front of the ADS1278 inputs is recommended to limit possible high-amplitude, out-of-band signals and noise. Often, a simple RC filter is sufficient. Table 5 lists the image rejection versus external filter order. Table 5. Antialiasing Filter Order Image Rejection IMAGE REJECTION (dB) (f–3dB at fDATA) ANTIALIASING FILTER ORDER HS, LP, LS HR 1 39 45 2 75 87 3 111 129 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT ADS1278-HT www.ti.com SBAS447B – MARCH 2009 – REVISED MARCH 2010 High-Resolution Mode 0 0 Amplitude (dB) -3 -4 -5 -6 -7 -8 -9 -10 0.45 0.47 0.49 0.51 0.53 0.55 Normalized Input Frequency (fIN/fDATA) Figure 60. Transition Band Response for High-Resolution mode 20 0 -40 -20 -60 -40 -80 Gain (dB) Amplitude (dB) -20 -2 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 The oversampling ratio is 128 in High-Resolution mode. Figure 58 shows the frequency response in High-Resolution mode normalized to fDATA. Figure 59 shows the passband ripple, and the transition from passband to stop band is shown in Figure 60. The overall frequency response repeats at multiples of the modulator frequency fMOD (128 × fDATA), as shown in Figure 61. The stop band of the ADS1278 provides 100 dB attenuation of frequencies that begin just beyond the passband and continue out to fMOD. Placing an antialiasing, low-pass filter in front of the ADS1278 inputs is recommended to limit possible high-amplitude out-of-band signals and noise. Often, a simple RC filter is sufficient. Table 5 lists the image rejection versus external filter order. -1 -100 -120 -60 -80 -100 -120 -140 0 0.50 0.25 0.75 1 Normalized Input Frequency (fIN/fDATA) -140 -160 0 Figure 58. Frequency Response for High-Resolution Mode 32 64 96 128 Normalized Input Frequency (fIN/fDATA) Figure 61. Frequency Response Out to fMOD for High-Resolution Mode 0.02 Amplitude (dB) 0 -0.02 -0.04 -0.06 -0.08 -0.10 0 0.1 0.2 0.3 0.4 0.5 0.6 Normalized Input Frequency (fIN/fDATA) Figure 59. Passband Response for High-Resolution Mode Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT 29 ADS1278-HT SBAS447B – MARCH 2009 – REVISED MARCH 2010 www.ti.com Table 6. Ideal Output Code versus Input Signal PHASE RESPONSE The ADS1278 incorporates a multiple stage, linear phase digital filter. Linear phase filters exhibit constant delay time versus input frequency (constant group delay). This characteristic means the time delay from any instant of the input signal to the same instant of the output data is constant and is independent of input signal frequency. This behavior results in essentially zero phase errors when analyzing multi-tone signals. Settling (%) 000001h 0 000000h * VREF 2 23 * 1 FFFFFFh Fully Settled Data at 76 Conversions (78 Conversions for High-Resolution mode) 10 20 30 40 50 60 70 23 23 800000h (1) Excludes effects of noise, INL, offset, and gain errors. ANALOG INPUTS (AINP, AINN) The ADS1278 measures each differential input signal VIN = (AINP – AINN) against the common differential reference VREF = (VREFP – VREFN). The most positive measurable differential input is +VREF, which produces the most positive digital output code of 7FFFFFh. Likewise, the most negative measurable differential input is –VREF, which produces the most negative digital output code of 800000h. For optimum performance, the inputs of the ADS1278 are intended to be driven differentially. For single-ended applications, one of the inputs (AINP or AINN) can be driven while the other input is fixed (typically to AGND or 2.5 V). Fixing the input to 2.5 V permits bipolar operation, thereby allowing full use of the entire converter range. Initial Value 80 Conversions (1/fDATA) Figure 62. Step Response While the ADS1278 measures the differential input signal, the absolute input voltage is also important. This value is the voltage on either input (AINP or AINN) with respect to AGND. The range for this voltage is: –0.1 V < (AINN or AINP) < AVDD + 0.1 V DATA FORMAT The ADS1278 outputs 24 bits of data in twos complement format. A positive full-scale input produces an ideal output code of 7FFFFFh, and the negative full-scale input produces an ideal output code of 800000h. The output clips at these codes for signals exceeding full-scale. Table 6 summarizes the ideal output codes for different input signals. 30 7FFFFFh 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Final Value 0 ≥ +VREF ) VREF 2 23 * 1 ǒ2 2* 1Ǔ As with frequency and phase response, the digital filter also determines settling time. Figure 62 shows the output settling behavior after a step change on the analog inputs normalized to conversion periods. The X-axis is given in units of conversion. Note that after the step change on the input occurs, the output data change very little prior to 30 conversion periods. The output data are fully settled after 76 conversion periods for High-Speed and Low-Power modes, and 78 conversion periods for High-Resolution mode. 0 IDEAL OUTPUT CODE(1) v −VREF SETTLING TIME 100 INPUT SIGNAL VIN (AINP – AINN) If either input is taken below –0.4 V or above (AVDD + 0.4 V), ESD protection diodes on the inputs may turn on. If these conditions are possible, external Schottky clamp diodes or series resistors may be required to limit the input current to safe values (see the Absolute Maximum Ratings table). The ADS1278 is a very high-performance ADC. For optimum performance, it is critical that the appropriate circuitry be used to drive the ADS1278 inputs. See the Application Information section for several recommended circuits. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT ADS1278-HT www.ti.com SBAS447B – MARCH 2009 – REVISED MARCH 2010 S1 9pF AINN Zeff = 14kW ´ (6.75MHz/fMOD) AINN Figure 65. Effective Input Impedances VOLTAGE REFERENCE INPUTS (VREFP, VREFN) AVDD AGND AINP AINP 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 The ADS1278 uses switched-capacitor circuitry to measure the input voltage. Internal capacitors are charged by the inputs and then discharged. Figure 63 shows a conceptual diagram of these circuits. Switch S2 represents the net effect of the modulator circuitry in discharging the sampling capacitor; the actual implementation is different. The timing for switches S1 and S2 is shown in Figure 64. The sampling time (tSAMPLE) is the inverse of modulator sampling frequency (fMOD) and is a function of the mode, the CLKDIV input, and CLK frequency, as shown in Table 7. S2 S1 AGND AVDD ESD Protection Figure 63. Equivalent Analog Input Circuitry The voltage reference for the ADS1278 ADC is the differential voltage between VREFP and VREFN: VREF = (VREFP – VREFN). The voltage reference is common to all channels. The reference inputs use a structure similar to that of the analog inputs with the equivalent circuitry on the reference inputs shown in Figure 66. As with the analog inputs, the load presented by the switched capacitor can be modeled with an effective impedance, as shown in Figure 67. However, the reference input impedance depends on the number of active (enabled) channels in addition to fMOD. As a result of the change of reference input impedance caused by enabling and disabling channels, the regulation and setting time of the external reference should be noted, so as not to affect the readings. tSAMPLE = 1/fMOD S1 ON OFF S2 ON OFF VREFP VREFN AGND AGND AVDD AVDD Figure 64. S1 and S2 Switch Timing for Figure 63 ESD Protection Table 7. Modulator Frequency (fMOD) Mode Selection MODE SELECTION CLKDIV fMOD High-Speed 1 fCLK/4 High-Resolution 1 fCLK/4 1 fCLK/8 Low-Power Low-Speed 0 fCLK/4 1 fCLK/40 0 fCLK/8 Figure 66. Equivalent Reference Input Circuitry VREFP The average load presented by the switched capacitor input can be modeled with an effective differential impedance, as shown in Figure 65. Note that the effective impedance is a function of fMOD. Zeff = VREFN 5.2kW ´ (6.75MHz/fMOD) N N = number of active channels. Figure 67. Effective Reference Impedance Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT 31 ADS1278-HT SBAS447B – MARCH 2009 – REVISED MARCH 2010 www.ti.com ESD diodes protect the reference inputs. To keep these diodes from turning on, make sure the voltages on the reference pins do not go below AGND by more than 0.4 V, and likewise do not exceed AVDD by 0.4 V. If these conditions are possible, external Schottky clamp diodes or series resistors may be required to limit the input current to safe values (see the Absolute Maximum Ratings table). Note that the valid operating range of the reference inputs is limited to the following parameters: Table 8. Clock Input Options MODE SELECTION MAX fCLK (MHz) High-Speed 32.768 High-Resolution 27 27 1 512 13.5 0 256 27 1 2,560 5.4 0 512 Low-Power Low-Speed fCLK/fDATA DATA RATE (SPS) 1 256 128,000 1 512 52,734 CLKDIV 52,734 10,547 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 –0.1 V ≤ VREFN ≤ +0.1 V MODE SELECTION (MODE) VREFN + 0.5 V ≤ VREFP ≤ AVDD + 0.1 V The ADS1278 supports four modes of operation: High-Speed, High-Resolution, Low-Power, and Low-Speed. The modes offer optimization of speed, resolution, and power. Mode selection is determined by the status of the digital input MODE[1:0] pins, as shown in Table 9. The ADS1278 continually monitors the status of the MODE pin during operation. CLOCK INPUT (CLK) The ADS1278 requires a clock input for operation. The individual converters of the ADS1278 operate from the same clock input. At the maximum data rate, the clock input can be either 27 MHz or 13.5 MHz for Low-Power mode, or 2 7MHz or 5.4 MHz for Low-Speed mode, determined by the setting of the CLKDIV input. For High-Speed mode, the maximum CLK input frequency is 32.768 MHz. For High-Resolution mode, the maximum CLK input frequency is 27 MHz. The selection of the external clock frequency (fCLK) does not affect the resolution of the ADS1278. Use of a slower fCLK can reduce the power consumption of an external clock buffer. The output data rate scales with clock frequency, down to a minimum clock frequency of fCLK = 100 kHz. Table 8 summarizes the ratio of the clock input frequency (fCLK) to data rate (fDATA), maximum data rate and corresponding maximum clock input for the four operating modes. As with any high-speed data converter, a high-quality, low-jitter clock is essential for optimum performance. Crystal clock oscillators are the recommended clock source. Make sure to avoid excess ringing on the clock input; keeping the clock trace as short as possible, and using a 50-Ω series resistor placed close to the source end, often helps. 32 Table 9. Mode Selection MODE SELECTION MAX fDATA (1) 00 High-Speed 128,000 01 High-Resolution 52,734 10 Low-Power 52,734 11 Low-Speed 10,547 MODE[1:0] (1) fCLK = 27 MHz max (32.768MHz max in High-Speed mode). When using the SPI protocol, DRDY is held high after a mode change occurs until settled (or valid) data are ready; see Figure 68 and Table 10. In Frame-Sync protocol, the DOUT pins are held low after a mode change occurs until settled data are ready; see Figure 68 and Table 10. Data can be read from the device to detect when DOUT changes to logic 1, indicating that the data are valid. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT ADS1278-HT www.ti.com SBAS447B – MARCH 2009 – REVISED MARCH 2010 MODE[1:0] Pins ADS1278 Mode Previous Mode New Mode tNDR-SPI SPI Protocol DRDY New Mode Valid Data Ready 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 tNDR-FS Frame-Sync DOUT Protocol New Mode Valid Data on DOUT Figure 68. Mode Change Timing Table 10. New Data After Mode Change SYMBOL DESCRIPTION MIN tNDR-SPI Time for new data to be ready (SPI) tNDR-FS Time for new data to be ready (Frame-Sync) SYNCHRONIZATION (SYNC) The ADS1278 can be synchronized by pulsing the SYNC pin low and then returning the pin high. When the pin goes low, the conversion process stops, and the internal counters used by the digital filter are reset. When the SYNC pin returns high, the conversion process restarts. Synchronization allows the conversion to be aligned with an external event, such as the changing of an external multiplexer on the analog inputs, or by a reference timing pulse. Because the ADS1278 converters operate in parallel from the same master clock and use the same SYNC input control, they are always in synchronization with each other. The aperture match among internal channels is typically less than 500 ps. However, the synchronization of multiple devices is somewhat different. At device power-on, variations in internal reset thresholds from device to device may result in uncertainty in conversion timing. The SYNC pin can be used to synchronize multiple devices to within the same CLK cycle. Figure 69 illustrates the timing requirement of SYNC and CLK in SPI format. 127 TYP MAX UNITS 129 Conversions (1/fDATA) 128 Conversions (1/fDATA) See Figure 70 for the Frame-Sync format timing requirement. After synchronization, indication of valid data depends on whether SPI or Frame-Sync format was used. In the SPI format, DRDY goes high as soon as SYNC is taken low; see Figure 69. After SYNC is returned high, DRDY stays high while the digital filter is settling. Once valid data are ready for retrieval, DRDY goes low. In the Frame-Sync format, DOUT goes low as soon as SYNC is taken low; see Figure 70. After SYNC is returned high, DOUT stays low while the digital filter is settling. Once valid data are ready for retrieval, DOUT begins to output valid data. For proper synchronization, FSYNC, SCLK, and CLK must be established before taking SYNC high, and must then remain running. If the clock inputs (CLK, FSYNC or SCLK) are subsequently interrupted or reset, re-assert the SYNC pin. For consistent performance, re-assert SYNC after device power-on when data first appear. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT 33 ADS1278-HT SBAS447B – MARCH 2009 – REVISED MARCH 2010 www.ti.com tCSHD CLK tSCSU tSYN SYNC tNDR DRDY Figure 69. Synchronization Timing (SPI Protocol) 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Table 11. SPI Protocol SYMBOL DESCRIPTION MIN TYP MAX UNITS tCSHD CLK to SYNC hold time 10 tSCSU SYNC to CLK setup time 5 ns tSYN Synchronize pulse width 1 CLK periods tNDR Time for new data to be ready 129 ns Conversions (1/fDATA) tCSHD CLK tSCSU tSYN SYNC FSYNC tNDR Valid Data DOUT Figure 70. Synchronization Timing (Frame-Sync Protocol) Table 12. Frame-Sync Protocol SYMBOL MIN TYP MAX UNITS tCSHD CLK to SYNC hold time 10 tSCSU SYNC to CLK setup time 5 ns tSYN Synchronize pulse width 1 CLK periods tNDR 34 DESCRIPTION Time for new data to be ready 127 Submit Documentation Feedback 128 ns Conversions (1/fDATA) Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT ADS1278-HT www.ti.com SBAS447B – MARCH 2009 – REVISED MARCH 2010 POWER-DOWN (PWDN) After powering up one or more channels, the channels are synchronized to each other. It is not necessary to use the SYNC pin to synchronize them. When a channel is powered down in TDM data format, the data for that channel are either forced to zero (fixed-position TDM data mode) or replaced by shifting the data from the next channel into the vacated data position (dynamic-position TDM data mode). 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 The channels of the ADS1278 can be independently powered down by use of the PWDN inputs. To enter the power-down mode, hold the respective PWDN pin low for at least two CLK cycles. To exit power-down, return the corresponding PWDN pin high. Note that when all channels are powered down, the ADS1278 enters a microwatt (mW) power state where all internal biasing is disabled. In this state, the TEST[1:0] input pins must be driven; all other input pins can float. The ADS1278 outputs remain driven. 3. Detect for non-zero data in the powered-up channel. As shown in Figure 71 and Table 13, a maximum of 130 conversion cycles must elapse for SPI interface, and 129 conversion cycles must elapse for Frame-Sync, before reading data after exiting power-down. Data from channels already running are not affected. The user software can perform the required delay time in any of the following ways: 1. Count the number of data conversions after taking the PWDN pin high. In Discrete data format, the data are always forced to zero. When powering-up a channel in dynamic-position TDM data format mode, the channel data remain packed until the data are ready, at which time the data frame is expanded to include the just-powered channel data. See the Data Format section for details. 2. Delay 129/fDATA or 130/fDATA after taking the PWDN pins high, then read data. ··· CLK tPWDN PWDN DRDY/FSYNC ··· tNDR (1) DOUT (Discrete Data Output Mode) Post Power-Up Data DOUT1 (TDM Mode, Dynamic Position) Normal Position Data Shifts Position Normal Position DOUT1 (TDM Mode, Fixed Position) Normal Position Data Remains in Position Normal Position Figure 71. Power-Down Timing Table 13. Power-Down Timing SYMBOL tPWDN tNDR tNDR DESCRIPTION MIN PWDN pulse width to enter Power-Down mode TYP MAX 2 UNITS CLK periods Time for new data ready (SPI) 129 130 Conversions (1/fDATA) Time for new data ready (Frame-Sync) 128 129 Conversions (1/fDATA) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT 35 ADS1278-HT SBAS447B – MARCH 2009 – REVISED MARCH 2010 www.ti.com FORMAT[2:0] Data can be read from the ADS1278 with two interface protocols (SPI or Frame-Sync) and several options of data formats (TDM/Discrete and Fixed/Dynamic data positions). The FORMAT[2:0] inputs are used to select among the options. Table 14 lists the available options. See the DOUT Modes section for details of the DOUT Mode and Data Position. FORMAT[2:0] INTERFACE PROTOCOL DOUT MODE DATA POSITION 000 SPI TDM Dynamic SPI TDM Fixed SPI Discrete — Frame-Sync TDM Dynamic Frame-Sync TDM Fixed Frame-Sync Discrete — Modulator Mode — — 001 010 011 100 101 110 SCLK may be run as fast as the CLK frequency. SCLK may be either in free-running or stop-clock operation between conversions. Note that one fCLK is required after the falling edge of DRDY until the first rising edge of SCLK. For best performance, limit fSCLK/fCLK to ratios of 1, 1/2, 1/4, 1/8, etc. When the device is configured for modulator output, SCLK becomes the modulator clock output (see the Modulator Output section). 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Table 14. Data Output Format Even though the SCLK input has hysteresis, it is recommended to keep SCLK as clean as possible to prevent glitches from accidentally shifting the data. SERIAL INTERFACE PROTOCOLS Data are retrieved from the ADS1278 using the serial interface. Two protocols are available: SPI and Frame-Sync. The same pins are used for both interfaces: SCLK, DRDY/FSYNC, DOUT[8:1], and DIN. The FORMAT[2:0] pins select the desired interface protocol. DRDY/FSYNC (SPI Format) In the SPI format, this pin functions as the DRDY output. It goes low when data are ready for retrieval and then returns high on the falling edge of the first subsequent SCLK. If data are not retrieved (that is, SCLK is held low), DRDY pulses high just before the next conversion data are ready, as shown in Figure 72. The new data are loaded within one CLK cycle before DRDY goes low. All data must be shifted out before this time to avoid being overwritten. 1/fDATA 1/fCLK DRDY SCLK Figure 72. DRDY Timing with No Readback SPI SERIAL INTERFACE The SPI-compatible format is a read-only interface. Data ready for retrieval are indicated by the falling DRDY output and are shifted out on the falling edge of SCLK, MSB first. The interface can be daisy-chained using the DIN input when using multiple devices. See the Daisy-Chaining section for more information. NOTE: The SPI format is limited to a CLK input frequency of 27 MHz, maximum. For CLK input operation above 27 MHz (High-Speed mode only), use Frame-Sync format. SCLK The serial clock (SCLK) features a Schmitt-triggered input and shifts out data on DOUT on the falling edge. It also shifts in data on the falling edge on DIN when this pin is being used for daisy-chaining. The device shifts data out on the falling edge and the user normally shifts this data in on the rising edge. 36 DOUT The conversion data are output on DOUT[8:1]. The MSB data are valid on DOUT[8:1] after DRDY goes low. Subsequent bits are shifted out with each falling edge of SCLK. If daisy-chaining, the data shifted in using DIN appear on DOUT after all channel data have been shifted out. When the device is configured for modulator output, DOUT[8:1] becomes the modulator data output for each channel (see the Modulator Output section). DIN This input is used when multiple ADS1278s are to be daisy-chained together. The DOUT1 pin of the first device connects to the DIN pin of the next, etc. It can be used with either the SPI or Frame-Sync formats. Data are shifted in on the falling edge of SCLK. When using only one ADS1278, tie DIN low. See the Daisy-Chaining section for more information. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT ADS1278-HT www.ti.com SBAS447B – MARCH 2009 – REVISED MARCH 2010 DOUT Frame-Sync format is similar to the interface often used on audio ADCs. It operates in slave fashion—the user must supply framing signal FSYNC (similar to the left/right clock on stereo audio ADCs) and the serial clock SCLK (similar to the bit clock on audio ADCs). The data are output MSB first or left-justified on the rising edge of FSYNC. When using Frame-Sync format, the FSYNC and SCLK inputs must be continuously running with the relationships shown in the Frame-Sync Timing Requirements. The conversion data are shifted out on DOUT[8:1]. The MSB data become valid on DOUT[8:1] after FSYNC goes high. The subsequent bits are shifted out with each falling edge of SCLK. If daisy-chaining, the data shifted in using DIN appear on DOUT[8:1] after all channel data have been shifted out. When the device is configured for modulator output, DOUT becomes the modulator data output (see the Modulator Output section). SCLK 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 FRAME-SYNC SERIAL INTERFACE DIN This input is used when multiple ADS1278s are to be daisy-chained together. It can be used with either SPI or Frame-Sync formats. Data are shifted in on the falling edge of SCLK. When using only one ADS1278, tie DIN low. See the Daisy-Chaining section for more information. The serial clock (SCLK) features a Schmitt-triggered input and shifts out data on DOUT on the falling edge. It also shifts in data on the falling edge on DIN when this pin is being used for daisy-chaining. Even though SCLK has hysteresis, it is recommended to keep SCLK as clean as possible to prevent glitches from accidentally shifting the data. When using Frame-Sync format, SCLK must run continuously. If it is shut down, the data readback will be corrupted. The number of SCLKs within a frame period (FSYNC clock) can be any power-of-2 ratio of CLK cycles (1, 1/2, 1/4, etc), as long as the number of cycles is sufficient to shift the data output from all channels within one frame. When the device is configured for modulator output, SCLK becomes the modulator clock output (see the Modulator Output section). DOUT MODES For both SPI and Frame-Sync interface protocols, the data are shifted out either through individual channel DOUT pins, in a parallel data format (Discrete mode), or the data for all channels are shifted out, in a serial format, through a common pin, DOUT1 (TDM mode). TDM Mode In TDM (time-division multiplexed) data output mode, the data for all channels are shifted out, in sequence, on a single pin (DOUT1). As shown in Figure 73, the data from channel 1 are shifted out first, followed by channel 2 data, etc. After the data from the last channel are shifted out, the data from the DIN input follow. The DIN is used to daisy-chain the data output from an additional ADS1278 or other compatible device. Note that when all channels of the ADS1278 are disabled, the interface is disabled, rendering the DIN input disabled as well. When one or more channels of the device are powered down, the data format of the TDM mode can be fixed or dynamic. DRDY/FSYNC (Frame-Sync Format) In Frame-Sync format, this pin is used as the FSYNC input. The frame-sync input (FSYNC) sets the frame period, which must be the same as the data rate. The required number of fCLK cycles to each FSYNC period depends on the mode selection and the CLKDIV input. Table 8 indicates the number of CLK cycles to each frame (fCLK/fDATA). If the FSYNC period is not the proper value, data readback will be corrupted. SCLK DOUT1 DRDY (SPI) 1 2 CH1 23 24 25 47 CH2 48 49 71 CH3 72 73 95 96 CH4 97 CH5 167 168 CH7 169 191 CH8 192 193 194 195 DIN FSYNC (Frame-Sync) Figure 73. TDM Mode (All Channels Enabled) Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT 37 ADS1278-HT SBAS447B – MARCH 2009 – REVISED MARCH 2010 www.ti.com TDM Mode, Fixed-Position Data TDM Mode, Dynamic Position Data In this TDM data output mode, the data position of the channels remain fixed, regardless of whether the channels are powered down. If a channel is powered down, the data are forced to zero but occupy the same position within the data stream. Figure 74 shows the data stream with channel 1 and channel 3 powered down. In this TDM data output mode, when a channel is powered down, the data from higher channels shift one position in the data stream to fill the vacated data slot. Figure 75 shows the data stream with channel 1 and channel 3 powered down. Discrete Data Output Mode SCLK 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 In Discrete data output mode, the channel data are shifted out in parallel using individual channel data output pins DOUT[8:1]. After the 24th SCLK, the channel data are forced to zero. The data are also forced to zero for powered down channels. Figure 76 shows the discrete data output format. 1 DOUT1 DRDY (SPI) FSYNC (Frame-Sync) 2 23 25 24 CH1 47 48 49 CH2 71 72 73 CH3 95 96 97 CH4 167 CH5 168 169 CH7 191 192 193 CH8 194 195 DIN Figure 74. TDM Mode, Fixed-Position Data (Channels 1 and 3 Shown Powered Down) SCLK DOUT1 1 2 CH2 23 24 25 47 CH4 48 49 50 CH5 119 120 CH7 121 143 CH8 144 145 145 146 DIN DRDY (SPI) FSYNC (Frame- Sync) Figure 75. TDM Mode, Dynamic Position Data (Channels 1 and 3 Shown Powered Down) 38 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT ADS1278-HT www.ti.com SBAS447B – MARCH 2009 – REVISED MARCH 2010 SCLK 1 2 22 DOUT1 CH1 DOUT2 CH2 DOUT3 CH3 DOUT4 CH4 23 24 25 26 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 DOUT5 CH5 DOUT6 CH6 DOUT7 CH7 DOUT8 CH8 DRDY (SPI) FSYNC (Frame-Sync) Figure 76. Discrete Data Output Mode DAISY-CHAINING Multiple ADS1278s can be daisy-chained together to output data on a single pin. The DOUT1 data output pin of one device is connected to the DIN of the next device. As shown in Figure 77, the DOUT1 pin of device 1 provides the output data to a controller, and the DIN of device 2 is grounded. Figure 78 shows the data format when reading back data. The maximum number of channels that may be daisy-chained in this way is limited by the frequency of fSCLK, the mode selection, and the CLKDIV input. The frequency of fSCLK must be high enough to completely shift the data out from all channels within one fDATA period. Table 15 lists the maximum number of daisy-chained channels when fSCLK = fCLK. To increase the number of data channels possible in a chain, a segmented DOUT scheme may be used, producing two data streams. Figure 79 illustrates four ADS1278s, with pairs of ADS1278s daisy-chained together. The channel data of each daisy-chained pair are shifted out in parallel and received by the processor through independent data channels. Table 15. Maximum Channels in a Daisy-Chain (fSCLK = fCLK) MODE SELECTION CLKDIV MAXIMUM NUMBER OF CHANNELS High-Speed 1 10 High-Resolution 1 21 1 21 Low-Power Low-Speed 0 10 1 106 0 21 Whether the interface protocol is SPI or Frame-Sync, it is recommended to synchronize all devices by tying the SYNC inputs together. When synchronized in SPI protocol, it is only necessary to monitor the DRDY output of one ADS1278. In Frame-Sync interface protocol, the data from all devices are ready after the rising edge of FSYNC. Since DOUT1 and DIN are both shifted on the falling edge of SCLK, the propagation delay on DOUT1 creates a setup time on DIN. Minimize the skew in SCLK to avoid timing violations. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT 39 ADS1278-HT SBAS447B – MARCH 2009 – REVISED MARCH 2010 www.ti.com U1 U2 SYNC SYNC CLK SYNC CLK SCLK DOUT1 DRDY Output from Device 1 DOUT1 DOUT from Devices 1 and 2 DIN SCLK SCLK 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Note: DRDY CLK DIN The number of chained devices is limited by the SCLK rate and device mode. Figure 77. Daisy-Chaining of Two Devices, SPI Protocol (FORMAT[2:0] = 000 or 001) SCLK 1 DOUT1 2 25 CH1, U1 26 49 CH2, U1 50 CH3, U1 73 74 97 CH4, U1 98 CH5, U1 193 194 217 CH1, U2 218 CH2, U2 385 386 DIN2 DRDY (SPI) FSYNC (Frame-Sync) Figure 78. Daisy-Chain Data Format of Figure 77 SYNC CLK SYNC SYNC CLK DIN SCLK FSYNC Note: SYNC CLK DOUT1 DIN U1 U2 U3 U4 SYNC CLK DOUT1 DIN Serial Data Devices 3 and 4 CLK DOUT1 DIN FSYNC FSYNC FSYNC FSYNC SCLK SCLK SCLK SCLK DOUT1 Serial Data Devices 1 and 2 The number of chained devices is limited by the SCLK rate and device mode. Figure 79. Segmented DOUT Daisy-Chain, Frame-Sync Protocol (FORMAT[2:0] = 011 or 100) 40 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT ADS1278-HT www.ti.com SBAS447B – MARCH 2009 – REVISED MARCH 2010 POWER SUPPLIES space The ADS1278 has three power supplies: AVDD, DVDD, and IOVDD. AVDD is the analog supply that powers the modulator, DVDD is the digital supply that powers the digital core, and IOVDD is the digital I/O power supply. The IOVDD and DVDD power supplies can be tied together if desired (1.8 V). To achieve rated performance, it is critical that the power supplies are bypassed with 0.1-mF and 10-mF capacitors placed as close as possible to the supply pins. A single 10-mF ceramic capacitor may be substituted in place of the two capacitors. space MODULATOR OUTPUT 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 The ADS1278 incorporates a 6th-order, single-bit, chopper-stabilized modulator followed by a multi-stage digital filter that yields the conversion results. The data stream output of the modulator is available directly, bypassing the internal digital filter. The digital filter is disabled, reducing the DVDD current, as shown in Table 16. In this mode, an external digital filter implemented in an ASIC, FPGA, or similar device is required. To invoke the modulator output, tie FORMAT[2:0], as shown in Figure 81. DOUT[8:1] then becomes the modulator data stream outputs for each channel and SCLK becomes the modulator clock output. The DRDY/FSYNC pin becomes an unused output and can be ignored. The normal operation of the Frame-Sync and SPI interfaces is disabled, and the functionality of SCLK changes from an input to an output, as shown in Figure 81. Figure 80 shows the start-up sequence of the ADS1278. At power-on, bring up the DVDD supply first, followed by IOVDD and then AVDD. Check the power-supply sequence for proper order, including the ramp rate of each supply. DVDD and IOVDD may be sequenced at the same time if the supplies are tied together. Each supply has an internal reset circuit whose outputs are summed together to generate a global power-on reset. After the supplies have exceeded the reset thresholds, 218 fCLK cycles are counted before the converter initiates the conversion process. Following the CLK cycles, the data for 129 conversions are suppressed by the ADS1278 to allow output of fully-settled data. In SPI protocol, DRDY is held high during this interval. In frame-sync protocol, DOUT is forced to zero. The power supplies should be applied before any analog or digital pin is driven. For consistent performance, assert SYNC after device power-on when data first appear. DVDD IOVDD AVDD 1V nom Table 16. Modulator Output Clock Frequencies CLKDIV MODULATOR CLOCK OUTPUT (SCLK) DVDD (mA) 00 1 fCLK/4 8 01 1 fCLK/4 7 1 fCLK/8 4 0 fCLK/4 4 1 fCLK/40 1 0 fCLK/8 1 MODE [1:0] 10 (1) 11 1V nom (1) 3V nom DOUT1 DOUT2 (1) Modulator Data Channel 1 Modulator Data Channel 2 IOVDD Internal Reset CLK 18 2 fCLK DIN 129 (max) tDATA FORMAT0 DRDY (SPI Protocol) FORMAT1 DOUT8 FORMAT2 SCLK Modulator Data Channel 8 Modulator Clock Output DOUT (Frame-Sync Protocol) Figure 81. Modulator Output Valid Data Figure 80. Start-Up Sequence Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT 41 ADS1278-HT SBAS447B – MARCH 2009 – REVISED MARCH 2010 www.ti.com In modulator output mode, the frequency of the modulator clock output (SCLK) depends on the mode selection of the ADS1278. Table 16 lists the modulator clock output frequency and DVDD current versus device mode. Figure 82 shows the timing relationship of the modulator clock and data outputs. TEST MODE PIN MAP INPUT PINS OUTPUT PINS PWDN1 DOUT1 PWDN2 DOUT2 PWDN3 DOUT3 PWDN4 DOUT4 PWDN5 DOUT5 PWDN6 DOUT6 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 The data output is a modulated 1s density data stream. When VIN = +VREF, the 1s density is approximately 80% and when VIN = –VREF, the 1s density is approximately 20%. Table 17. Test Mode Pin Map (TEST[1:0] = 11) Modulator Clock Output Modulator Data Output SCLK DOUT (13ns max) Figure 82. Modulator Output Timing PIN TEST USING TEST[1:0] INPUTS The test mode feature of the ADS1278 allows continuity testing of the digital I/O pins. In this mode, the normal functions of the digital pins are disabled and routed to each other as pairs through internal logic, as shown in Table 17. The pins in the left column drive the output pins in the right column. Note: some of the digital input pins become outputs; these outputs must be accommodated in the design. The analog input, power supply, and ground pins all remain connected as normal. The test mode is engaged by setting the pins TEST [1:0] = 11. For normal converter operation, set TEST[1:0] = 00. Do not use '01' or '10'. 42 PWDN7 DOUT7 PWDN8 DOUT8 MODE0 DIN MODE1 SYNC FORMAT0 CLKDIV FORMAT1 FSYNC/DRDY FORMAT2 SCLK VCOM OUTPUT The VCOM pin provides a voltage output equal to AVDD/2. The intended use of this output is to set the output common-mode level of the analog input drivers. The drive capability of the output is limited; therefore, the output should only be used to drive high-impedance nodes (> 1 MΩ). In some cases, an external buffer may be necessary. A 0.1-mF bypass capacitor is recommended to reduce noise pickup. Submit Documentation Feedback OPA350 VCOM » (AVDD/2) 0.1mF Figure 83. VCOM Output Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT ADS1278-HT www.ti.com SBAS447B – MARCH 2009 – REVISED MARCH 2010 APPLICATION INFORMATION 6. Analog Inputs: The analog input pins must be driven differentially to achieve specified performance. A true differential driver or transformer (ac applications) can be used for this purpose. Route the analog inputs tracks (AINP, AINN) as a pair from the buffer to the converter using short, direct tracks and away from digital tracks. A 1-nF to 10-nF capacitor should be used directly across the analog input pins, AINP and AINN. A low-k dielectric (such as COG or film type) should be used to maintain low THD. Capacitors from each analog input to ground can be used. They should be no larger than 1/10 the size of the difference capacitor (typically 100 pF) to preserve the ac common-mode performance. 7. Component Placement: Place the power supply, analog input, and reference input bypass capacitors as close as possible to the device pins. This layout is particularly important for small-value ceramic capacitors. Larger (bulk) decoupling capacitors can be located farther from the device than the smaller ceramic capacitors. 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 To obtain the specified performance from the ADS1278, the following layout and component guidelines should be considered. 1. Power Supplies: The device requires three power supplies for operation: DVDD, IOVDD, and AVDD. The allowed range for DVDD is 1.65 V to 1.95 V; the range of IOVDD is 1.65 V to 3.6 V; AVDD is restricted to 4.75 V to 5.25 V. For all supplies, use a 10-mF tantalum capacitor, bypassed with a 0.1-mF ceramic capacitor, placed close to the device pins. Alternatively, a single 10-mF ceramic capacitor can be used. The supplies should be relatively free of noise and should not be shared with devices that produce voltage spikes (such as relays, LED display drivers, etc.). If a switching power-supply source is used, the voltage ripple should be low (less than 2 mV) and the switching frequency outside the passband of the converter. 2. Ground Plane: A single ground plane connecting both AGND and DGND pins can be used. If separate digital and analog grounds are used, connect the grounds together at the converter. 3. Digital Inputs: It is recommended to source-terminate the digital inputs to the device with 50-Ω series resistors. The resistors should be placed close to the driving end of digital source (oscillator, logic gates, DSP, etc.) This placement helps to reduce ringing on the digital lines (ringing may lead to degraded ADC performance). 4. Analog/Digital Circuits: Place analog circuitry (input buffer, reference) and associated tracks together, keeping them away from digital circuitry (DSP, microcontroller, logic). Avoid crossing digital tracks across analog tracks to reduce noise coupling and crosstalk. 5. Reference Inputs: It is recommended to use a minimum 10-mF tantalum with a 0.1-mF ceramic capacitor directly across the reference inputs, VREFP and VREFN. The reference input should be driven by a low-impedance source. For best performance, the reference should have less than 3 mVRMS in-band noise. For references with noise higher than this level, external reference filtering may be necessary. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1278-HT 43 PACKAGE OPTION ADDENDUM www.ti.com 16-Jan-2012 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) ADS1278SHFQ ACTIVE CFP HFQ 84 1 TBD AU N / A for Pkg Type Add to cart ADS1278SKGDA ACTIVE XCEPT KGD 0 36 TBD Call TI N / A for Pkg Type Add to cart (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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