September 1999 PRELIMINARY ML6411 Programmable Video Digitizer with Selectable Gain and Clamps GENERAL DESCRIPTION FEATURES The ML6411 is a Dual Video A/D converter, incorporating two input sample and holds, two high speed 8-Bit A/D converters, programmable gain control, selectable clamps, multi-phase clocking, and reference voltage generation. The ML6411 can be used to convert the following analog signals to digital signals: two composite channels or Svideo channel. ■ Complete video digitizer for Y/C and CV video ■ Contains A/D’s with scalable gain, selectable clamps, and clock generation (programmable via serial bus) ■ Two 8-Bit +/- ½ LSB Differential Non-Linearity with 30MHz guaranteed conversion All inputs are provided with appropriate input selectable clamps to establish DC level. The clamps are full DC restore circuits with the A-to-D converters in each respective correction loop. The clamps are selectable to 16, 24, 64, and 128. The programmable gain control provides various possibilities to select and adjust the gain via two separate mechanisms: Sync-Suppressed Gain Control (SGC ) for sync suppressed video such as RGB, and User Gain Control (UGC) for video formats that require scalable gain settings. Each of these can be programmed through a serial bus. ■ Two Gain Control Mechanisms for programmable or sync-suppressed video gain control ■ Selectable Video Clamping: 16, 24, 64, 128 ■ Selectable Video Gain: 3dB to –6dB ■ Operating total power dissipation less than 425mW ■ Power down mode and Tri-state output control ■ Applications: Video Capture, Video Editing, Video Cameras, Y/C and CV analog to digital conversion ■ 44-pin TQFP BLOCK DIAGRAM 35 AVCC1 44 38 AVCC2 41 AVCC3 17 DVCC 15 VCCO 2 CLAMP GATE 33 DGND 32 DVCC 18 RESET 23 OEA 11 OEB 39 VINN REF1 CHANNEL A 36 Y/CV1 S/H GAIN PRESET SGC SYNC SUPPRESS GAIN CONTROL UGC USER GAIN CONTROL Y OR CV1 CHANNEL A ADC LATCH Y/CV1 GAIN PRESET SGC SYNC SUPPRESS GAIN CONTROL UGC USER GAIN CONTROL C OR CV2 CHANNEL B ADC LATCH C/CV2 AOUT<7:0> 24:31 14 1 PD BOOSTB CV/S_MODE BOOSTA GNB<5:0> BPEAK CLPA<1:0> SERIAL BUS CLPB<1:0> TIMING GENERATOR CLK BOUT<7:0> 3:10 19 SCLK 20 SDAT CLKDIV CLAMP LEVEL SELECT GNA<5:0> STDA <1:0> S/H APEAK C/CV2 STDB <1:0> CHANNEL B 42 21 REFIN 22 REFOUT 12 VCC 37 AGNDI 40 AGND2 43 AGND3 13 GNDO 16 DGND 34 NC 1 ML6411 PIN CONFIGURATION NC AVCC1 Y/CV1 AGND1 AVCC2 VINN AGND2 AVCC3 C/CV2 AGND3 REF1 ML6411 44-Pin TQFP (H44-14) 44 43 42 41 40 39 38 37 36 35 34 PD 1 33 DGND CLAMP GATE 2 32 DVCC BOUT0 3 31 AOUT7 BOUT1 4 30 AOUT6 BOUT2 5 29 AOUT5 BOUT3 6 28 AOUT4 BOUT4 7 27 AOUT3 BOUT5 8 26 AOUT2 BOUT6 9 25 AOUT1 BOUT7 10 24 AOUT0 OEB 11 23 OEA 2 REFIN REFOUT SCLK SDAT RESET DVCC DGND VCCO CLK VCC GNDO 12 13 14 15 16 17 18 19 20 21 22 ML6411 PIN DESCRIPTION PIN NAME FUNCTION PIN NAME FUNCTION 1 PD When high, power downs the chip. TTL compatible 23 OEA Output enable for the AOUT channel. Active high. TTL compatible 2 Clamp Gate Luma clamp gate input. Clamps to selected level when high. TTL compatible 3-10 BOUT<7:0> Either chroma bits 7 (BOUT7MSB) to 0 (BOUT0 LSB) or composite bits 7 (MSB) to 0 (LSB). TTL compatible 11 OEB 24-31 AOUT<7:0> Luma bit 7 (AOUT7 MSB) thru Luma bit 0 (AOUT0 LSB) outputs or Composite bit 7 (MSB) thru Composite bit 0 (LSB) outputs. TTL compatible 32 DVCC Digital supply pin 33 DGND Digital ground pin Output enable for the BOUT channel. Active low. TTL compatible 34 NC No connection 12 VCC Reference voltage. Tie to Digital VCC 35 AVCC1 Analog supply pin 13 GNDO Output ground pin 36 Y/CV1 Y or CV (primary composite) input pin 14 CLK Clock input pin. TTL compatible 37 AGND1 Analog ground pin 15 VCCO Output supply pin 38 AVCC2 Analog supply pin 16 DGND Digital ground pin 39 VINN Internal common mode bias of the A/D 17 DVCC Digital supply pin 40 AGND2 Analog ground pin 18 RESET Resets the control registers to nominal values. Active HIGH. TTL compatible input 41 AVCC3 Analog supply pin 42 C/CV2 C (modulated chroma) or CV (2nd composite for dual channel mode) input pin 43 AGND3 Analog ground pin 44 REF1 Internal reference. Tie this pin thru 0.1uF capacitor to analog ground for proper operation 19 SCLK Control Bus Clock. Address latched on rising edge, data on falling edge 20 SDAT Control data 21 REFIN Internal reference tied to REFOUT 22 REFOUT Internal reference tied to REFIN 3 ML6411 ABSOLUTE MAXIMUM RATINGS OPERATING CONDITIONS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Temperature Range ........................................ 0°C to 70°C Supply Range (AVCC, DVCC, VCCO) ........... 4.5V to 5.5V DC Supply Voltage (AVCC, DVCC, VCCO) .... -0.3V to 7V Analog & Digital Inputs/Outputs ........ -0.3 to AVCC+0.3V Input Current Per Pin .............................. -25mA to 25mA Storage Temperature Range...................... –65°C to 150°C Junction Temperature ............................................. 125°C ELECTRICAL CHARACTERISTICS Unless otherwise specified, AVCC, DVCC, VCCO = 4.5V to 5.5V, TA = Operating Temperature Range (Note 1) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 425 600 mW POWER CONSUMPTION Pdiss Max power dissipation Cload = 0pF SUPPLY AVCC Analog supply voltage 4.5 5.5 V DVCC Digital supply voltage 4.5 5.5 V VCCO Output supply voltage 4.5 5.5 V IDD Digital supply current FCLK = 30MHz 17 30 mA IO Output supply current FCLK=30MHz, VIN=NTSC, 40IRE modulated rate, Cload=0pF 7 mA 5 mA Ishut Shutdown current INPUT SIGNALS (CLK, CLAMP GATE, OEA, OEB) VIL Input Low Voltage 0 0.8 V VIH Input High Voltage 2.4 DVCC V -5 5 µA IIL CIN1 High level Input Current DVCC - 0.1V Input Capacitance 3 pF INPUT SIGNALS (Y / CV1, C / CV2) VIN CIN2Input Input Voltage Peak-to-peak for 2V 1.0 2.0 3.0 V Peak-to-peak for 1V 0.5 1.0 1.5 V Capacitance 3 pF Icharge Clamp Charge Current Clamp Gate = High, Digital Output < Clamp level 700 µA Idisch Clamp Discharge Current Clamp Gate = High, Digital Output > Clamp level –700 µA A TO D CONVERTER OUTPUTS (AOUT<7:0>, BOUT<7:0>) Low level output voltage Io = 2mA High level output voltage Leakage current 4 Tri-state mode 0 0.6 2.4 VCCO -20 20 V µA ML6411 ELECTRICAL CHARACTERISTICS SYMBOL (Continued) PARAMETER CONDITIONS MIN TYP MAX UNITS SWITCHING CHARACTERISTICS FCLK Clock input max frequency 30 MHz Tcph Clock input min high time See Figure 2 15 ns Tcpl Clock input min low time See Figure 2 15 ns Clamp Gate Width VIN magnitude 2V max 1.5 µs Clamp Gate Width VIN magnitude > 2V 3.5 µs ANALOG SIGNAL PROCESSING Y/C Gain Match CGAIN1 = CGAIN2 = 0 1.01 V/V Chroma Crosstalk YIN = 5MHz and CIN = at DC; or YIN = at DC and CIN = 5MHz –60 dB Differential Gain VIN = NTSC 40 IRE modulated ramp FCLK = 27 MHz 2 % Differential Phase VIN = NTSC 40 IRE modulated ramp FCLK = 27 MHz 1 degree Signal to Noise Ratio VIN = 2V, 10MHz sinewave, FCLK = 20MHz 48 dB VIN = 2V, 10MHz sinewave, FCLK = 30MHz 45 dB Distortion VIN = 2V, 10MHz, FCLK = 20MHz 0.3 % SFDR VIN = 2V, 10MHz, FCLK = 20MHz 54 dB TRANSFER FUNCTION DC integral linearity @ 27MHz ±0.8 LSB DC differential linearity @ 27MHz ±0.5 LSB GAIN CONTROL GRES Gain accuracy of UGC for a given gain level Input = 1VP-P or 2VP-P (See Note 2) -30mV 30mV % Absolute gain error 5 % Gain accuracy for standard preset gain, GPRESET 1 % OUTPUT TIMING tds Sampling delay See Figure 2 8 ns tho Output hold time See Figure 2 10 ns tdo Output delay time See Figure 2 12 ns toe Output enable time See Figure 2 5 ns tod Output disable time See Figure 2 5 ns Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. Note 2: Volt Peak-to-Peak = VP-P 5 ML6411 SERIAL BUS Unless otherwise specified, AVCC, DVCC, VCCO = 4.5V to 5.5V, TA = Operating Temperature Range (Note 1) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS INPUT (SDAT) VIL Low Level Input Voltage 0 0.8 V VIH High Level Input Voltage VCC – 0.8 VCC V IIL Low Level Input Current VIN = 0V 1.0 mA IIH High Level Input Current VIN = DVCC 1.0 mA ZIN Input Impedance fCLK = 100kHz CIN Input Capacitance 1 MW 2 pF SYSTEM TIMING (SCLK) fCLOCK SCLK Frequency VHYS Input Hysteresis tSPIKE Spike Suppression tWAIT 100 0.2 Max Length for Zero Response kHz V 50 ns Wait Time From STOP to START On SDATA 1.3 µs tHD/START Hold Time for START On SDATA 0.6 µs tSU/START 0.6 µs Setup Time for START On SDATA tLOW Min LOW Time On SCLK 1.3 µs tHI Min HIGH Time On SCLK 0.6 µs tHD/DATA Hold Time On SDATA tSU/DATA Setup Time On 5.0 Fast mode 100 ns Slow mode 250 ns tLH Rise Time for SCLK & SDATA 30 300 ns tHL Fall Time for SCLK & SDATA 30 300 ns Setup Time for STOP On SDATA 0.6 tSU/STOP Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions. Note 2: All specifications include reconstruction filter and line driver. Note 3: Normalized to burst. 6 µs µs ML6411 FUNCTIONAL DESCRIPTION GENERAL The Universal Video Digitizer is a single-chip Video A/D converter with an analog front end which is intended for analog to digital conversion of 2V peak-to-peak (VP-P) or 1VP-P signals at rates up to 30 MSPS through a high performance A/D with ±½ DNL performance. It forms a complete solution for data conversion of dual CV and Y/C signals including gain settings and clamp settings by incorporating clamps, user selectable gain controls (UGC and SGC), bias and clock generation. The ML6411 consist of two video clamps, two sample and hold amplifiers, two three-stage pipeline A/D converters, digital error correction circuitry, selectable clamps, programmable gain control, bias voltage generation and clock generation. The operating power dissipation is 425mW typical. INPUT FOR VARIOUS VIDEO MODES The ML6411 can digitize various analog video inputs: S-Video (Y/C), or composite video (CV). Again, for each video channel, the gain and clamps can be selected. A description of each of these modes is described below. The Table 1 below provides a summary of the various modes. Dual Channel Composite Video (CV1 and CV2) Mode The composite input channels are provided through the Y/ CV1 (A channel) and C/CV2 (B channel) pins. To activate this mode, the CV/S_Mode Bit (Register D, Bit D3) must set HIGH (D3=1). This mode is selectable via serial bus. In this mode, the two S&H circuits for each channel can be clocked up to 30MHz. Each CV channel can be then scaled for a desired gain setting using the User Gain Control (UGC). Standard gain selection can also be chosen using the preset gain modes for 2VP-P signals only. For 1VP-P signals, the preset gain selection mode is not available; however the UGC functions can be used to select gain values. The preset gain modes are for typical NTSC or PAL composite video and are selectable via serial bus through the STDA<1:0> and STDB<1:0> (Register B, Bits B4, B3, B2, and B1) bits. When using the preset gain mode, the output signals are enhanced by amplifying the input signal by the value of GPRESET (see Table 2). In addition, the clamp levels can be selected for either channel for 16, 24, 64, and 128 binary levels (depending on the channel) via the serial bus through the CLPA<1:0> and CLPB<1:0> bits (see Table 3). S-Video (Y / C) Mode The input channels are provided through the Y/CV1 (A channel) and C/CV2 (B channel) pins. To activate this mode, the CV/S_Mode Bit (Register D, Bit D3) must be set LOW (D3=0). This mode is selectable via serial bus. In this mode, the two S&H circuits for each channel can be clocked up to 30MHz. Each channel (Y and C) can be then scaled for a desired gain setting using the User Gain Control (UGC). Standard gain selection can also be chosen using the preset gain modes for 2VP-P signals only. For 1VP-P signals, the preset gain selection mode is not available; however the UGC functions can be used to select gain values. The preset gain modes are for typical NTSC or PAL S-Video and are selectable via serial bus through the STDA<1:0> and STDB<1:0> (Register B, Bits B4, B3, B2, and B1) bits. When using the preset gain mode, the output signals are enhanced by amplifying the input signal by the value of GPRESET (see Table 2). In addition, the clamp levels can be selected for either channel for 16, 24, 64, and 128 binary levels (depending on the channel 24 not available for C-channel) via the serial bus through the CLPA<1:0> and CLPB<1:0> bits (see Table 3). Input Voltage Selection The ML6411 can support 1VP-P and 2VP-P input video. Selection for the voltage input is programmed via control register on the APEAK and BPEAK bits, A channel and B channel, respectively (see Table 7). GAIN SELECTION CONTROL (UGC AND SGC) There are two separate control mechanisms that can be used to scale gain settings for the incoming video format: User Gain Control (UGC) and Sync-suppressed Gain Control (SGC). User Gain Control (UGC) The user gain control function is achieved through a variation of the full scale range of the A/D converters. This will provide the user with approximately +/-3dB gain variation as needed. Y reference and C reference are supplied by two independent DACs. The user can adjust the gain of each ADC independently providing the 6-Bit code for the gain control through serial interface for each A/D. Each step change can increment or decrement the gain by 3% and allows for up to 64 different gain setting levels per channel. The UGC can be used for both 1V and 2VP-P inputs. When using the UGC mode, the output signals are enhanced by amplifying the input signal by the value of GUGC. Table 4 provides a summary of the possible incremental ranges. The gain accuracy of the UGC for each of the 64 levels is +/-1.5%. The UGC gain settings are selected via serial bus by programming Registers C, D, and E on the GNA<5:0> bits for the A-channel and GNB<5:0> bits for the B-channel. Unity gain is set at default for GNA<5:0> = 100,000 and GNB<5:0> = 100,000. For values of GNA<5:0> and GNB<5:0> from 100,000 to 111,111, the gain increases monotonically from 0dB (unity gain) to almost 3dB (actually 1.48x), while from 100,000 to 000,000 the gain decreases monotonically from 0dB (unity gain) to –3dB (0.5x). Note that Table 4 provides only approximation of gain values: actual gain values can vary from device to device. 7 ML6411 FUNCTIONAL DESCRIPTION (Continued) Sync-suppress Gain Control (SGC) This control function is used for video where the sync signal is suppressed (i.e., chroma signal). In which case, the SGC can be activated to provide a 25% gain boost to each channel (Y and C). The SGC is activated via serial bus (Register D, Bits D1 and D2), also called the BOOSTA and BOOSTB programming bits. In the SGC mode, the output signals are enhanced by amplifying the input signal by the value of GSGC (see Table 5). Using The Gain Control Blocks Together The UGC combined provides digital gain control data to a variable gain control circuit while the SGC is directly in the A/D processing path. Hence the UGC sets variable gain control of the A/D. When the UGC and the SGC are enabled. In this mode, the output gain is the combination of the different gain setting mechanisms: For 1VP-P signals, Equation 1: Output Gain = [<Input Signal> x GUGC x GSGC ] + Clamp Level For 2VP-P signals, Equation 2: Output Gain = [<Input Signal> x GUGC x GSGC x GPRESET ] + Clamp Level Note that separate GUGC, GSGC, and GPRESET values are available for both channels A and B. There are up to 640 combinations of gain settings possible. WARNING Note that it is possible to exceed the output voltage ranges for standard video using the combination of the gain setting mechanisms on the input signal. The user should take precaution in understanding the gain limits necessary and make the proper selection for each of the gain mechanism. A/D CONVERTER The A/D conversion is performed via a three stage pipeline architecture. The first two stages quantize their input signal to the three bits, then subtract the result from the input and amplify by a factor of four. This creates a residue signal which spans the full scale range of the following converter. The subtraction and amplification is performed via a bottom plate sampling capacitor feedback amplifier, similar to the input sample and hold. The third stage quantizes the signal to four bits. One bit from each of the last two stages is used for error correction. The first stage A/D performs the conversion at the end of the sample and holds period, approximately one-half 8 cycle later, after the subtraction/amplification of the first stage has settled. The third stage A/D performs the conversion after another one-half cycle delay, when the second stage has settled. Error correction is then performed and, one clock cycle later, data is transferred to the output latch. This creates a 3 clock latency. INPUT SAMPLE AND HOLD The input sample and hold consist of a bottom plate sampling capacitor feedback amplifier. The input capacitance is 0.4pF, plus transmission gate. The input to the sample and hold is driven differentially. The sample and hold samples the input signal during the positive half cycle of the input clock, and holds the last value of the input during the negative half cycle of the input clock. The settling time of the amplifier is less than 10nS. INPUT COUPLING AND DC CLAMP PROGRAM SELECTION All inputs are AC coupled into the positive sampling capacitor of the sample and hold. Each input capacitor becomes the integrating component for the DC restore clamps. The direction of clamp current depends on the data at the A/D output during the clamp gating pulse. For the color channel (i.e. C in Y/C mode) the clamp level is 128. If the code is above this number during the gate pulse, the current source will sink current from the input capacitor in order to drive the input voltage lower. Otherwise, the current source will source current to raise the input voltage. Clamp currents are shown in Table 6. The clamp values of 16, 24, 64, 128 can be select via register program (Register A and B) through the serial bus. Note that there is no Level 24 in the B channel. The CLPA<1:0> controls the clamp settings for the A-channel, while the CLPB<1:0> controls the clamp settings for the B-channel. For example, clamp values can be selected independently for the chroma channel in Y/C mode (CLPB<1:0>). Once the clamp settings are selected, the clamps are active when the ClampGate is asserted HIGH. The ClampGate signal is an external signal provided by a genlock/sync clock device that is genlocked to the horizontal sync of the video input. The ML6431 can be used to generate the ClampGate signal (see Application Section). SERIAL PROGRAM The ML6411 can be register programmed through the serial bus. Clamping and gain setting can be selected for various video formats. This serial bus is a standard threepin interface with data, clock, and ground. See Timing Control information. Table 7 provides a description the Register information. Please see section “Input Coupling and DC Clamp Program Selection” and “Gain Select Control”. ML6411 FUNCTIONAL DESCRIPTION (Continued) RESET DEFAULT MODE ■ The ML6411 provides a RESET pin that programs the Control Registers as described in Table 8. The RESET pin is active HIGH. Basically, the ML6411 on RESET defaults to: UGC is set to unity gain (GUGCA = 1 and GUGCB = 1) to either Y or C channels (see Table 4 and GNA and GNB bits) ■ Input pin are set for 2VP-P inputs on both Y and C ■ S-Video mode. Ideally, for PAL S-Video since Preset Mode (STDA and STDB bits) is set to unity gain boost (GPRESET = 1) for both Y and C (see Table 2) ■ Y is clamped to 16. C is clamped to 128 (see Table 3) and CLPA and CLPB bits) MODE REGISTER/BIT VALUES Dual CV Register D, Bit D3= CV/S_Mode =1 S-Video Register D, Bit D3= CV/S_Mode =0 CHANNEL SIGNAL INPUT OUPUT A CV1 Y/CV1 pin AOUT<7:0> B CV2 C/CV2 pin BOUT<7:0> A Y Y/CV1 pin AOUT<7:0> B C C/CV2 pin BOUT<7:0> OPTIONS Gain Control Selection (UGC, SGC) and Clamp Selection. 1VP-P or 2VP-P inputs. Serial Bus Programable. Gain Control Selection (UGC, SGC) and Clamp Selection. 1VP-P or 2VP-P inputs. Serial Bus Programable. Note: Volt Peak-to-Peak = VP-P Table 1. Various Video Modes Using the ML6411 and Key Features 9 ML6411 DUAL COMPOSITE VIDEO MODE TYPICAL INPUTS GAIN SELECTION OF AMPLIFIERS GAIN FACTOR OF AMPLIFIERS (nominal) Channel A Channel B Channel A Channel B Channel A Channel B CV1 Input (mV) CV2 Input (mV) STDA<1:0> STDB<1:0> GPRESETA GPRESETB Composite Video NTSC 1320 1320 01 01 1.061 1.061 Composite Video PAL 1400 1400 00 00 1 1 Preset Mode 1 1320 1320 01 11 1.061 0.7495 Preset Mode 2 1428 1428 11 00 1.02 1 Preset Mode 3 1400 1400 00 11 1 0.7495 Preset Mode 4 1294 1294 10 10 1.082 1.082 STANDARD S-VIDEO MODE TYPICAL INPUTS GAIN SELECTION OF AMPLIFIERS GAIN FACTOR OF AMPLIFIERS (nominal) Channel A Channel B Channel A Channel B Channel A Channel B Y Input (mV) C Input (mV) STDA<1:0> STDB<1:0> GPRESETA GPRESETB S-Video NTSC 1320 1320 01 01 1.061 1.061 S- Video PAL 1400 1400 00 00 1 1 Preset Mode 1 1320 1320 01 11 1.061 0.7495 Preset Mode 2 1428 1428 11 00 1.02 1 Preset Mode 3 1400 1400 00 11 1 0.7495 Preset Mode 4 1294 1294 10 10 1.082 1.082 STANDARD Table 2. Video Standard Preset Gain Selection Modes 10 ML6411 DUAL COMPOSITE MODE CLAMP LEVEL Channel A (CV1) CLPA1 BIT CLPA0 BIT 16 0 0 24 1 0 64 0 1 128 1 1 CLPB1 BIT CLPB0 BIT 16 1 0 64 1 1 128 0 X CLPA1 BIT CLPA0 BIT 16 0 0 24 1 0 64 0 1 128 1 1 CLPB1 BIT CLPB0 BIT 16 1 0 64 1 1 128 0 X CLAMP LEVEL Channel B (CV2) NOTES Typical CV Clamp. Defaults to this value on RESET NOTES Typical CV clamp. Defaults to this value on RESET S-VIDEO MODE CLAMP LEVEL Channel A (Y) CLAMP LEVEL Channel B (C) NOTES Typical Y clamp. Defaults to this value on RESET NOTES Typical C clamp. Defaults to this value on RESET Note: X = Don't Care Table 3. Programmable Clamp Level Selection 11 ML6411 A-CHANNEL B-CHANNEL GNA5 GNA4 GNA3 GNA2 GNA1 GNA0 GAIN FACTOR GUGCA GNB5 GNB4 GNB3 GNB2 GNB1 GNB0 (NOMINAL) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0.50 0.52 0.53 0.55 0.56 0.58 0.59 0.61 0.63 0.64 0.66 0.67 0.69 0.70 0.72 0.73 0.75 0.77 0.78 0.80 0.81 0.83 0.84 0.86 0.88 0.89 0.91 0.92 0.94 0.95 0.97 0.98 1.00 1.02 1.03 1.05 1.06 1.08 1.09 1.11 1.13 1.14 1.16 1.17 1.19 1.20 1.22 1.23 1.25 1.27 1.28 1.30 1.31 1.33 1.34 1.36 1.38 1.39 1.41 1.42 1.44 1.45 1.47 1.48 (NOMINAL) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Table 4. Gain Approximations for User Gain Control (UGC) Block 12 GAIN FACTOR GUGCB 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0.50 0.52 0.53 0.55 0.56 0.58 0.59 0.61 0.63 0.64 0.66 0.67 0.69 0.70 0.72 0.73 0.75 0.77 0.78 0.80 0.81 0.83 0.84 0.86 0.88 0.89 0.91 0.92 0.94 0.95 0.97 0.98 1.00 1.02 1.03 1.05 1.06 1.08 1.09 1.11 1.13 1.14 1.16 1.17 1.19 1.20 1.22 1.23 1.25 1.27 1.28 1.30 1.31 1.33 1.34 1.36 1.38 1.39 1.41 1.42 1.44 1.45 1.47 1.48 ML6411 CHANNEL REGISTER/BIT VALUES GAIN FACTOR A REGISTER D, BIT D1 = "BOOSTA" = 0 GSGCA = 1 REGISTER D, BIT D1 = "BOOSTA" = 1 GSGCA = 1.25 REGISTER D, BIT D2 = "BOOSTB" = 0 GSGCB = 1 REGISTER D, BIT D2 = "BOOSTB" = 1 GSGCB = 1.25 B Table 5. SGC Gain Mode CLAMP GATE SIGNAL CLAMP LEVEL OUTPUT CLAMP CURRENT 0 X X 0 1 00 OUT < 16 700µA 00 OUT > 16 –700µA 01 OUT < 64 700µA 01 OUT > 64 –700µA 10 OUT < 24 700µA 10 OUT > 24 –700µA 11 OUT < 128 700µA 11 OUT > 128 –700µA Table 6: Clamp Current for Various Clamp Levels 13 ML6411 REGISTER INFORMATION AND ORGANIZATION REGISTER ADDRESS A B C D E F 000 001 010 011 100 101 DATA BIT NAME DESCRIPTION A0 CLPA0 Sets Clamp Level for the A Channel See Table 3 A1 CLPA1 Sets Clamp Level for the A Channel See Table 3 A2 Reserved Reserved Don't Care A3 Reserved Reserved Don't Care A4 CLPB0 Sets Clamp Level for the B Channel See Table 3 B0 CLPB1 Sets Clamp Level for the B Channel See Table 3 B1 STDB0 Selects Standard Preset Gain Level for B Channel See Table 2 B2 STDB1 Selects Standard Preset Gain Level for B Channel See Table 2 B3 STDA0 Selects Standard Preset Gain Level for A Channel See Table 2 B4 STDA1 Selects Standard Preset Gain Level for A Channel See Table 2 C0 GNA0 Sets User Defined Gain Level for A Channel See Table 4 C1 GNA1 Sets User Defined Gain Level for A Channel See Table 4 C2 GNA2 Sets User Defined Gain Level for A Channel See Table 4 C3 GNA3 Sets User Defined Gain Level for A Channel See Table 4 See Table 4 C4 GNA4 Sets User Defined Gain Level for A Channel D0 GNA5 Sets User Defined Gain Level for A Channel D1 BOOSTA Provides 25% Extra Gain on A Channel 0 = 1 x Gain; 1 = 1.25 x Gain; See Table 5 D2 BOOSTB Provides 25% Extra Gain on B Channel 0 = 1 x Gain; 1 = 1.25 x Gain; See Table 5 D3 CV/S_Mode Select Dual Composite Mode or S-Video Mode D4 GNB0 Selects User Defined Gain Level for B Channel See Table 4 E0 GNB1 Sets User Defined Gain Level for B Channel See Table 4 E1 GNB2 Sets User Defined Gain Level for B Channel See Table 4 E2 GNB3 Sets User Defined Gain Level for B Channel See Table 4 E3 GNB4 Sets User Defined Gain Level for B Channel See Table 4 E4 GNB5 Sets User Defined Gain Level for B Channel See Table 4 Set to 0 for Proper Operation See Table 4 0 = S-Video Mode; 1 = Dual Composite Mode F0 Reserved F1 APEAK Sets A Channel for 1VP-P or 2VP-P inputs 1 = 1VP-P 0 = 2VP-P F2 BPEAK Sets A Channel for 1VP-P or 2VP-P inputs 1 = 1VP-P 0 = 2VP-P F3 CLKDIV Sets Internal Clock Frequency to Divide-by-2 1 = 1VP-P 0 = 2VP-P F4 Reserved Recommend 0 for RESET and 1 for Normal Operation Note: Volt Peak-to-Peak = VP-P Table 7: Control Register Summary 14 BIT CODE RANGE F0 = 0 0 or 1 is Acceptable ML6411 REGISTER INFORMATION AND ORGANIZATION REGISTER ADDRESS A B C D E F 000 001 010 011 100 101 DATA BIT NAME DESCRIPTION A0 CLPA0 Sets Clamp Level for the A Channel to 16 DEFAULT SETTING A1 CLPA1 A2 Reserved Reserved X A3 Reserved Reserved X A4 CLPB0 Sets Clamp Level for the B Channel to 128 X B0 CLPB1 Sets Clamp Level for the B Channel to 128 0 B1 STDB0 Selects Standard Preset Gain Level for B Channel (See Table 2) 0 B2 STDB1 Selects Standard Preset Gain Level for B Channel (See Table 2) 0 B3 STDA0 Selects Standard Preset Gain Level for A Channel (See Table 2) 0 B4 STDA1 Selects Standard Preset Gain Level for A Channel (See Table 2) 0 0 0 C0 GNA0 Sets User Defined Gain Level for A Channel (See Table 4) 0 C1 GNA1 Sets User Defined Gain Level for A Channel (See Table 4) 0 C2 GNA2 Sets User Defined Gain Level for A Channel (See Table 4) 0 C3 GNA3 Sets User Defined Gain Level for A Channel (See Table 4) 0 0 C4 GNA4 Sets User Defined Gain Level for A Channel (See Table 4) D0 GNA5 Sets User Defined Gain Level for A Channel (See Table 4) D1 BOOSTA Provides 25% Extra Gain on A Channel D2 BOOSTB Provides 25% Extra Gain on B Channel (See Table C) D3 CV/S_Mode D4 GNB0 Selects User Defined Gain Level for B Channel (See Table 4) 0 E0 GNB1 Sets User Defined Gain Level for B Channel (See Table 4) 0 E1 GNB2 Sets User Defined Gain Level for B Channel (See Table 4) 0 E2 GNB3 Sets User Defined Gain Level for B Channel (See Table 4) 0 E3 GNB4 Sets User Defined Gain Level for B Channel (See Table 4) 0 E4 GNB5 Sets User Defined Gain Level for B Channel (See Table 4) 1 Select Dual Composite Mode or S-Video Mode Set to 0 for Proper Operation 1 0 = 1 x Gain 0 = 1 x Gain 0 = S-Video Mode F0 Reserved F1 APEAK Sets A Channel for 1VP-P or 2VP-P inputs 0 = 2VP-P 0 F2 BPEAK Sets A Channel for 1VP-P or 2VP-P inputs 0 = 2VP-P F3 CLKDIV Sets Internal Clock Frequency to Divide-by-2 0 = CLK F4 Reserved Recommend 0 for RESET and 1 for Normal Operation 0 Note: X = Don't Care Note: Volt Peak-to-Peak = VP-P Table 8: RESET Control Valures of Control Register 15 ML6411 REGISTER INFORMATION AND ORGANIZATION DEVICE INFORMATION DEVICE ADDRESS: B5 REGISTOR ADDRESS BITS: RA <2:0> DATA BITS: <4:0>X CONTROL REGISTERS: REGISTER A ADDRESS RA <2:0> = <000> DATABITS A <4:0> X REGISTER A ADDRESS RA <2:0> = <000> MSB A4 A3 A2 A1 A0 X REGISTER B ADDRESS RA <2:0> = <001> REGISTER B ADDRESS RA <2:0> = <001> DATABITS B <4:0> X MSB B4 B3 B2 B1 B0 X REGISTER C ADDRESS RA <2:0> = <010> DATABITS C <4:0> X REGISTER C ADDRESS RA <2:0> = <010> MSB C4 C3 C2 C1 C0 X REGISTER D ADDRESS RA <2:0> = <011> DATABITS D <4:0> X REGISTER D ADDRESS RA <2:0> = <011> MSB D4 D3 D2 D1 D0 X REGISTER E ADDRESS RA <2:0> = <100> DATABITS E <4:0> X REGISTER E ADDRESS RA <2:0> = <100> MSB E4 E3 E2 E1 E0 X REGISTER F ADDRESS RA <2:0> = <101> DATABITS F <4:0> X REGISTER F ADDRESS RA <2:0> = <101> MSB F4 F3 F2 F1 F0 X X = DUMMY BIT FOR ACKNOWLEDGE Figure 1. Register Organization and Information 16 ML6411 TIMING CONTROL The ML6411 operates in master mode where all internal timing is derived from the clock input at the CLK pin. Figure 2 provides timing diagrams for both the Dual Composite and Y/C modes. Note that the REF OUT pin provides the internal timing to the REF IN pin. These pins are shorted together for normal operation. shown in Figure 1, there are six independent 5-bit registers in the Control Block. To load a register, the 3-bit address is loaded in first followed by the 5-bit data values and a dummy bit. This is a total of 9-bits to load a register with the last bit being a dummy bit. Note that all of the registers can be loaded in succession before the STOP condition is enabled. Serial Bus Timing. Figure 3 provides timing of serial bus mode. Figure 4 provides a detailed timing for device, register, and data insertion to the control registers. As SAMPLE N VIN The CLKDIV function provides an internal divide-by-2 clock. This function is enable via control register. SAMPLE N +1 SAMPLE N +2 SAMPLE N +3 SAMPLE N +4 tcph tds tcpl CLK S/H CHANNEL A SAMPLE HOLD SAMPLE HOLD SAMPLE HOLD SAMPLE HOLD SAMPLE HOLD SAMPLE HOLD SAMPLE HOLD S/H CHANNEL A SAMPLE HOLD SAMPLE HOLD SAMPLE HOLD SAMPLE HOLD SAMPLE HOLD SAMPLE HOLD SAMPLE HOLD OEC OEY Y<7:0> C<7:0> CV1<7:0> CV2<7:0> Yn -3 Cn -3 Yn -2 Cn -2 tod toe Yn -1 Cn -1 Yn Cn Yn +1 Cn +1 Yn +2 Cn +2 tho tdo Figure 2. Y/C and Dual CV Mode 17 ML6411 START SDATA tRISE tFALL All Other SDATA Transitions Must Occur While SCLK is Low tSET/START SCLK STOP START: A Falling Edge on the SDATA While SCLK is Held High STOP: A Rising Edge on the SDATA While SCLK is Held High Figure 3. Definition of START & STOP on Serial Data Bus START REGISTER ADDRESS DEVICE ADDRESS SDATA MSB AD7 MSB AD6 DATA FOR REGISTER A, B, C, D, E, OR F MSB AD1 AD0 X RA2 RA1 7 8 9 10 11 RA0 DATABIT 4 DATABIT 3 DATABIT 2 DATABIT 1 DATABIT 0 X 17 18 SCLK 0 1 2 12 13 14 15 16 STOP SCLK: 9th pulse strobes dummy bit for ACK STOP SCLK: Rising edge enables data transfer SCLK: 9th pulse strobes dummy bit for ACK SDATA: Value set to AD6, Device Address (MSB-1) SCLK: Rising edge enables data transfer SCLK: Falling edge disables data transfer SDATA: Value set to DATABIT 4, MSB of data SCLK: Rising edge enables data transfer SCLK: Falling edge disables data transfer SCLK: Rising edge enables data transfer SDATA: Value set to AD7, Device Address MSB SCLK: Falling edge in prep for first address transfer SDATA: Value set to RA3, MSB of Register Address SDATA; Falling edge with SCLK Hi means start of sequence Figure 4. Definition of ADDRESS and DATA FORMAT on Serial Data Bus 18 ML6411 APPLICATION 1: VIDEO EDITING SYSTEMS DIGITAL AUX INPUT Y/CV1 IN Y/CV2 IN ML6420 ANTI-ALIAS FILTER Y/CV1 OUT ML6411 DUAL A/D CONVERTER D/A ML6421 RECONSTRUCTION FILTER Y/CV2 OUT AUX OUT ML6431 GENLOCK DIGITAL VIDEO OUTPUTS Figure 5. Typical S-video and Composite Video Capture System 19 ML6411 APPLICATION 1: VIDEO EDITING SYSTEMS P2 / P19 P1 / P20 VCC C12 1µF C31 0.1µF P26 / P2 P27 / P33 C11 0.1µF JP16 J1 R6 470Ω R7 91Ω 1 2 3 4 5 6 7 8 9 10 11 12 P1 P0 GNDD VCCD C8 0.1µF P2/SDATa P3/SCLK SLEEP U6 VCCS ML6431 GNDS CVIN CVREF VSYNC VBLNK HRESET FRESET VCCB GNDB 1XCLK 2XCLK F ID 24 23 22 21 20 19 18 17 VCCA GNDA XTALIN XTALOUT FREERUN NOSIG LOCKED AUDIO 1 2 3 4 5 6 7 8 Y / P6 AUDIO CLK OUTPUT SCLAMP BCLAMP CSYNC HBLNK 32 31 30 29 28 27 26 25 1 3 5 7 9 11 13 15 C9 0.1µF C13 0.1µF C10 0.01µF 9 10 11 12 13 14 15 16 2 4 6 8 10 12 14 16 GND P18 / P14 JP7 C14 22nF P1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 X2 4.43MHz SERIAL BUS VIA PARALLEL PC PORT X1 3.58MHz R5 330Ω D1 R4 330Ω D2 Figure 6 (Page 1 of 3). Application Schematic Detailing Block Diagram of Figure 5 20 ML6411 Y / P6 C1 10µF Y/CV1 IN R1 75Ω AUX IN ML6420 C2 10µF 1 2 3 4 5 6 7 8 R24 3kΩ R2 75Ω C/CV2 IN C3 10µF GNDB VINB VINC VINA GND RANGE GNDC GNDA U5 VCC GND VCCC VCCA VOUTC VOUTA VCCB VOUTB 16 15 14 13 R21 12 3kΩ 11 10 9 R22 3kΩ 1µF FB3 C25 0.1µF C6 0.1µF C26 0.1µF C7 0.1µF C5 0.1µF +5VA VCC AVCC1 AVCC2 AVCC3 VCCO DVCC OEA VCC 35 38 41 15 17 23 12 L4 C27 0.1µF P26 / P2 P2 / P19 P1 / P20 36 44 42 2 19 20 P18 / P14 14 18 +5VD 32 33 P27 / P33 39 CLK RSET DVCC DGND VINN AOUT0 AOUT1 AOUT2 AOUT3 AOUT4 AOUT5 AOUT6 AOUT7 ML6411 U1 REF OUT REF IN B7 B6 B5 B4 B3 B2 B1 B0 24 25 26 27 28 29 30 31 Y7 / R7 Y6 / R6 Y5 / R5 Y4 / R4 Y3 / R3 Y2 / R2 Y1 / R1 Y0 / R0 22 21 10 9 8 7 6 5 4 3 B7 B6 B5 B4 B3 B2 B1 B0 PD OEB GNDO DGND AGND1 AGND2 AGND3 R23A 150Ω Y/CV1 REF1 C/CV2 CLAMP GATE SCLK SDAT 1 11 13 16 37 40 43 C32 0.1µF R19 1kΩ VCC C4 R3 R18 75Ω 1kΩ R20 1kΩ JP10 / P31 Figure 6 (Page 2 of 3). Application Schematic Detailing Block Diagram of Figure 5 21 ML6411 APPLICATION 1: VIDEO EDITING SYSTEMS VCC R14 499Ω C21 0.01µF L2 L3 C19 0.01µF C18 C16 47µF 0.02µF C17 47µF R16 150Ω Y7 / R7 Y6 / R6 Y5 / R5 Y4 / R4 Y3 / R3 Y2 / R2 Y1 / R1 Y0 / R0 R17 150Ω 44 43 42 41 40 39 38 37 36 35 34 R15 150Ω 1 2 3 4 5 6 7 8 9 10 11 C15 20nF QR VDR QR CAS QG VDG QG CAS QB VDB QB CV1/Y DIGITAL IREF VSSR R7 R6 R5 VSS VDD R4 R3 R2 R1 MC44200 U2 33 32 31 30 29 28 27 26 25 24 23 VREF VDDR CLK B0 B1 VSS VDD B2 B3 B4 B5 C22 47nF 8 7 6 5 4 3 2 1 12 13 14 15 16 17 18 19 20 21 22 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 8 7 6 5 4 3 2 1 C20 470nF L1 AUX DIGITAL C23 47nF B7 B6 B5 B4 B3 B2 B1 B0 JP21 / P31 R12 150Ω R11 150Ω 1 2 3 4 5 6 7 8 R13 150Ω C/CV2 DIGITAL C30 0.1µF C24 1µF ML6421 1 2 3 4 5 6 7 8 GNDB VINB VINC VINA GND RANGE GNDC GNDA U7 VCC GND VCC VCCA VOUTC VOUTA VCCB VOUTB FB4 16 15 14 13 12 11 10 9 VCC Y/CV1 OUT R10 75Ω AUX OUT R9 75Ω C/CV2 OUT R8 75Ω Figure 6 (Page 3 of 3). Application Schematic Detailing Block Diagram of Figure 5 22 ML6411 PHYSICAL DIMENSIONS inches (millimeters) Package: H44-14 44-Pin (14 x 14 x 1mm) TQFP 0.630 BSC (16.00 BSC) 0.551 BSC (14.00 BSC) 0º - 7º 0.003 - 0.008 (0.09 - 0.20) 34 1 PIN 1 ID 0.551 BSC (14.00 BSC) 0.630 BSC (16.00 BSC) 23 0.018 - 0.030 (0.45 - 0.75) 12 0.039 BSC (1.00 BSC) 0.014 - 0.020 (0.36 - 0.51) 0.048 MAX (1.20 MAX) SEATING PLANE 0.037 - 0.041 (0.95 - 1.05) 23 ML6411 ORDERING INFORMATION PART NUMBER ML6411 OUTPUT VOLTAGE TEMPERATURE RANGE PACKAGE 0°C to 70°C 44 Pin TQFP (H44) Micro Linear Corporation 2092 Concourse Drive San Jose, CA 95131 Tel: (408) 433-5200 Fax: (408) 432-0295 www.microlinear.com © Micro Linear 1999. their respective owners. is a registered trademark of Micro Linear Corporation. All other trademarks are the property of Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174; 5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999; 5,818,207; 5,818,669; 5,825,165; 5,825,223; 5,838,723; 5.844,378; 5,844,941. Japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. Other patents are pending. Micro Linear makes no representations or warranties with respect to the accuracy, utility, or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, express or implied, by estoppel or otherwise, to any patents or other intellectual property rights is granted by this document. The circuits contained in this document are offered as possible applications only. Particular uses or applications may invalidate some of the specifications and/ or product descriptions contained herein. The customer is urged to perform its own engineering review before deciding on a particular application. Micro Linear assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Micro Linear products including liability or warranties relating to merchantability, fitness for a particular purpose, or infringement of any intellectual property right. Micro Linear products are not designed for use in medical, life saving, or life sustaining applications. 24 DS6411-01