DF1750 ® Dual Channel DIGITAL DECIMATION FILTER FEATURES DESCRIPTION ● USER SELECTABLE FOR 1/4 OR 1/2 DECIMATING RATIOS ● USER SELECTABLE FOR 16- OR 18-BIT INPUT DATA The DF1750 is a high performance 1/4 or 1/2 decimating digital filter that is designed for digital audio applications. This device decimates and filters 2x or 4x (2fs or 4fs) oversampled data from the output of an ADC to a data frequency of fs. The technique of oversampling and decimating allows the input to an oversampling ADC to be processed by a much lower order, linear phase, analog low-pass filter. This simultaneously improves system performance while reducing circuit complexity and cost. ● SERIAL DATA INPUT IS COMPATIBLE WITH THE BURR-BROWN PCM1750 ADC ● FILTERS OUT-OF-BAND NOISE WITH STOPBAND ATTENUATION > 95dB ● PASSBAND RIPPLE < 0.0005dB ● SINGLE +5V SUPPLY OPERATION WITH LOW POWER DISSIPATION OF ONLY 250mW SCSL1 SCSL2 The DF1750 provides output data word rates (fs) up to 50.5kHz and it is compatible with the Burr-Brown PCM1750, dual 18-bit analog-to-digital converter. 2DS IBCK DINL DINR XTI XTO CKEN System Clock Input Interface Circuit Timing Control FIR Filter Circuit IMOD CKO CC BBC IBO TEST OW20 Output Interface Circuit LRCK WDCK BCK DOUT MUTE FSEN LRPOL OBPOL International Airport Industrial Park • Mailing Address: PO Box 11400 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1990 Burr-Brown Corporation PDS-1092 Printed in U.S.A. October, 1993 PIN CONFIGURATION Top View SOIC Top View DIP CKO 1 40 VDD1 CKO 1 28 VDD1 NC 2 39 CKEN SCSL1 2 27 CKEN SCSL1 3 38 (NC) SCSL2 3 26 XTO TEST 4 25 XTI SCSL2 4 37 XTO TEST 5 36 XTI 2DS 5 24 MUTE IMOD 6 23 DOUT (NC) 6 35 MUTE 2DS 7 34 (NC) VSS2 7 22 BCK DINR 8 21 VSS1 IMOD 8 33 DOUT (NC) 9 32 BCK CC 9 20 WDCK 10 19 OBPOL VSS2 10 31 (NC) BBC DINR 11 30 (NC) IBCK 11 18 LRPOL IBO 12 17 LRCK (NC) 12 29 VSS1 CC 13 28 WDCK DINL 13 16 FSEN VDD2 14 15 OW20 BBC 14 27 OBPOL (NC) 15 26 (NC) IBCK 16 25 LRPOL IBO 17 24 LRCK DINL 18 23 FSEN VDD2 19 22 (NC) (NC) 20 21 OW20 PIN DESCRIPTION PIN NO. DIP SOIC PIN NO. NAME I/O* DESCRIPTION DIP SOIC NAME I/O* DESCRIPTION 15 21 OW20 ip Output data bit select (16bit: OW20 = H, 20 bit: OW20 = L) I/O pin select (FSEN = H: BCK, WDCK, LRCK pin=Input (FSEN = L: BCK, WDCK, LRCK pin=Output) fs clock LRCK polarity select (LRPOL = H: Lch/Rch=Low/High) (LRPOL = L: Lch/Rch=High/Low) 1 1 CKO o Clock output (the same as XTI frequency), CKO = L when CKEN = H – 2 2 3 (NC) SCSL1 ip XTI Frequency select – 16 22 23 (NC) FSEN ip 3 4 4 5 SCSL2 TEST ip ip (Refer to XTI pin description) Test, (Test = L; test mode) 17 18 24 25 LRCK LRPOL ip ip – 5 6 7 (NC) 2DS – 26 (NC) ip 6 – 7 8 – 9 8 9 10 11 12 13 IMOD (NC) VSS2 DINR (NC) CC ip ip 1/4 or 1/2 decimating select 2DS = H: 1/4 decimating, 2DS = L: 1/2 decimating A/D converter interface mode select o A/D converter control signal OBPOL WDCK VSS1 (NC) (NC) BCK DOUT BCK polarity select 2fs clock GND 1 GND 2 Rch input data 27 28 29 30 31 32 33 ip ip/o – – ip 19 20 21 – – 22 23 ip/o o Output data bit clock Data output (Lch or Rch serial data output). 10 – 14 15 BBC (NC) o A/D converter control signal – 24 25 34 35 36 (NC) MUTE XTI ip i 11 16 IBCK ip Input data bit clock input 12 13 14 – 17 18 19 20 IBO DINL VDD2 (NC) o ip – Input data bit clock output Lch input data +5V 26 – 27 28 37 38 39 40 XTO (NC) CKEN VDD1 *i = Input pin ip = Input with pull-up resistor o = Output pin ® DF1750 2 o ip – Data output mute, (MUTE = L: DOUT = L) Oscillator Input (512fs: SCSL1 = H, SCSL2 = H) (256fs: SCSL1 = H, SCSL2 = L) (768fs: SCSL1 = L, SCSL2 = H) (384fs: SCSL1 = L, SCSL2 = L) Oscillator Output CKO output select, (CKEN = H, CKO = L) +5V ip/o = Input with pull-up resistor when FSEN = H, output with FSEN = L. ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS Supply Voltage (VDD) .......................................................... –0.3V to +7.0V Input Voltage (VIN) ...................................................... –0.3V to VDD + 0.3V Soldering Temperature .................................................................. +255°C Soldering Time ...................................................................................... 10s Storage Temperature ...................................................... –40°C to +125°C Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Burr-Brown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. PACKAGE INFORMATION MODEL DF1750P DF1750U PACKAGE PACKAGE DRAWING NUMBER(1) 28-Pin Plastic DIP 40-Pin Plastic SOIC 215 252 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. DC SPECIFICATIONS ELECTRICAL VDD = 4.5V to 5.5V, VSS = 0V, TA = –20°C to +80°C unless otherwise specified. DF1750P/U PARAMETER INPUTS Logic Family Logic Voltages PIN SYMBOL CONDITION XTI XTI XTI VIL1 VIH1 VCLK VIL2 VIH2 IIL1 IIH1 IIL2 ILH1 For Clock Input For Clock Input For AC Coupling FSEN = H FSEN = H VIN = 0V VIN = VDD VIN = 0V, FSEN = H VIN = VDD, FSEN = H VOL VOH IOL = 1.6mA, FSEN = L IOH = –0.4mA, FSEN = L VDD1, V DD2 IDD PD VDD = 5V(4), FSEN = H Nominal VDD (1),(2) XTI XTI (1),(2) Input Leakage Current (1),(2) OUTPUTS Logic Family Logic Voltages (2),(3) MAX UNIT 0.3VDD 10 10 20 1.0 V V VP-P V V µA µA µA µA 0.4 V 30 250 V mA mW +80 +80 °C °C 0.7VDD 1.8 0.5 2.4 5 5 10 CMOS (2),(3) POWER SUPPLY REQUIREMENTS Supply Voltage Supply Current Power Dissipation TYP CMOS (1),(2) Logic Currents MIN 2.5 +5 TEMPERATURE RANGE (AMBIENT, TA) Specification Operating –20 –20 NOTES: (1) Refers to pins SCSL1, SCSL2, TEST, 2DS, IMOD, DINR, IBCK, DINL, OW20, MUTE, OBPOL, LRPOL, FSEN, CKEN. (2) Refers to pins BCK, WDCK, LRCK. (3) Refers to pins CKO, CC, BBC, IBO, DOUT. (4) Test Condition; SCSL1 = H, SCSL2 = H, TEST = H, 2DS = H, IMOD = H, OW20 = H, MUTE = H, OBPOL = H, LRPOL = H, FSEN = L, CKEN = L. TCY = 38ns (XTI Clock Period), CL= 0pF (Capacitive Load), DINL, DINR (Applicable Input Data). The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 DF1750 AC SPECIFICATIONS ELECTRICAL VDD = 4.5V to 5.5V, VSS = 0V, TA = –20°C to +80°C unless otherwise specified. XTI Clock CONDITION PARAMETER Crystal Oscillator Frequency External Clock Pulse Width DF1750P/U SCSL1 SCSL2 FREQ MIN FOSC H H L L H L H L 512fs(1) 256fs 768fs 384fs H H L L H L H L H H L L H L H L tCW External Clock Pulse Period SYS SYMBOL tCY TYP MAX UNIT 8 4 12 6 26 13 26 20 MHz MHz MHz MHz 512fs 256fs 768fs 384fs 15 38 15 25 70 140 50 100 ns ns ns ns 512fs 256fs 768fs 384fs 38 77 38 50 125 250 84 167 ns ns ns ns VIH1 1/2VDD XTI VIL1 tCW tCW tCY AC Coupling is required with an external clock. NOTE: (1) fs = Sampling frequency. ADC CONTROL SIGNAL TIMING (CC, BBC, AND IBO) WITH IMOD = H DF1750P/U PARAMETER 2DS = H CC Pulse Width (H) S/H Acquisition Time CC-BBC Time BBC Pulse Period BBC Pulse Width (H) BBC Pulse Width (L) BBC-IBO Time IBO Pulse Period IBO Pulse Width (H) IBO Pulse Width (L) SYMBOL MIN TYP T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 65 670 285 228 65 140 140 228 140 65 1/256fs 9/256fs 4/256fs 3/256fs 1/256fs 2/256fs 2/256fs 3/256fs 2/256fs 1/256fs MAX UNIT ns ns ns ns ns ns ns ns ns ns T1 1.5V CC T4 T2 T3 T5 1.5V BBC T6 T7 2DS = L CC Pulse Width (H) S/H Acquisition Time CC-BBC Time BBC Pulse Period BBC Pulse Width (H) BBC Pulse Width (L) BBC-IBO Time IBO Pulse Period IBO Pulse Width (H) IBO Pulse Width (L) T8 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 130 1350 570 456 130 280 280 456 280 130 1/256fs 9/256fs 4/256fs 3/256fs 1/256fs 2/256fs 2/256fs 3/256fs 2/256fs 1/256fs ns ns ns ns ns ns ns ns ns ns ® DF1750 4 T9 1.5V IBO T10 SERIAL INPUT TIMING (IBCK, DINL, DINR) WITH IMOD=H DF1750P/U PARAMETER SYMBOL MIN TYP MAX UNIT tIBW tIBY tSL 50 3/12.928MHz(1) 50 1/256fs 3/256fs tHL 50 ns tSD 25 ns 2DS = H IBCK Pulse Width IBCK Pulse Period Data Word Latch Set-up Time Data Word Latch Hold Time DINL, DINR Set-up Time DINL, DINR Hold Time ns ns ns 1.5V CC tSL t HL tHD 25 1.5V IBCK t IBW ns t IBW t IBY t HD tSD 2DS = L IBCK Pulse Width IBCK Pulse Period Data Word Latch Set-up Time Data Word Latch Hold Time DINL, DINR Set-up Time DINL, DINR Hold Time tIBW tIBY tSL 50 3/12.928MHz(1) 50 tHL 50 ns tSD 25 ns tHD 25 ns 1/128fs 3/128fs ns ns ns DINL DINR 1.5V Normally, IBO output is connected to IBCK (Refer to the applications diagram). NOTE: (1) 12.928MHz = 256 x 50.5kHz (max sampling frequency). ADC CONTROL SIGNAL TIMING (CC, BBC, AND IBO) WITH IMOD = L DF1750P/U PARAMETER SYMBOL MIN TYP MAX UNIT 2DS = H CC Pulse Width (H) BBC Pulse Width BBC Pulse Period IBO Pulse Width IBO Pulse Period CC-BBC Time CC-IBO Time BBC-IBO Time t CCW tCCW tBBW tBBY tBOW tBOY tCCBB tCCBO tBBBO 130 130 -5 130 130 1/8fs 1/128fs 1/64fs 1/128fs 1/64fs 0 1/128fs 1/128fs ns ns ns ns ns ns ns ns 20 CC 1.5V tBBY tBBW 1.5V tBOW tCCW tBBW tBBY tBOW tBOY tCCBB tCCBO tBBBO 280 280 –5 280 280 1/4fs 1/64fs 1/32fs 1/64fs 1/32fs 0 1/64fs 1/64fs ns ns ns ns ns ns ns ns 20 t CCBB tBBW BBC 2DS = L CC Pulse Width (H) BBC Pulse Width BBC Pulse Period IBO Pulse Width IBO Pulse Period CC-BBC Time CC-IBO Time BBC-IBOTime t CCW tBOY tBBBO t CCBO IBO 1.5V tBOW ® 5 DF1750 SERIAL INPUT TIMING (IBCK, DINL, DINR) WITH IMOD = L DF1750P/U PARAMETER SYMBOL MIN TYP MAX UNIT tIBW tIBY tSL 100 1/3.232MHz(1) 50 1/128fs 1/64fs tHL 50 ns tSD 25 ns 2DS = H IBCK Pulse Width IBCK Pulse Period Data Word Latch Set-up Time Data Word Latch Hold Time DINL, DINR Set-up Time DINL, DINR Hold Time ns ns ns 1.5V CC t HL tSL 1.5V IBCK t IBW tHD 25 ns t IBW t IBY t HD tSD 2DS = L IBCK Pulse Width IBCK Pulse Period Data Word Latch Set-up Time Data Word Latch Hold Time DINL, DINR Set-up Time DINL, DINR Hold Time tIBW tIBY tSL 100 1/3.232MHz(1) 50 tHL 50 ns tSD 25 ns tHD 25 ns 1/64fs 1/32fs DINL DINR ns ns ns 1.5V Normally, IBO output is connected to IBCK. (Refer to the application diagram). NOTE: (1) 3.232MHz = 64 x 50.5kHz (max sampling frequency). SERIAL OUTPUT TIMING WITH FSEN = H DF1750P/U PARAMETER SYMBOL BCK Pulse Width BCK Pulse Period LRCK Pulse Width LRCK Pulse Period LRCK Set-up Time LRCK Hold Time Output Data Hold Time Output Data Delay Time tBCW tBCY tLCW tLCY tBL tLB tH MIN TYP MAX 100 1/128fs 1/3.232MHz(1) 1/64fs 1/2fs 1/50.5kHz 1/fs 50 50 0 tD UNIT ns ns µs µs ns ns ns 100 REMARKS LRCK 1.5V tBL tLB Duty = 50% 1.5V BCK (OBPOL = H) CL = 0pF ns tBCW tBCW tBCY t H, t D CL = 15pF 1.5V DOUT NOTE: (1) 3.232MHz = 64 x 50.5kHz (max sampling frequency). SERIAL OUTPUT TIMING WITH FSEN = L DF1750P/U PARAMETER SYMBOL BCK Pulse Width BCK Pulse Period WDCK Pulse Width WDCK Pulse Period LRCK Pulse Width LRCK Pulse Period Output Data Delay Time tOBCW tOBCY tWDCW tWDCY tLRCW tLRCY tDHL tDLH MIN 140 –10 –10 TYP MAX 1/128fs 1/64fs 1/4fs 1/2fs 1/2fs 1/fs 30 30 UNIT ns ns µs µs µs µs ns ns (OBPOL =H) t OBCW t OBCW tOBCY t DHL LRCK WDCK DOUT ® DF1750 1.5V BCK 6 t DLH 1.5V THEORY According to the Nyquist Theorem, digital audio recordings sampled at a rate of 44.1kHz (CD) or 48kHz (DAT) should accurately reproduce the full 20kHz audio bandwidth. Unfortunately, if frequencies higher than1/2 the sample rate are seen at the input of an analog-to-digital converter, aliasing back into the baseband will occur. At these sample frequencies, the way to assure that aliasing does not occur is to use complicated high order filters at the input of the ADC . These filters can be expensive and they can also have undesirable phase characteristics. These problems can be avoided by using an oversampling ADC (such as the PCM1750) with a decimating filter, where a high order filter can be replaced with a low order filter which has very little phase distortion (Figure 1). 0 2 Analog Filter 3.0 4.0 x fs 1.0 2.0 3.0 4.0 x fs Foldover Noise 1.0 2.0 3.0 Foldover Noise Foldover Noise 1.0 2.0 3.0 4.0 x fs Foldover Noise Foldover Noise Signal 4.0 x fs 0 1.0 2.0 3.0 4.0 x fs Signal F/N F/N F/N F/N 0 1.0 2.0 3.0 4.0 x fs A/D (g) 1st LPF 4.0 x fs Foldover Noise Signal 0 (f) 2.0 Signal 0 (e) 1.0 Signal 0 (d) 3.0 Band limited by the analog filter. 0 (c) 2.0 3 Sampling 4 1.0 (b) With the oversampling-decimating technique, the input signal (Figure 2a) is band limited by a low order analog low-pass filter as shown in Figure 2b. This signal is 4-times oversampled, with its spectra and foldover noise shown in Figure 2c. The DF1750 first rejects the high frequency components of the 4fs ADC output (Figure 2d). A 1/2 decimating filter then processes this data into a 2fs data stream. This output spectra is shown in Figure 2e. The high frequency components of the 2fs data are then removed, producing the output spectra shown in Figure 2f. A second 1/2 decimating filter processes the 2fs data to a final fs data stream and the original signal is restored without distortion (Figure 2g). Note, when operating in the 1/2 decimating mode the DF1750 processes data through the first LPF and a single 1/2 decimating filter only. 1 Signal (a) 1st 1/2 Decimating 5 2nd LPF 6 2nd 1/2 Decimating 7 FIGURE 2. The Associated Spectra of the OversamplingDecimating Technique. FIGURE 1. A Block Diagram of an Oversampling ADC Followed by Digital Decimation. ® 7 DF1750 THEORETICAL FILTER CHARACTERISTICS 1/4 DECIMATING, INPUT DATA FREQUENCY = 4fs 1/2 DECIMATING, INPUT DATA FREQUENCY = 2fs PARAMETER CHARACTERISTICS PARAMETER CHARACTERISTICS Passband Stopband Passband Ripple Stopband Attenuation DC to 0.4583fs 0.5417fs and Above ±0.0005 dB 95dB min, 0.5417fs to 1.4583fs 88dB min, 1.4583fs to 2.5417fs 95dB min, 2.5417fs to 3.4583fs Constant, Linear Phase Passband Stopband Passband Ripple Stopband Attenuation Group Delay Time DC to 0.4583fs 0.5417fs and above ±0.0002dB 95dB min, 0.5417fs to 1.4583fs Constant, Linear Phase Group Delay Time 0 0 20 Attenuation (dB) Attenuation (dB) 20 40 60 60 80 80 100 100 0.5 1 2 3 0.5 4 (x fs) DF1750 1/4 Decimating Filter Tranfer Characteristics. 1 1.5 2 (x fs) DF1750 1/2 Decimating Filter Transfer Characteristics. —0.001 Attenuation (dB) —0.001 Attenuation (dB) 40 —0.0005 0 —0.0005 0 0.0005 0.0005 0.001 0.001 0.1 0.2 0.3 0.1 0.4 0.45 0.2 0.3 0.4 (x fs) DF1750 1/2 Decimating Passband Frequency Response. 0 0 20 20 Attenuation (dB) Attenuation (dB) DF1750 1/4 Decimating Passband Frequency Response. 0.45 (x fs) 40 60 80 100 40 60 80 100 0.5 0.55 0.6 0.5 (x fs) 0.6 (x fs) DF1750 1/4 Decimating Transitionband Frequency Response. DF1750 1/2 Decimating Transitionband Frequency Response. ® DF1750 0.55 8 FUNCTIONAL DESCRIPTION 1/4 AND 1/2 DECIMATING FUNCTIONS 1/4 or 1/2 decimating filtering converts 4fs or 2fs oversampled data back to a sampling rate of fs data by a digital filtering algorithm. 2DS is used to select 1/4 or 1/2 decimating. 1 WORD IBCK DINL DINR 2DS = H; 1/4 decimating (0.5417fs ~ 3.4583fs) 2DS = L; 1/2 decimating (0.5417fs ~ 1.4583fs) MSB 2 3 14(16)15(17) LSB SIPO Loading Timing The filter arithmetic block consists of two 1/2 decimating finite impulse response (FIR) filters as shown in Figure 3. 2fs INPUT The numbers in the parenthesis in the DINL and DINR waveforms are applicable to the 18-bit input mode. 2nd FIR 2fs 1/2 Decimating fs OUTPUT Filter (141 Taps) 1st FIR 1/2 Decimating Filter (21 Taps) Latch Timing FIGURE 4. SIPO Input Data Loading Timing. 4fs 2DS (1) IMOD = H FIGURE 3. Filter Arithmetic Structure CC SYSTEM CLOCK The system clock frequency can be 256fs, 364fs, 512fs, or 768fs selectable with SCSL1 and SCSL2 as indicated in Table I. An external clock (applied to Pin XTI) or crystal oscillator (Pins XTI and XTO) can be employed. AC coupling is required for an external clock. The XTI input clock is available as an output at pin CKO, when CKEN = L. CKO stays low when CKEN = H. DINL L1 L2 L3 L4 DINR R1 R2 R3 R4 LATCH (L) LOADING L1 L2 L3 L4 LATCH (R) LOADING R1 R2 R3 R4 (2) IMOD = L CC SCSL1 H SCSL2 XTI Clock Frequency FXI Clock Input Internal System Clock Frequency L H L H L 512fs 256fs 768fs 384fs External Clock or Crystal Oscillator FSYS DINL L1 L2 L3 L4 DINR R1 R2 R3 R4 LATCH (L) LOADING L1 L2 L3 L4 LATCH (R) LOADING R1 R2 R3 R4 256fs TABLE I. System Clock and Internal Clock Frequency Selection. FIGURE 5. Input Data Latch/Loading Timing. SERIAL DATA INPUT The DF1750 is programmed for accepting the correct number of input data bits per word by the IMOD pin. A 16-bit input word is selected with IMOD = L and an 18-bit input word is selected with IMOD = H. Set IMOD = H for use with the PCM1750. The serial input data format is two's complement and MSB first. Both the left and right channel data are loaded into the DF1750 simultaneously. Each bit of the data is loaded to each channel’s SIPO (Serial/ parallel conversion register) by the rising edge of the Input Bit Clock, IBCK (Figure 4). After the serial input data is loaded, the data is latched into a parallel register by the rising edge of CC for IMOD = H and the falling edge of CC for IMOD = L (Figure 5). ® 9 DF1750 ADC CONTROL SIGNALS (CC, BBC, AND IBO) WITH IMOD = H (1) 1/4 Decimating (2DS = H) (1/4fs) 31 0 1 2 3 4 5 25 30 31 0 1 30 31 0 1 (128fs) BBC 1 CC (SOUTL) DINL 2 2 MSB (SOUTL) DINR IBO (2) 1/2 Decimating 15 3 3 16 15 17 16 17 18 19 LSB (2DS = L) (1/2fs) 31 0 1 2 3 4 25 5 (64fs) BBC 1 CC (SOUTL) DINL 2 2 MSB (SOUTL) DINR IBO 15 3 3 15 16 17 16 17 18 19 LSB (SOUTL) (SOUTR) are outputs of the PCM1750. FIGURE 6. ADC Control Signals With IMOD = H. (Applicable for use with the Burr-Brown PCM1750 ADC). b. Sampling rate clock (LRCK) When FSEN = H, apply a 50% duty cycle sampling frequency (fs) to pin LRCK. When FSEN = L, a fs clock generated from the system clock is available at pin LRCK. ADC CONTROL SIGNALS (CC, BBC AND IBO) WITH IMOD = L (1) 1/4 Decimating 15 (2DS = H) 1 0 2 (1/4fs) 12 13 14 15 (64fs) c. Word Clock (WDCK) When FSEN = L, WDCK provides a 2fs clock that is derived from the system clock. BBC IBO CC DINL DINR MSB 2 3 (2) 1/2 Decimating 15 15 d. Output bit clock When FSEN = H, apply a 64fs clock to pin BCK. When FSEN = L, a 64fs clock generated from the system clock is available at pin BCK. LSB (2DS = L) 1 0 14 2 (1/2fs) 12 13 14 15 e. LRCK polarity selection (LRPDL) LRPOL = H; Lch/Rch = Low/High LRPOL = L; Lch/Rch = High/Low (Regardless of LRCK’s I/O mode). (32fs) BBC IBO CC DINL DINR MSB 2 3 14 15 f. BCK polarity selection (OBPOL) OBPOL = H; DOUT changes state at rising edge of BCK. OBPOL = L; DOUT changes state at falling edge of BCK. (Regardless of BCK’s I/O mode). LSB FIGURE 7. ADC Control Signals with IMOD = L. OUTPUT INTERFACE (BCK, WDCK, LRCK, OBPOL, LRPOL, FSEN) The output of the DF1750 can be interfaced to many different devices by programming the output interface pins. These pins provide the following functions: g. Timing relation between XTI and BCK, WDCK, LRCK clocks. When FSEN = H, clocks to BCK and LRCK must be synchronized to XTI. However, there is no limit on their phase differences (between XTI and BCK, LRCK clocks). a. Output control clocks, BCK, WDCK, LRCK I/O selection (FSEN). FSEN = H; BCK WDCK, LRCK = Input FSEN = L; BCK WDCK, LRCK = Output ® DF1750 10 SERIAL DATA OUTPUT The number of bits per output data word is selected with the OW20 pin. With OW20 = H a 16-bit output is selected and with OW20 = L a 20-bit output is selected. The serial output data format is two's complement and MSB first. The left and right channel outputs are alternated, with the left channel preceding the right channel. Each data word is allocated in each pulse of LRCK and the LSB is located at the end of the LRCK pulse as shown in Figure 8. The output of the DF1750 can be muted by the use of the MUTE pin. When MUTE = L, the output stays low (muted). Under normal operation MUTE = H. LRCK (LRPOL = H) Lch WORD MSB DOUT Rch WORD LSB MSB LSB FIGURE 8. Output Timing. TIMING DIAGRAMS INPUT 1/4 decimating (2DS = H) IMOD = H 1/2fs 1/4fs 128 1 INTERNAL CLOCK (128fs) 16 8 24 40 32 48 56 64 CC BBC IBCK DINL DINR INVALID 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 INVALID 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 NOTE: Bit 1 is the most significant bit. 1/4 decimating (2DS = H) IMOD = L 1/2fs 1/4fs CC BBC (64fs) IBCK (64fs) DINL DINR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NOTE: Bit 1 is the most significant bit. ® 11 DF1750 1/2 decimating (2DS = L) IMOD = H 1/2fs INTERNAL 64 1 CLOCK (64fs) 8 16 24 32 CC BBC IBCK DINL DINR INVALID 1 2 3 4 5 6 8 7 9 10 11 12 13 15 14 16 17 18 INVALID NOTE: Bit 1 is the most significant bit. 1/2 decimating (2DS = L) IMOD = L 1/2fs CC BBC (32fs) IBCK (32fs) DINL 1 2 3 DINR 4 5 6 7 8 9 10 11 12 13 14 15 16 NOTE: Bit 1 is the most significant bit. OUTPUT LRCK (LRPOL = H) (LRPOL = L) WDCK BCK (64fs) 64 1 8 16 24 32 40 48 56 64 (OBPOL = H) (OBPOL = L) DOUT LSB 16 MSB 1 Lch MSB 1 LSB 16 Rch LSB 16 (OW20 = H) LSB 20 MSB 1 Lch LSB 20 MSB 1 Rch LSB 20 (OW20 = L) APPLICATIONS PCM1750 by the DF1750. The 4fs oversampled data of the PCM1750 is filtered by the DF1750 to provide a data stream of fs. A PCM1750/DF1750 evaluation board, DEM1133, is available from Burr-Brown. This board incorporates the features mentioned above as well as an AES/EBU interface, test points for monitoring both the serial and parallel data outputs, and a breadboard area for user experimentation. A typical circuit configuration for digital audio recording is shown in Figure 9. Each of the stereo input channels passes through a six pole Generalized Immittance Converter (GIC) low pass analog filter. This filter features extremely low distortion and negligible phase shift. The band limited signals are 4x oversampled by the dual-channel PCM1750 A/D converter. Clock and convert signals are provided to the ® DF1750 12 ® 13 DF1750 A1* 5 A4* 5 A4* 1 1 7 3.92kΩ A6* 5 6 7.32k Ω 7.32k Ω 1 3.92k Ω 5 6 7.32kΩ 7.32kΩ A3* A5* 1000pF 3 2 7 1 A3* 1000pF 3.48k Ω 1000pF 2 3 A6* 1000pF 1.33kΩ 1000pF 3.48k Ω 1000pF 2 3 1000pF 1 5 6 1 1.33k Ω A5* 5 6 7 A2* *A1 – A2 = 1/2 OPA2604 with ±15V supplies or 1/2 5532 with ±5V. 1000pF 3.48k Ω 1000pF 2 3 1.33k Ω A1* A2* 1000pF 3 2 7 25k Ω 150Ω 150Ω 0.01µF 10 µF 0.1µ F 10 µF 25k Ω 47k Ω 150k Ω 0.01µ F 47k Ω 0.01µ F 220pF 220pF 0.01µF 47k Ω + + 150k Ω 47kΩ AGND 28 OFF ADJ 27 MSB ADJ 26 VINL DGND 10Ω 10Ω +5V + -5V 10µF + 10µF -VA 1 +VA 2 SOUTL 3 CLK 4 +VD 5 24 VREF OUT 25 VREF IN +VD 6 +VD 7 DCOM 8 ACOM 9 DCOM 10 CONVERT 11 SOUTR 12 +VA 13 -VA 14 23 ACOM 22 REF COM 21 REF CAP 20 ACOM 19 VREF OUT 18 VREF IN 17 VINR 16 MSB ADJ 15 OFF ADJ PCM1750P +5V CC DINR VSS2 IMOD 2DS TEST SCSL2 SCSL1 CKO 14 VDD2 13 DINL 12 IBO 11 IBCK 10 BBC 9 8 7 6 5 4 3 2 1 OW20 FSEN LRCK LRPOL OBPOL WDCK VSS1 BCK DOUT MUTE XTI XTO CKEN VDD1 DF1750P (28-PIN DIP PKG) 15 16 17 18 19 20 21 22 23 24 25 26 27 28 10pF +5V Interleaved Digital Output 10pF 16.9344 MHz 1.00M Ω FIGURE 9. Circuit diagram for a typical digital audio application using the DF1750 for decimating oversampled data from the output of the PCM1750 dual channel ADC. The OPA2604s are configured in a generalized immittance converter (GIC) filter arrangement to avoid aliasing in the PCM1750. 7 6 7.32k Ω 7.32kΩ 3.92kΩ 1000pF 3.48k Ω 1000pF 6 Left Channel Analog Input 7 2 7.32kΩ 1.33k Ω 3 7.32kΩ 3.92kΩ Right Channel Analog Input 25k Ω 25kΩ