TPPM0115 SWITCH MODE SYNCHRONOUS BUCK CONTROLLER SLVS371A– MARCH 2001 – REVISED JUNE 2001 SO (D) PACKAGE (TOP VIEW) features D DC-DC Synchronous Buck Controller D Switching Frequency, 200 kHz (Typ) D Programmable Output Voltage, D D D 1 V to 2.5 V ± 2% Power Good Function (PWRGD) Input Voltage, 12 V ±5% Drive High Load Current With External Components VCC PWRGD NC PHASE 1 8 2 7 3 6 4 5 GND SEN DRVL DRVH NC – No internal connection applications D PC Motherboard, Voltage Regulation for D D D System Power DDR Memory Supply (VDDQ or VTT) RDRAM Memory Supply (VDDQ) General Purpose Synchronous Switch Mode Controller description The TPPM0115 is a synchronous buck controller capable of driving two external power FETs 180° out of phase. The device requires a minimum of external standard filter components and switching FETs to regulate the desired output voltage. This is achieved with an internal switching frequency of 200 kHz (typical). The TPPM0115 switch mode controller and associated circuitry provide efficient voltage regulation of greater than 85%. The output voltage is set by two external resistors. During power up, when the output voltage reaches 90% of the desired value, the power good (PWRGD) output is transitioned high after a short delay of 1 ms to 5 ms. During power down, when the output voltage falls below 90% of the set value, the PWRGD output is pulled low without any delay. In the event the set output is in an over-voltage condition due to a system fault, the drive to the lower FET turns on to correct the fault. There is a dead time between switching one FET ON while the other FET is switching OFF to prevent cross conduction. The TPPM0115 is capable of driving high static load currents with minimal ripple on the output (<2%). The phase sense input is used to sense the flow of current through the inductor during flyback to minimize ripple on the output. To optimize output filter capacitance, the voltage mode control is based on a fixed ON time during the start of the cycle and hysteretic control during load transients. This allows the device to respond and maintain the set regulation voltage. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2001, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TPPM0115 SWITCH MODE SYNCHRONOUS BUCK CONTROLLER SLVS371A– MARCH 2001 – REVISED JUNE 2001 functional block diagram VCC DRVH Gate Drive Control DRVL Logic + _ Voltage Reference PHASE GND + _ PWRGD + _ Power Good Control PWRGD Ref Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION DRVH 5 O Output for upper FET gate drive DRVL 6 O Output for lower FET gate drive GND 8 O Ground NC/ TEST 3 O No connection, used for test purpose only PHASE 4 I Phase sense input PWRGD 2 O Open-drain output for power good function SEN 7 I Sense input VCC 1 I Input voltage 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1-V Ref SEN TPPM0115 SWITCH MODE SYNCHRONOUS BUCK CONTROLLER SLVS371A– MARCH 2001 – REVISED JUNE 2001 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Unregulated input voltage, VCC (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 V Drive output voltage, V(DRVH) and V(DRVL) (see Notes 1 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V Power good voltage, V(PWRGD) (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Feedback voltage, V(SEN) (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Phase sense voltage, V(PHASE) (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Continuous power dissipation, PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.4 W Electrostatic discharge susceptibility, V(HBMESD) (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV Operating ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature (soldering, 10 sec) TLEAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to GND. 2. Absolute negative voltage values on these terminals should not be below – 0.5 V. 3. Absolute negative voltage values on these terminals should not be below –1 V. 4. The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each terminal. recommended operating conditions MIN Unregulated input voltage, VCC NOM 11.4 Drive output current, I(DRVH) and I(DRVL) MAX 12.6 500 UNIT V mA Power good voltage, V(PWRGD) 5 V Feedback voltage, V(SEN) 1 V Phase sense voltage, V(PHASE) 0 Continuous power dissipation, PD Operating ambient temperature, TA POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V 100 mW 55 °C 3 TPPM0115 SWITCH MODE SYNCHRONOUS BUCK CONTROLLER SLVS371A– MARCH 2001 – REVISED JUNE 2001 dc electrical characteristics, TA = 0°C to 55°C, VCC = 12 V (unless otherwise noted) PARAMETER VOUT Output voltage η Efficiency IQ Quiescent current ∆VO(∆IO) ∆VO(∆VI) Load regulation TEST CONDITIONS MIN VCC = 11.4 V to 12.6 V, IL = 5 A to 10 A, See Figure 8 for external components, R1 = 0, R2 is not present Line regulation TYP MAX 1 IL = 10 A, See Figure 8 V(SEN) = < 1 V or >1.3 V, VOUT = 1 V to 1.3 V 86% See Figure 8 –1% 1% UNIT V 2 mA 1% Temperature regulation VOH(DRVH) VOL(DRVH) VOH(DRVL) VOL(DRVL) IIH IIL Upper drive output voltage Lower drive out output ut voltage Phase input current V(PWRGD) Sense out output ut voltage for PWRGD detection range IBIAS Sense feedback bias current V(SEN) = 0.9 V, V(SEN) = 1.2 V, IOH = 200 mA IOL = – 200 mA V(SEN) = 1.2 V, V(PHASE) < 0 V IOH = 200 mA V(SEN) = 0.9 V, V(SEN) = 0.9 V, IOL = – 200 mA V(PHASE) = 5 V VCC–3V 1 5 V V 1 100 µA A V(SEN) = 1.2 V, V(PHASE) = – 0.3 V Ramp up sense input until PWRGD transition to high –50 VOUT* 0.86 VOUT* 0.96 Ramp down sense input until PWRGD transition to low VOUT* 0.63 VOUT* 0.71 V(SEN) = 1.08 V 5 V µA ac electrical characteristics, TA = 0°C to 55°C, VCC = 12 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN Measured at DRVH terminal TYP fsw Switching frequency V(SEN) → 1.1 V to 0.9 V V(SEN) → 0.9 V to 1.1 V 50 tr V(DRVH) → 0 V to 8 V, Output rise time for both DRVH and DRVL V(DRVL) → 0 V to 8 V, Output fall time for both DRVH and DRVL V(DRVH) → 8 V to 0 V, V(DRVL) → 8 V to 0 V, V(SEN) → 0.9 V to 1.1 V V(SEN) → 1.1 V to 0.9 V 50 tf td Power good signal delay Delay time for V(SEN) > V(PWRGD) to PWRGD transitioning high tdt Dead time between DRVH and DRVL switch conduction MAX 200 kHz ns 50 ns 50 1 5 V(SEN) → 1.1 V to 0.9 V, Delay between V(DRVL) at 0 V and V(DRVH) = 1.5 V 50 V(SEN) → 0.9 V to 1.1 V, Delay between V(DRVH) at 0 V and V(DRVL) = 1.5 V 50 UNIT ms ns thermal characteristics MIN RθJC Thermal impedance, junction-to-case RθJA Thermal impedance, junction-to-ambient 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYP MAX UNIT 50 °C/W 178 °C/W TPPM0115 SWITCH MODE SYNCHRONOUS BUCK CONTROLLER SLVS371A– MARCH 2001 – REVISED JUNE 2001 TYPICAL CHARACTERISTICS DRVH DRVL Figure 1. Dead Time Between Gate Drives Upper Switching OFF and Lower Switching ON DRVH DRVL Figure 2. Dead Time Between Gate Drives Upper Switching ON and Lower Switching OFF POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TPPM0115 SWITCH MODE SYNCHRONOUS BUCK CONTROLLER SLVS371A– MARCH 2001 – REVISED JUNE 2001 TYPICAL CHARACTERISTICS DRVH DRVL Ripple = 9.4 mV Load = 0 Figure 3. Output Voltage Ripple (Offset = 2.5 V) With NO Load DRVH DRVL Ripple = 12.6 mV Load = 6 A Figure 4. Output Voltage Ripple (Offset = 2.5 V) With 6 A Load 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPPM0115 SWITCH MODE SYNCHRONOUS BUCK CONTROLLER SLVS371A– MARCH 2001 – REVISED JUNE 2001 TYPICAL CHARACTERISTICS DRVH DRVL Ripple = 14 mV Load = 12 A Figure 5. Output Voltage Ripple (Offset = 2.5 V) With 12 A Load Ripple = 52.4 mV Dynamic Load Step 1 A to 8 A Figure 6. Output Voltage Ripple (Offset = 2.5 V) With Dynamic Load Switching (1 A to 8 A) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TPPM0115 SWITCH MODE SYNCHRONOUS BUCK CONTROLLER SLVS371A– MARCH 2001 – REVISED JUNE 2001 TYPICAL CHARACTERISTICS EFFICIENCY vs LOAD Efficiency – % 100 95 2.5 V 90 85 80 0 2 4 6 8 IL – Load Current – A Figure 7. System Efficiency With Load Current (2.5-V Output) 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 10 TPPM0115 SWITCH MODE SYNCHRONOUS BUCK CONTROLLER SLVS371A– MARCH 2001 – REVISED JUNE 2001 APPLICATION INFORMATION 5V 1.7 µH 0.1 µF 12 V Supply VDD VCC 4.7 µF 2200 µF 2200 µF DRVH 1 µF PHASE TPPM0115 20 kΩ PWRGD DRVL 4 µH 2.2 Ω 4.7 nF R1 1-V Ref GND VOUT 1 V to 2.5 V 0.1 µF 4.7 µF 1500 µF Low ESR 1500 µF Low ESR R2 SEN Optional 680 pF NOTES: A. B. C. D. E. 4.7 µF The heavy lines must be kept short and connected to the ground plane construction for efficient results. The feedback (sense) trace should be kept from the inductor flux. The 1500-µF capacitor should have a low ESR to minimize output voltage ripple. External FETs are MTD3302 or PHD55N03LT. Set the resistor values on the SEN terminal using the following formulas: V OUT V (R1 ) R2) + ref , where V + 1V ref R2 F. Maximum efficiency is dependent on proper selection of external components. G. Line and load regulation is dependent on proper selection of external components. Optional: When resistor feedback network is not used, VOUT must be connected directly to SEN input to provide output regulation at VOUT = Vref. Figure 8. Typical Application Schematic POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TPPM0115 SWITCH MODE SYNCHRONOUS BUCK CONTROLLER SLVS371A– MARCH 2001 – REVISED JUNE 2001 APPLICATION INFORMATION VCC 1.7 µH 0.1 µF 4.7 µF 4.7 µF 1000 µF 1000 µF PHD55N03LT 12V Supply VCC 1 µF GND 8 4 µH TPPM0115 2 PWRGD SEN 7 20 kΩ 1500 µF Low ESR PHD55N03LT DRVL 6 4 DRVH 5 0.1 µF 2.2 Ω 680pF 3 NC 1500 µF Low ESR 4.7 µF 4700 pF PHASE V 2P5 MEM 250 Ω 1% 1 kΩ 1% VCC FQD13N06L 5 4 V1P25MEM VTT 4.7 µF 0.1 µF 220 µF Low ESR 220 µF Low ESR + 1 LMV321 – 3 2 50 Ω 1% 0.1 µF 50 Ω 1% 1 µF P-Channel NOTES: A. The heavy lines must be kept short and connected to the ground plane construction for efficient results. B. The performance of the regulator depends on the proper selection of the external components for the application. Figure 9. Application Schematic for DDR Memory VDDQ and VTT Supplies 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V2P5MEM VDDQ 1 TPPM0115 SWITCH MODE SYNCHRONOUS BUCK CONTROLLER SLVS371A– MARCH 2001 – REVISED JUNE 2001 APPLICATION INFORMATION VCC 1.7 µH 0.1 µF 4.7 µF 4.7 µF 1000 µF 1000 µF PHD55N03LT VCC 1 µF 12V Supply GND 8 4 µH TPPM0115 2 PWRGD SEN 7 1500 µF Low ESR PHD55N03LT 20 kΩ 680pF 3 NC DRVL 6 4 DRVH 5 1500 µF Low ESR 4.7 µF 0.1 µF 2.2 Ω 4700 pF PHASE V2P5MEM VDDQ 1 V 2P5 MEM 250 Ω 1% 1 kΩ 1% J1 VCC FQD13N06L 5 4 VCORE 4.7 µF 0.1 µF 220 µF Low ESR + 1 LMV321 – 3 2 300 Ω 1% 3 2 1 175 Ω 1% 450 Ω 1% 0.1 µF 1 µF P-Channel J1: 1 and 2 = 1.8 V VCORE J1: 2 and 3 = 1.5 V VCORE NOTES: A. The heavy lines must be kept short and connected to the ground plane construction for efficient results. B. The performance of the regulator depends on the proper selection of the external components for the application. Figure 10. Application Schematic for RAMBUS Memory VDDQ and VCORE Supplies POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TPPM0115 SWITCH MODE SYNCHRONOUS BUCK CONTROLLER SLVS371A– MARCH 2001 – REVISED JUNE 2001 MECHANICAL DATA D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 0.010 (0,25) M 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 0.010 (0,25) 1 7 0°–ā8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047 / D 10/96 NOTES: A. B. C. D. 12 All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). 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