SN74FB2041A 7-BIT TTL/BTL TRANSCEIVER SCBS172I – NOVEMBER 1991 – REVISED SEPTEMBER 1999 D D D D D D Compatible With IEEE Std 1194.1-1991 (BTL) TTL A Port, Backplane Transceiver Logic (BTL) B Port Open-Collector B-Port Outputs Sink 100 mA Isolated Logic-Ground and Bus-Ground Pins Reduce Noise BIAS VCC Pin Minimizes Signal Distortion During Live Insertion or Withdrawal D D D High-Impedance State During Power Up and Power Down B-Port Biasing Network Preconditions the Connector and PC Trace to the BTL High-Level Voltage TTL Input Structures Incorporate Active Clamping to Aid in Line Termination Packaged in Plastic Quad Flatpack TMS GND 1B1 2AO1 1AI1 1AO1 VCC BIAS VCC 1OEA OEB 1OEB TCK VCC RC PACKAGE (TOP VIEW) 52 51 50 49 48 47 46 45 44 43 42 41 40 1 39 2 38 3 37 4 36 5 35 6 34 7 33 8 32 9 31 10 30 11 29 12 28 13 27 GND 2B1 GND 2B2 GND 2B3 GND 3B1 GND 3B2 GND 3B3 GND 3OEB 3OEA 2OEB BG GND 2OEA TDO TDI VCC 14 15 16 17 18 19 20 21 22 23 24 25 26 3AI2 GND 3AO3 BG VCC 3AI3 GND 2AI1 2AI2 2AO2 GND 2AO3 GND 2AI3 3AI1 3AO1 GND 3AO2 GND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74FB2041A 7-BIT TTL/BTL TRANSCEIVER SCBS172I – NOVEMBER 1991 – REVISED SEPTEMBER 1999 description The SN74FB2041A device is a 7-bit transceiver designed to translate signals between TTL and backplane transceiver logic (BTL) environments. It is specifically designed to be compatible with IEEE Std 1194.1-1991. The B port operates at BTL signal levels. The open-collector B ports are specified to sink 100 mA. Two output enables (OEB and OEB) are provided for the B outputs. When OEB is high and OEB is low, the B port is active and reflects the inverse of the data present at the A-input pins. When OEB is low, OEB is high, or VCC is less than 2.1 V, the B port is turned off. The enable/disable logic partitions the device as two 3-bit sections and one 1-bit section. The A port operates at TTL signal levels and has split input and output pins. The A outputs reflect the inverse of the data at the B port when the A-port output enable (OEA) is high. When OEA is low or when VCC is less than 2.1 V, the A outputs are in the high-impedance state. Pins are allocated for the four-wire IEEE Std 1149.1 (JTAG) test bus. TMS and TCK are not connected and TDI is shorted to TDO. BIAS VCC establishes a voltage between 1.62 V and 2.1 V on the BTL outputs when VCC is not connected. The SN74FB2041A is characterized for operation from 0°C to 70°C. FUNCTION TABLE INPUTS 2 OEB OEB OEA L X L X H L FUNCTION Isolation L X H X H H H L L AI data to B bus H L H AI data to B bus, B data to AO bus B data to AO bus b s POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74FB2041A 7-BIT TTL/BTL TRANSCEIVER SCBS172I – NOVEMBER 1991 – REVISED SEPTEMBER 1999 logic symbol† OEB 1OEA 1OEB 2OEA 2OEB 3OEA 3OEB 1AO1 1AI1 2AO1 2AI1 2AO2 2AI2 2AO3 2AI3 3AO1 3AI1 3AO2 3AI2 3AO3 3AI3 46 47 45 20 25 24 26 50 G1 EN2 1EN3 EN4 1EN5 EN6 1EN7 2 51 52 40 1 1B1 3 4 1 2 38 2B1 5 4 36 2B2 3 6 34 2B3 8 10 6 32 1 9 7 12 30 3B1 3B2 14 28 16 3B3 18 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74FB2041A 7-BIT TTL/BTL TRANSCEIVER SCBS172I – NOVEMBER 1991 – REVISED SEPTEMBER 1999 functional block diagram OEB 1OEB 1OEA 1AI1 1AO1 2OEB 2OEA 2AI1 2AO1 46 45 47 40 51 50 25 20 38 2 2B1 52 36 3 2AI2 2AO2 2B2 4 34 8 2B3 2AI3 2AO3 1B1 6 26 3OEB 24 3OEA 3AI1 3AO1 3AI2 3AO2 3AI3 32 9 3B1 10 30 14 12 28 18 16 3AO3 4 3B2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3B3 SN74FB2041A 7-BIT TTL/BTL TRANSCEIVER SCBS172I – NOVEMBER 1991 – REVISED SEPTEMBER 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI: Except B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 7 V B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 3.5 V Voltage range applied to any B output in the disabled or power-off state, VO . . . . . . . . . . . . . . –0.5 V to 3.5 V Voltage range applied to any output in the high state, VO: A port . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC Input clamp current, IIK: Except B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40 mA B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Current applied to any single output in the low state, IO: A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA Package thermal impedance, θJA (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 2) VCC, BIAS VCC, BG VCC Supply voltage VIH High level input voltage High-level VIL Low level input voltage Low-level IIK IOH Input clamp current IOL Low level output current Low-level B port Except B port B port Except B port High-level output current AO port AO port B port MIN NOM MAX 4.5 5 5.5 1.62 2.3 2 0.75 1.47 0.8 UNIT V V V –18 mA –3 mA 24 100 mA TA Operating free-air temperature 0 70 °C NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74FB2041A 7-BIT TTL/BTL TRANSCEIVER SCBS172I – NOVEMBER 1991 – REVISED SEPTEMBER 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER MIN TYP† MAX Except B port II = –18 mA II = –40 mA AO port VCC = 4 4.5 5V IOH = –1 mA IOH = –3 mA AO port VCC = 4 4.5 5V IOL = 20 mA IOL = 24 mA B port VCC = 4 4.5 5V IOL = 80 mA IOL = 100 mA II Except B port VCC = 5.5 V, VI = 5.5 V IIH‡ Except B port VCC = 5.5 V, Except B port VCC = 5.5 V, VCC = 5.5 V, VCC = 0 to 5.5 V, VCC = 5.5 V, VO = 2.1 V VO = 2.7 V 100 µA 50 µA –50 µA 50 µA VOH VOL IIL‡ B port IOZPD IOS§ AO port VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V AO port VCC = 5.5 V, VO = 0 VCC = 5 5.5 5 V, V IO = 0 Co Cio AO port B port per IEEE Std 1194.1-1991 V 1.15 µA VO = 0.5 V VO = 0.5 V to 2.7 V Control inputs 1.1 50 VCC = 5.5 V, VCC = 0 to 2.1 V, AI port 0.5 –50 AO port Ci 0.35 0.75 VI = 0.5 V VI = 0.75 V AO port B port to AO port V 3.3 VI = 2.7 V IOZL IOZPU AI port to B port 2.5 V µA B port ICC –0.5 50 IOH IOZH AO port –1.2 UNIT VCC = 4.5 V, VCC = 4.5 V, VIK B port TEST CONDITIONS –100 –30 –50 µA –180 mA 45 65 3 VI = 0.5 0 5 V or 2.5 25V 5.5 pF 5 VCC = 4.5 V to 5.5 V mA pF 3 VO = 0.5 V or 2.5 V VCC = 0 to 4.5 V µA A 5 pF † All typical values are at VCC = 5 V, TA = 25°C. ‡ For I/O ports, the parameters IIH and IIL include the off-state output current. § Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. live-insertion specifications over recommended operating free-air temperature range PARAMETER ICC (BIAS VCC) VO IO 6 B port B port TEST CONDITIONS VCC = 0 to 4.5 V VCC = 4.5 V to 5.5 V V VB = 0 to 2 V, 4 5 V to 5.5 55V Vl (BIAS VCC) = 4.5 VCC = 0, VCC = 0, VI (BIAS VCC) = 5 V VB = 1 V, Vl (BIAS VCC) = 4.5 V to 5.5 V VCC = 0 to 5.5 V, VCC = 0 to 2.2 V, MIN MAX 450 10 µA 2.1 V OEB = 0 to 0.8 V 100 µA OEB = 0 to 5 V 100 POST OFFICE BOX 655303 1.62 UNIT • DALLAS, TEXAS 75265 –1 SN74FB2041A 7-BIT TTL/BTL TRANSCEIVER SCBS172I – NOVEMBER 1991 – REVISED SEPTEMBER 1999 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tPLH tPHL AI B tPLH tPHL B AO tPLH tPHL OEB B tPLH tPHL OEB B tPZH tPZL OEA AO tPHZ tPLZ OEA AO PARAMETER tsk(p)† tsk(o)† tt t(pr) VCC = 5 V, TA = 25°C MIN MAX 5.1 2 5.6 4.1 5 2.5 5.3 MIN TYP MAX 2.3 3.9 2.6 2 3.6 4.8 1.7 5.3 2.3 3.8 4.9 2 6.4 3 4.6 5.8 2.6 6.3 3.1 4.7 6 3.1 6.2 2.7 4.3 5.6 2.6 5.8 2.7 4.2 5.3 2.5 6.4 1.5 3.2 5.2 1.5 5.2 1.1 2.8 5 1 5 1 2.4 3.9 1 4.2 2.2 3.8 5.6 1.7 5.8 UNIT ns ns ns ns ns ns Pulse skew, AI to B or B to AO 0.5 ns Pulse skew, AI to B or B to AO 0.4 ns Rise time, 1.3 V to 1.8 V, B outputs 1 1.6 2.4 1 2.5 Fall time, 1.8 V to 1.3 V, B outputs 1 1.4 2.3 1 2.4 B-port input pulse rejection 1 1 ns ns † Skew values are applicable for through mode only. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN74FB2041A 7-BIT TTL/BTL TRANSCEIVER SCBS172I – NOVEMBER 1991 – REVISED SEPTEMBER 1999 PARAMETER MEASUREMENT INFORMATION 2.1 V 16.5 Ω 7V S1 500 Ω From Output Under Test CL = 50 pF (see Note A) Open CL = 30 pF (see Note A) 500 Ω LOAD CIRCUIT FOR A OUTPUTS Input 1.5 V Test Point From Output Under Test LOAD CIRCUIT FOR B OUTPUTS 3V TEST S1 0V tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open 1.5 V tPHL tPLH 1.55 V 1.55 V VOH Output VOL 3V Output Control tPZL 2V 1.55 V 1.55 V 1V tPHL 1.5 V Output Waveform 1 S1 at 7 V (see Note B) tPLZ 3.5 V 1.5 V tPZH tPLH VOH Output 1.5 V 0V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (A TO B) Input 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (B TO A) Output Waveform 2 S1 at Open (see Note B) VOL + 0.3 V VOL tPHZ 1.5 V VOH VOH – 0.3 V ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES (A PORT) NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: TTL inputs: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns; BTL inputs: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1999, Texas Instruments Incorporated