Revised January 2002 74F676 16-Bit Serial/Parallel-In, Serial-Out Shift Register General Description Features The 74F676 contains 16 flip-flops with provision for synchronous parallel or serial entry and serial output. When the Mode (M) input is HIGH, information present on the parallel data (P0–P15) inputs is entered on the falling edge of the Clock Pulse (CP) input signal. When M is LOW, data is shifted out of the most significant bit position while information present on the Serial (SI) input shifts into the least significant bit position. A HIGH signal on the Chip Select (CS) input prevents both parallel and serial operations. ■ 16-bit parallel-to-serial conversion ■ 16-bit serial-in, serial-out ■ Chip select control ■ Slim 24 lead 300 mil package Ordering Code: Order Number 74F676SC Package Number M24B Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74F676PC N24A 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600" Wide 74F676SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 2002 Fairchild Semiconductor Corporation DS009588 www.fairchildsemi.com 74F676 16-Bit Serial/Parallel-In, Serial-Out Shift Register April 1988 74F676 Unit Loading/Fan Out Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL P0–P15 Parallel Data Inputs 1.0/1.0 20 µA/−0.6 mA CS Chip Select Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA CP Clock Pulse Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA M Mode Select Input 1.0/1.0 20 µA/−0.6 mA SI Serial Data Input 1.0/1.0 20 µA/−0.6 mA SO Serial Output 50/33.3 −1 mA/20 mA Functional Description Shift Register Operations Table The 16-bit shift register operates in one of three modes, as indicated in the Shift Register Operations Table. Control Input Operating Mode HOLD— a HIGH signal on the Chip Select (CS) input prevents clocking, and data is stored in the sixteen registers. Shift/Serial Load— data present on the SI pin shifts into the register on the falling edge of CP. Data enters the Q0 position and shifts toward Q15 on successive clocks, finally appearing on the SO pin. M CP H X L L L H H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = HIGH-to-LOW Transition Parallel Load— data present on P0–P15 are entered into the register on the falling edge of CP. The SO output represents the Q15 register output. To prevent false clocking, CP must be LOW during a LOW-to-HIGH transition of CS. Block Diagram www.fairchildsemi.com CS 2 X Hold Shift/Serial Load Parallel Load Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Current Applied to Output in LOW State (Max) twice the rated IOL (mA) DC Electrical Characteristics Symbol Parameter Min Typ Max VCC VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V Min V Min 0.5 V Min IOL = 20 mA 5.0 µA Max VIN = 2.7V 7.0 µA Max VIN = 7.0V 50 µA Max VOUT = VCC V 0.0 3.75 µA 0.0 −0.6 mA Max VIN = 0.5V −150 mA Max VOUT = 0V 72 mA Max Output HIGH Voltage VOL Output LOW Voltage IIH Input HIGH Current IBVI Input HIGH Current 10% VCC 2.5 5% VCC 2.7 V Conditions Input HIGH Voltage VOH 2.0 Units VIH 10% VCC Breakdown Test ICEX Output HIGH Leakage Current VID Input Leakage Test IOD 4.75 Output Leakage Circuit Current IIL Input LOW Current IOS Output Short-Circuit Current ICC Power Supply Current −60 3 Recognized as a HIGH Signal Recognized as a LOW Signal IIN = −18 mA IOH = −1 mA IOH = −1 mA IID = 1.9 µA, All Other Pins Grounded VIOD = 150 mV, All Other Pins Grounded www.fairchildsemi.com 74F676 Absolute Maximum Ratings(Note 1) 74F676 AC Electrical Characteristics Symbol Parameter TA = +25°C TA = −55°C to 125°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF CL = 50 pF Min Typ fMAX Maximum Clock Frequency 100 110 Max Min Max tPLH Propagation Delay 4.5 9.0 11.0 4.5 17.0 4.5 12.0 tPHL CP to SO 5.0 9.0 12.5 5.0 14.5 5.0 13.5 45 Min Units Max 90 MHz ns AC Operating Requirements Symbol Parameter TA = +25°C TA = −55°C to 125°C VCC = +5.0V VCC = +5.0V Min Max Min Max TA, VCC = ____ VCC = +5.0V Min tS(H) Setup Time, HIGH or LOW 4.0 4.0 4.0 tS(L) SI to CP 4.0 4.0 4.0 tH(H) Hold Time, HIGH or LOW 4.0 4.0 4.0 tH(L) SI to CP 4.0 4.0 4.0 tS(H) Setup Time, HIGH or LOW 3.0 3.0 3.0 tS(L) Pn to CP 3.0 3.0 3.0 tH(H) Hold Time, HIGH or LOW 4.0 4.0 4.0 tH(L) Pn to CP 4.0 4.0 4.0 tS(H) Setup Time, HIGH or LOW 8.0 8.0 8.0 tS(L) M to CP 8.0 8.0 8.0 tH(H) Hold Time, HIGH or LOW 2.0 2.0 2.0 tH(L) M to CP 2.0 2.0 2.0 tS(L) Setup Time, LOW 10.0 12.0 10.0 10.0 10.0 10.0 CS to CP tH(H) Hold Time, HIGH CS to CP ns ns ns ns tW(H) CP Pulse Width 4.0 5.0 4.0 tW(L) HIGH or LOW 6.0 9.0 6.0 www.fairchildsemi.com Units Max 4 ns 74F676 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M24B 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600" Wide Package Number N24A 5 www.fairchildsemi.com 74F676 16-Bit Serial/Parallel-In, Serial-Out Shift Register Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 6