Revised May 1999 MM74HCT573 • MM74HCT574 Octal D-Type Latch • 3-STATE Octal D-Type Flip-Flop General Description The MM74HCT573 octal D-type latches and MM74HCT574 octal D-type flip-flop advanced silicon-gate CMOS technology, which provides the inherent benefits of low power consumption and wide power supply range, but are LS-TTL input and output characteristic and pin-out compatible. The 3-STATE outputs are capable of driving 15 LS-TTL loads. All inputs are protected from damage due to static discharge by internal diodes to VCC and ground. When the MM74HCT573 Latch Enable input is HIGH, the Q outputs will follow the D inputs. When the Latch Enable goes LOW, data at the D inputs will be retained at the outputs until Latch Enable returns HIGH again. When a high logic level is applied to the Output Control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. The MM74HCT574 are positive edge triggered flip-flops. Data at the D inputs, meeting the setup and hold time requirements, are transferred to the Q outputs on positive going transitions of the Clock (CK) input. When a high logic level is applied to the Output Control (OC) input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. The MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS devices. These parts are also plug in replacements for LS-TTL devices and can be used to reduce power consumption in existing designs. Features ■ TTL input characteristic compatible ■ Typical propagation delay: 18 ns ■ Low input current: 1 µA maximum ■ Low quiescent current: 80 µA maximum ■ Compatible with bus-oriented systems ■ Output drive capability: 15 LS-TTL loads Ordering Codes: Order Number Package Number MM74HCT573WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HCT573SJ MM74HCT573MTC MTC20 Package Description 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HCT573N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide MM74HCT574WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HCT574SJ MM74HCT574MTC MM74HCT574N MTC20 N20A 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. © 1999 Fairchild Semiconductor Corporation DS010627.prf www.fairchildsemi.com MM74HCT573 • MM74HCT574 Octal D-Type Latch • 3-STATE Octal D-Type Flip-Flop February 1990 MM74HCT573 • MM74HCT574 Connection Diagrams Truth Tables MM74HCT573 Output Control LE Data Output L H H H L H L L L L X Q0 H X X Z H = HIGH Level L = LOW Level Q0 = Level of output before steady-state input conditions were established. Z = High Impedance State Top View MM74HCT573 MM74HCT574 Output Control LE Data Output L ↑ H H L ↑ L L L L X Q0 H X X Z H = HIGH Level L = LOW Level Q0 = Level of output before steady-state input conditions were established. X = Don’t Care Z = High Impedance State ↑ = Transition from LOW-to-HIGH Top View MM74HCT574 www.fairchildsemi.com 2 Recommended Operating Conditions −0.5 to +7.0V Supply Voltage (VCC) DC Input Voltage (VIN) −1.5 to VCC+ 1.5V DC Output Voltage (VOUT) −0.5 to VCC+ 0.5V Clamp Diode Current (IIK, IOK) ± 20 mA DC Output Current, per pin (IOUT) ± 35 mA 600 mW 500 mW 0 VCC V −40 +85 °C 500 ns tr, tf Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C. Lead Temperature (TL) (Soldering 10 seconds) V Input Rise or Fall Times Power Dissipation (PD) S. O. Package only Units 5.5 (VIN, VOUT) Operating Temperature Range (TA) −65°C to +150°C (Note 3) Max 4.5 DC Input or Output Voltage ± 70 mA DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Min Supply Voltage (VCC) 260°C DC Electrical Characteristics VCC = 5V ± 10% (unless otherwise specified) Symbol VIH Parameter TA = 25°C Conditions Typ Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH VOL IIN IOZ TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits 2.0 2.0 2.0 V 0.8 0.8 0.8 V Minimum HIGH Level VIN = VIH or VIL Output Voltage |IOUT| = 20 µA VCC VCC − 0.1 VCC − 0.1 VCC − 0.1 |IOUT| = 6.0 mA, VCC = 4.5V 4.2 3.98 3.84 3.7 |IOUT| = 7.2 mA, VCC = 5.5V 5.7 4.98 4.84 4.7 Maximum LOW Level VIN = VIH or VIL Voltage |IOUT| = 20 µA Units V 0 0.1 0.1 0.1 |IOUT| = 6.0 mA, VCC = 4.5V 0.2 0.26 0.33 0.4 |IOUT| = 7.2 mA, VCC = 5.5V 0.2 0.26 0.33 0.4 ±0.1 ±1.0 ±1.0 µA ±0.5 ±5.0 ±10 µA 8.0 80 160 µA 1.5 1.8 2.0 mA Maximum Input VIN = VCC or GND, Current VIH or VIL Maximum 3-STATE VOUT = VCC or GND Output Leakage Enable = VIH or VIL V Current ICC Maximum Quiescent Supply Current VIN = VCC or GND IOUT = 0 µA VIN = 2.4V or 0.5V (Note 4) Note 4: Measured per pin. All others tied to VCC or ground. 3 www.fairchildsemi.com MM74HCT573 • MM74HCT574 Absolute Maximum Ratings(Note 1) (Note 2) MM74HCT573 • MM74HCT574 AC Electrical Characteristics MM74HCT573 VCC = 5.0V, tr = tf = 6 ns, TA = 25°C (unless otherwise specified) Symbol Parameter tPHL Maximum Propagation Delay tPLH Data to Output tPHL Maximum Propagation Delay tPLH Latch Enable to Output Conditions CL = 45 pF CL = 45 pF Typ Guaranteed Limit Units 17 27 ns 16 27 ns 21 30 ns 14 23 ns tPZH Maximum Enable Propagation Delay CL = 45 pF tPZL Control to Output RL = 1 kΩ tPHZ Maximum Disable Propagation Delay CL = 5 pF tPLZ Control to Output RL = 1 kΩ tW Minimum Clock Pulse Width 15 ns tS Minimum Setup Time Data to Clock 5 ns tH Minimum Hold Time Clock to Data 12 ns AC Electrical Characteristics MM74HCT573 VCC= 5.0V ± 10%, tr = tf = 6 ns (unless otherwise specified) Symbol Parameter TA = 25° Conditions TA = −40 to 85°C TA = −55 to 125°C Typ CL = 50 pF Guaranteed Limits tPHL Maximum Propagation tPLH Delay Data to Output tPHL Maximum Propagation Delay tPLH Latch Enable to Output tPZH Maximum Enable Propagation CL = 50 pF tPZL Delay Control to Output RL = 1 kΩ tPHZ Maximum Disable Propagation CL = 50 pF tPLZ Delay Control to Output RL = 1 kΩ tTHL Maximum Output CL = 50 pF tTLH Rise and Fall Time tW Minimum Clock Pulse Width tS Minimum Setup Time Data to Clock −3 tH Minimum Hold Time Clock to Data 4 CIN Maximum Input Capacitance COUT Maximum Output Capacitance CPD Power Dissipation Capacitance OC = V CC 5 (Note 5) OC = GND 52 CL = 50 pF 18 30 38 45 ns 17 30 44 53 ns 22 30 38 45 ns 15 30 38 45 ns 6 12 15 18 ns 15 20 24 ns 5 6 8 ns 12 15 18 ns 10 10 10 pF 20 20 20 pF Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f+ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f+ICC. www.fairchildsemi.com 4 Units pF MM74HCT573 • MM74HCT574 AC Electrical Characteristics MM74HCT574 VCC = 5.0V, tr = tf = 6 ns, TA = 25°C Symbol Parameter Conditions Typ Guaranteed Limit Units 60 33 MHz 17 27 ns 19 28 ns fMAX Maximum Clock Frequency tPHL Maximum Propagation Delay tPLH to Output tPZH Maximum Enable Propagation Delay tPZL Control to Output RL = 1 kΩ tPHZ Maximum Disable Propagation Delay CL = 45 pF tPLZ Control to Output RL = 1 kΩ 25 ns tW Minimum Clock Pulse Width 15 ns tS Minimum Setup Time Data to Clock 12 ns tH Minimum Hold Time Clock to Data 5 ns CL = 45 pF CL = 45 pF 14 AC Electrical Characteristics MM74HCT574 VCC = 5.0V ± 10%, tr = tf = 6 ns (unless otherwise specified) Symbol Parameter fMAX Maximum Clock Frequency tPHL Maximum Propagation Delay tPLH Clock to Output Conditions CL = 50 pF TA = 25°C Typ TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits Units 33 28 23 MHz 18 30 38 45 ns 22 30 38 45 ns 15 30 38 45 ns 6 12 15 18 ns 15 20 24 ns 12 15 18 ns tPZH Maximum Enable Propagation CL = 50 pF tPZL Delay Control to Output RL = 1 kΩ tPHZ Maximum Disable Propagation CL = 50 pF tPLZ Delay Control to Output RL = 1 kΩ tTHL Maximum Output CL = 50 pF tTLH Rise and Fall Time tW Minimum Clock Pulse Width tS Minimum Setup Time Data to Clock 6 tH Minimum Hold Time Clock to Data −1 CIN Maximum Input Capacitance COUT Maximum Output Capacitance CPD Power Dissipation Capacitance OC = VCC 5 (Note 6) OC = GND 58 5 6 8 ns 10 10 10 pF 20 20 20 pF pF Note 6: CPD determines the no load power consumption, PD = CPD VCC f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC. 2 5 www.fairchildsemi.com MM74HCT573 • MM74HCT574 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 6 MM74HCT573 • MM74HCT574 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 7 www.fairchildsemi.com MM74HCT573 • MM74HCT574 Octal D-Type Latch • 3-STATE Octal D-Type Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.