Revised February 1999 MM74HC175 Quad D-Type Flip-Flop With Clear General Description The MM74HC175 high speed D-type flip-flop with complementary outputs utilizes advanced silicon-gate CMOS technology to achieve the high noise immunity and low power consumption of standard CMOS integrated circuits, along with the ability to drive 10 LS-TTL loads. Information at the D inputs of the MM74HC175 is transferred to the Q and Q outputs on the positive going edge of the clock pulse. Both true and complement outputs from each flip flop are externally available. All four flip-flops are controlled by a common clock and a common CLEAR. Clearing is accomplished by a negative pulse at the CLEAR input. All four Q outputs are cleared to a logical “0” and all four Q outputs to a logical “1.” The 74HC logic family is functionally as well as pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. Features ■ Typical propagation delay: 15 ns ■ Wide operating supply voltage range: 2–6V ■ Low input current: 1 µA maximum ■ Low quiescent supply current: 80 µA maximum (74HC) ■ High output drive current: 4 mA minimum (74HC) Ordering Code: Order Number MM74HC175M MM74HC175SJ MM74HC175MTC MM74HC175N Package Number Package Description M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC16 N16E 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table (Each Flip-Flop) Inputs Outputs Pin Assignments for DIP, SOIC, SOP and TSSOP Clear Clock D Q Q L X X L H H ↑ H H L H ↑ L L H H L X Q0 Q0 H = HIGH Level (steady state) L = LOW Level (steady state) X = Irrelevant ↑ = Transition from LOW-to-HIGH level Q0 = The level of Q before the indicated steady-state input conditions were established Top View © 1999 Fairchild Semiconductor Corporation DS005319.prf www.fairchildsemi.com MM74HC175 Quad D-Type Flip-Flop With Clear September 1983 MM74HC175 Logic Diagram www.fairchildsemi.com 2 Recommended Operating Conditions −0.5 to +7.0V Supply Voltage (VCC) DC Input Voltage (VIN) −1.5 to VCC +1.5V DC Output Voltage (VOUT) −0.5 to VCC +0.5V Clamp Diode Current (IIK, IOK) ±20 mA DC Output Current, per pin (IOUT) ±25 mA Max Units 2 6 V 0 VCC V −40 +85 °C (tr, tf) VCC = 2.0V 1000 ns VCC = 4.5V 500 ns VCC = 6.0V 400 ns DC Input or Output Voltage (VIN,VOUT) Operating Temperature Range (TA) ±50 mA DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Min Supply Voltage (VCC) Input Rise or Fall Times −65°C to +150°C Power Dissipation (PD) (Note 3) 600 mW S.O. Package only 500 mW Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Lead Temperature (TL) (Soldering 10 seconds) DC Electrical Characteristics Symbol VIH VIL VOH Parameter Note 2: Unless otherwise specified all voltages are referenced to ground. 260°C Conditions Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C. (Note 4) VCC TA = 25°C Typ TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits Units Minimum HIGH Level 2.0V 1.5 1.5 1.5 Input Voltage 4.5V 3.15 3.15 3.15 V V 6.0V 4.2 4.2 4.2 V V Maximum LOW Level 2.0V 0.5 0.5 0.5 Input Voltage 4.5V 1.35 1.35 1.35 V 6.0V 1.8 1.8 1.8 V Minimum HIGH Level VIN = VIH or VIL Output Voltage |IOUT| ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 V 4.5V 4.5 4.4 4.4 4.4 V 6.0V 6.0 5.9 5.9 5.9 V |IOUT| ≤ 4.0 mA 4.5V 4.2 3.98 3.84 3.7 V |IOUT| ≤ 5.2 mA 6.0V 5.7 5.48 5.34 5.2 V VIN = VIH or VIL VOL Maximum LOW Level VIN = VIH or VIL Output Voltage |IOUT| ≤ 20 µA 2.0V 0 0.1 0.1 0.1 V 4.5V 0 0.1 0.1 0.1 V 6.0V 0 0.1 0.1 0.1 V |IOUT| ≤ 4.0 mA 4.5V 0.2 0.26 0.33 0.4 V |IOUT| ≤ 5.2 mA 6.0V 0.2 0.26 0.33 0.4 V VIN = VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA 6.0V 8 80 160 µA VIN = VIH or VIL IIN Maximum Input ICC Maximum Quiescent VIN = VCC or GND Supply Current IOUT = 0 µA Current Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. 3 www.fairchildsemi.com MM74HC175 Absolute Maximum Ratings(Note 1) (Note 2) MM74HC175 AC Electrical Characteristics VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns Symbol fMAX Parameter Conditions Guaranteed Typ Maximum Operating Limit Units 60 35 MHz 15 25 ns 13 21 ns 20 ns Frequency tPHL, tPLH Maximum Propagation Delay, Clock to Q or Q tPHL, tPLH Maximum Propagation Delay, Reset to Q or Q tREC Minimum Removal Time, Clear to Clock tS Minimum Setup Time, Data to Clock 20 ns tH Minimum Hold Time, Data from Clock 0 ns tW Minimum Pulse Width, Clock or Clear 16 ns 10 AC Electrical Characteristics VCC = 2.0V to 6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol fMAX Parameter Conditions VCC TA = 25°C Typ TA = −40 to 85°C TA = −55 to 125°C Units Guaranteed Limits Maximum Operating 2.0V 12 6 5 4 MHz Frequency 4.5V 60 30 24 20 MHz 6.0V 70 35 28 24 MHz tPHL, tPLH Maximum Propagation 2.0V 80 150 190 225 ns Delay, Clock to Q or Q 4.5V 15 30 38 45 ns 6.0V 13 26 32 38 ns tPHL, tPLH Maximum Propagation 2.0V 64 125 158 186 ns Delay, Reset to Q or Q 4.5V 14 25 32 37 ns 6.0V 12 21 27 32 ns tREM tS tH tW tr , tf Minimum Removal Time 2.0V 100 125 150 ns Clear to Clock 4.5V 20 25 30 ns 6.0V 17 21 25 ns Minimum Setup Time 2.0V 100 125 150 ns Data to Clock 4.5V 20 25 30 ns 6.0V 17 21 25 ns Minimum Hold Time 2.0V 0 0 0 ns Data from Clock 4.5V 0 0 0 ns 6.0V 0 0 0 ns Minimum Pulse Width 2.0V 30 80 100 120 ns Clear or Clock 4.5V 9 16 20 24 ns 6.0V 8 14 17 20 ns Maximum Input Rise and 2.0V 1000 1000 1000 ns 4.5V 500 500 500 ns 400 400 400 ns Fall Time 6.0V tTLH, tTHL Maximum CPD 2.0V 30 75 95 110 ns Output Rise and 4.5V 9 15 19 22 ns Fall Time 6.0V 8 13 16 19 Power Dissipation Capacitance (Note 5) CIN 150 (per package) Maximum Input 5 ns pF 10 10 10 pF Capacitance Note 5: CPD determines the no load dynamic power consumption, PD=CPD VCC2f+ICC VCC, and the no load dynamic current consumption, IS=CPD VCC f+ICC. www.fairchildsemi.com 4 MM74HC175 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Package Number M16A 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D 5 www.fairchildsemi.com MM74HC175 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 www.fairchildsemi.com 6 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. MM74HC175 Quad D-Type Flip-Flop With Clear Physical Dimensions inches (millimeters) unless otherwise noted (Continued)