Revised February 1999 MM74HCT164 8-Bit Serial-in/Parallel-out Shift Register General Description The MM74HCT164 utilizes advanced silicon-gate CMOS technology. It has the high noise immunity and low consumption of standard CMOS integrated circuits. It also offers speeds comparable to low power Schottky devices. This 8-bit shift register has gated serial inputs and CLEAR. Each register bit is a D-type master/slave flip-flop. Inputs A & B permit complete control over the incoming data. A LOW at either or both inputs inhibits entry of new data and resets the first flip-flop to the low level at the next clock pulse. A HIGH level on one input enables the other input which will then determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is HIGH or LOW, but only information meeting the setup and hold time requirements will be entered. Data is serially shifted in and out of the 8-bit register during the positive going transition of the clock pulse. Clear is independent of the clock and accomplished by a low level at the CLEAR input. The 74HCT logic family is functionally as well as pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS devices. These parts are also plug-in replacements for LS-TTL devices and can be used to reduce power consumption in existing designs. Features ■ Typical propagation delay: 20 ns ■ Low quiescent current: 40 µA maximum (74HCT Series) ■ Low input current: 1 µA maximum ■ Fanout of 10 LS-TTL loads ■ TTL input compatible Ordering Code: Order Number Package Number MM74HCT164M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Package Description MM74HCT164SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HCT164N N14A 14-Lead Plastic Dual-In-Line Package (PDIP) JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table Pin Assignments for DIP, SOIC and SOP Inputs Outputs Clear Clock A B QA QB ... QH L X X X L L L H L X X QAO QBO QHO H ↑ H H H QAn QGn H ↑ L X L QAn QGn H ↑ X L L QAn QGn H = HIGH Level (steady state) L = LOW Level (steady state) X = Irrelevant (any input, including transitions) ↑ = Transition from LOW-to-HIGH level. QAO, QBO, QHO = the level of QA, QB, or QH, respectively, before the indicated steady state input conditions were established. QAn, QGn = The level of QA or QG before the most recent ↑ transition of the clock; indicated a one-bit shift. Top View © 1999 Fairchild Semiconductor Corporation DS005765.prf www.fairchildsemi.com MM74HCT164 8-Bit Serial-in/Parallel-out Shift Register February 1984 MM74HCT164 Logic Diagram www.fairchildsemi.com 2 Recommended Operating Conditions −0.5 to +7.0V Supply Voltage (VCC) DC Input Voltage (VIN) −1.5 to VCC +1.5V DC Output Voltage (VOUT) −0.5 to VCC +0.5V Clamp Diode Current (IIK, IOK) ±20 mA DC Output Current, per pin (IOUT) ±25 mA 600 mW 500 mW V 0 VCC V −40 +85 °C 500 ns (tr, tf) Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C. Lead Temperature (TL) (Soldering 10 seconds) Units 5.5 Input Rise or Fall Times Power Dissipation (PD) S.O. Package Only Max 4.5 (VIN, VOUT ) Operating Temperature Range (TA) −65°C to +150°C (Note 3) Min DC Input or Output Voltage ±50 mA DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Supply Voltage (VCC) 260°C DC Electrical Characteristics VCC = 5V ± 10% (unless otherwise specified) Symbol VIH Parameter TA = 25°C Conditions Typ Minimum HIGH Level TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits Units 2.0 2.0 2.0 V 0.8 0.8 0.8 V Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VOL IIN VIN = VIH or VIL |IOUT| = 20 µA VCC VCC− 0.1 VCC− 0.1 VCC− 0.1 V |IOUT| = 4.0 mA, VCC = 4.5V 4.2 3.98 3.84 3.7 V |IOUT| = 4.8 mA, VCC = 5.5V 5.2 4.98 4.84 4.7 V Maximum LOW Level VIN = VIH or VIL Voltage |IOUT| = 20 µA Maximum Input 0 0.1 0.1 0.1 V |IOUT| = 4.0 mA, VCC = 4.5V 0.2 0.26 0.33 0.4 V |IOUT| = 4.8 mA, VCC = 5.5V 0.2 0.26 0.33 0.4 V ±0.1 ±1.0 ±1.0 µA VIN = VCC or GND Current ICC Maximum Quiescent VIN = VCC or GND Supply Current IOUT = 0 µA 8.0 80 160 µA VIN = 2.4V or 0.4V (Note 4) 1.0 1.3 1.5 mA Note 4: This is measured per pin. All other inputs are held at VCC ground. 3 www.fairchildsemi.com MM74HCT164 Absolute Maximum Ratings(Note 1) (Note 2) MM74HCT164 AC Electrical Characteristics VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns Symbol fMAX tPHL, tPLH Parameter Conditions Maximum Operating 50% Duty Frequency from Clock to Q Cycle Clock Guaranteed Typ Units Limit 55 35 MHz 17 27 ns 23 38 ns 3 6 ns tH ≥ 20 ns 6 13 ns tS ≥ 20 ns 1.5 5 ns 9 16 ns Maximum Propagation Delay Clock to Q tPHL, tPLH Maximum Propagation Delay from Clear to Q tREM Minimum Removal Time, Clear to Clock tS Minimum Set Up Time Data to Clock tH Minimum Hold Time Clock to Data tW Minimum Pulse Width Clock, Preset or Clear AC Electrical Characteristics VCC = 5.0V, ± 10%, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol fMAX Parameter Conditions TA = 25°C TA = −40°C to 85°C TA = −55°C to 125°C Max 45 30 25 22 MHz 20 30 38 45 ns 26 41 51 61 ns 4 8 10 14 ns tH ≥ 20 ns 7 15 19 23 ns tS ≥ 20 ns 1.5 5 5 5 ns 10 18 22 27 ns 500 500 500 ns 15 19 22 ns Maximum Operating 50% Duty Frequency Cycle Clock tPHL, tPLH Maximum Propagation Min Max Min Max Units Typ Delay from Clock to Q tPHL Maximum Propagation Delay from Clear to Q tREM Minimum Removal Time Clear to Clock tS Minimum Setup Time Data to Clock tH Minimum Hold Time Clock to Data tW Minimum Pulse Width Clock, or Clear tr, tf Maximum Input Rise and Fall Time tTHL, tTLH Maximum Output Rise and Fall Time CPD Power Dissipation (per flip-flop) 160 pF Capacitance (Note 5) CIN Maximum Input 5 10 10 10 pF Capacitance Note 5: C PD determines the no load dynamic power consumption, PD=CPD VCC2 f+ICC VCC, and the no load dynamic current consumption, IS=CPD VCC f+ICC. www.fairchildsemi.com 4 MM74HCT164 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Package Number M14A 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D 5 www.fairchildsemi.com MM74HCT164 8-Bit Serial-in/Parallel-out Shift Register Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N14A LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.