Revised July 2003 MM74HC4514 4-to-16 Line Decoder with Latch General Description Features The MM74HC4514 utilizes advanced silicon-gate CMOS technology, which is well suited to memory address decoding or data routing application. It possesses high noise immunity and low power dissipation usually associated with CMOS circuitry, yet speeds comparable to low power Schottky TTL circuits. It can drive up to 10 LS-TTL loads. ■ Typical propagation delay: 18 ns ■ Low quiescent power: 80 µA maximum (74HC Series) ■ Low input current: 1 µA maximum ■ Fanout of 10 LS-TTL loads (74HC Series) The MM74HC4514 contain a 4-to-16 line decoder and a 4bit latch. The latch can store the data on the select inputs, thus allowing a selected output to remain HIGH even though the select data has changed. When the LATCH ENABLE input to the latches is HIGH the outputs will change with the inputs. When LATCH ENABLE goes LOW the data on the select inputs is stored in the latches. The four select inputs determine which output will go HIGH provided the INHIBIT input is LOW. If the INHIBIT input is HIGH all outputs are held LOW thus disabling the decoder. The MM74HC4514 is functionally and pinout equivalent to the CD4514BC and the MC1451BC. All inputs are protected against damage due to static discharge diodes from VCC and ground. Ordering Code: Order Number Package Number MM74HC4514WM M24B MM74HC4514MTC MTC24 MM74HC4514N N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2003 Fairchild Semiconductor Corporation DS005215 www.fairchildsemi.com MM74HC4514 4-to-16 Line Decoder with Latch February 1984 MM74HC4514 Connection Diagram Truth Table Data Inputs Top View LE Inhibit D C B A Selected Output High H L L L H L L L L L S0 L H H L L S1 L H L H L S2 L L H H H S3 L L H L L S4 H L L H L H S5 H L L H H L S6 H L L H H H S7 H L H L L L S8 H L H L L H S9 H L H L H L S10 H L H L H H S11 H L H H L L S12 H L H H L H S13 H L H H H L S14 H L H H H H S15 X H X X X X Outputs = 0 L L X X X X All Latched Logic Diagram www.fairchildsemi.com 2 Data Recommended Operating Conditions (Note 2) −0.5 to +7.0V Supply Voltage (VCC) DC Input Voltage (VIN) −1.5 to VCC +1.5V DC Output Voltage (VOUT) −0.5 to VCC +0.5V Clamp Diode Current (IIK, IOK) ±20 mA DC Output Current, per pin (IOUT) ±25 mA DC VCC or GND Current, per pin (ICC) ±50 mA Max 2 6 V DC Input or Output Voltage 0 VCC V −40 +85 °C (tr, tf) VCC = 2.0V 1000 ns VCC = 4.5V 500 ns VCC = 6.0V 400 ns Input Rise or Fall Times Power Dissipation (PD) (Note 3) 600 mW S.O. Package only 500 mW Note 1: Maximum Ratings are those values beyond which damage to the device may occur. Lead Temperature (TL) DC Electrical Characteristics Symbol VIH VIL VOH Parameter Note 2: Unless otherwise specified all voltages are referenced to ground. 260°C (Soldering 10 seconds) Conditions Units (VIN, VOUT) Operating Temperature Range (TA) −65°C to +150°C Storage Temperature Range (TSTG) Min Supply Voltage (VCC) Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C. (Note 4) VCC TA = 25°C Typ TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits Minimum HIGH Level 2.0V 1.5 1.5 1.5 Input Voltage 4.5V 3.15 3.15 3.15 6.0V 4.2 4.2 4.2 Maximum LOW Level 2.0V 0.5 0.5 0.5 Input Voltage 4.5V 1.35 1.35 1.35 6.0V 1.8 1.8 1.8 1.9 Minimum HIGH Level VIN = VIH or VIL 2.0V 2.0 1.9 1.9 Output Voltage |IOUT | ≤ 20 µA 4.5V 4.5 4.4 4.4 4.4 6.0V 6.0 5.9 5.9 5.9 Units V V V VIN = VIH or VIL VOL |IOUT | ≤ 4.0 mA 4.5V 4.2 3.98 3.84 3.7 |IOUT | ≤ 5.2 mA 6.0V 5.7 5.48 5.34 5.2 Maximum LOW Level VIN = VIH or VIL 2.0V 0 0.1 0.1 0.1 Output Voltage |IOUT | ≤ 20 µA 4.5V 0 0.1 0.1 0.1 6.0V 0 0.1 0.1 0.1 V V VIN = VIH or VIL |IOUT | ≤ 4.0 mA 4.5V 0.2 0.26 0.33 0.4 |IOUT | ≤ 5.2 mA 6.0V 0.2 0.26 0.33 0.4 6.0V ±0.1 ±1.0 ±1.0 µA 6.0V 8.0 80 160 µA IIN Maximum Input Current VIN = VCC or GND ICC Maximum Quiescent VIN = VCC or GND Supply Current IOUT = 0 µA V Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. 3 www.fairchildsemi.com MM74HC4514 Absolute Maximum Ratings(Note 1) MM74HC4514 AC Electrical Characteristics VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns Symbol Parameter Conditions Typ Guaranteed Limit Units tPHL, tPLH Maximum Propagation Delay Data to Output 18 30 ns tPHL Maximum Propagation Delay LE to Output 18 30 ns tPLH Maximum Propagation Delay LE to Output 24 40 ns tPHL Maximum Propagation Delay Inhibit to Output 16 30 ns tPLH Maximum Propagation Delay Inhibit to Output 24 40 ns ts Minimum Setup Time, Date to LE 20 ns tH Minimum Hold Time, LE to Data 5 ns tW Minimum Pulse Width, Latch Enable 16 ns AC Electrical Characteristics VCC = 2.0V − 6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol Parameter tPHL, tPLH Maximum Propagation tPLH tPHL tPLH ts tH tW CPD TA = 25°C VCC Typ 80 175 220 263 18 35 44 53 6.0V 16 30 38 45 Maximum Propagation 2.0V 80 175 220 263 Delay LE to Output 4.5V 19 35 44 53 6.0V 17 30 38 45 Maximum Propagation 2.0V 120 230 290 343 Delay LE to Output 4.5V 27 46 58 69 6.0V 22 39 49 58 Maximum Propagation 2.0V 70 175 220 263 Delay Inhibit to Output 4.5V 18 35 44 53 6.0V 16 30 38 45 Maximum Propagation 2.0V 120 230 290 343 Delay Inhibit to Output 4.5V 27 46 58 69 6.0V 22 39 49 58 Minimum Setup Time, 2.0V 100 125 150 Data to LE 4.5V 20 25 30 6.0V 17 21 25 Minimum Hold Time, 2.0V 5 5 5 LE to Data 4.5V 5 5 5 6.0V 5 5 5 Minimum Pulse Width, 2.0V 80 100 120 Latch Enable 4.5V 16 20 24 6.0V 14 17 20 Power Dissipation 290 Maximum Input 5 Capacitance www.fairchildsemi.com 4 ns ns ns ns ns ns ns ns pF 10 10 10 Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + I CC. 2 Units Guaranteed Limits 4.5V Capacitance (Note 5) CIN TA= −40 to 85°C TA = −55 to 125°C 2.0V Delay Data to Output tPHL Conditions pF MM74HC4514 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M24B 5 www.fairchildsemi.com MM74HC4514 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC24 www.fairchildsemi.com 6 MM74HC4514 4-to-16 Line Decoder with Latch Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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