Revised May 2005 MM74HC273 Octal D-Type Flip-Flops with Clear General Description Features The MM74HC273 edge triggered flip-flops utilize advanced silicon-gate CMOS technology to implement D-type flipflops. They possess high noise immunity, low power, and speeds comparable to low power Schottky TTL circuits. This device contains 8 master-slave flip-flops with a common clock and common clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the LOW-to-HIGH transition of the CLOCK input. The CLEAR input when LOW, sets all outputs to a low state. Each output can drive 10 low power Schottky TTL equivalent loads. The MM74HC273 is functionally as well as pin compatible to the 74LS273. All inputs are protected from damage due to static discharge by diodes to VCC and ground. ■ Typical propagation delay: 18 ns ■ Wide operating voltage range ■ Low input current: 1 PA maximum ■ Low quiescent current: 80 PA (74 Series) ■ Output drive: 10 LS-TTL loads Ordering Code: Order Number Package Number MM74HC273WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC273SJ MM74HC273MTC MM74HC273N MTC20 N20A Package Description 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Top View © 2005 Fairchild Semiconductor Corporation DS005331 www.fairchildsemi.com MM74HC273 Octal D-Type Flip-Flops with Clear September 1983 MM74HC273 Truth Table Logic Diagram (Each Flip-Flop) Inputs Outputs Clear Clock D L X X Q L H H H H n n L L H L X Q0 H HIGH Level (Steady State) L LOW Level (Steady State) X Don’t Care n Transition from LOW-to-HIGH level Q0 The level of Q before the indicated steady state input conditions were established www.fairchildsemi.com 2 Recommended Operating Conditions Supply Voltage (VCC ) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) 0.5 to 7.0V 1.5 to VCC 1.5V 0.5 to VCC 0.5V r20 mA r25 mA r50 mA 65qC to 150qC Supply Voltage (VCC) 600 mW S.O. Package only 500 mW (VIN, VOUT) Operating Temperature Range (TA) Symbol VIH VIL VOH Parameter Conditions 0 VCC V 40 85 qC (tr, tf) VCC 2.0V 1000 ns VCC 4.5V 500 ns VCC 6.0V 400 ns Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating — plastic “N” package: 12 mW/qC from 65qC to 85qC. (Note 4) VCC TA 25qC Typ TA 40 to 85qC TA 55 to 125qC Guaranteed Limits Units Minimum HIGH Level 2.0V 1.5 1.5 1.5 Input Voltage 4.5V 3.15 3.15 3.15 V 6.0V 4.2 4.2 4.2 V V V Maximum LOW Level 2.0V 0.5 0.5 0.5 Input Voltage 4.5V 1.35 1.35 1.35 V 6.0V 1.8 1.8 1.8 V Minimum HIGH Level VIN Output Voltage |IOUT| d 20 PA VIH or VIL 2.0V 2.0 1.9 1.9 1.9 V 4.5V 4.5 4.4 4.4 4.4 V 6.0V 6.0 5.9 5.9 5.9 V |IOUT| d 4.0 mA 4.5V 4.2 3.98 3.84 3.7 V |IOUT| d 5.2 mA 6.0V 5.7 5.48 5.34 5.2 V VIN VOL V Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. 260qC DC Electrical Characteristics Units 6 Input Rise or Fall Times Lead Temperature (TL) (Soldering 10 seconds) Max 2 DC Input or Output Voltage Power Dissipation (PD) (Note 3) Min VIH or VIL Maximum LOW Level VIN VIH or VIL Output Voltage |IOUT| d 20 PA 2.0V 0 0.1 0.1 0.1 V 4.5V 0 0.1 0.1 0.1 V 6.0V 0 0.1 0.1 0.1 V |IOUT| d 4 mA 4.5V 0.2 0.26 0.33 0.4 V |IOUT| d 5.2 mA 6.0V 0.2 0.26 0.33 0.4 V VIN VCC or GND 6.0V r0.1 r1.0 r1.0 PA VCC or GND 6.0V 8 80 160 PA VIN IIN Maximum Input ICC Maximum Quiescent VIN Supply Current IOUT VIH or VIL Current 0 PA Note 4: For a power supply of 5V r10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. 3 www.fairchildsemi.com MM74HC273 Absolute Maximum Ratings(Note 1) (Note 2) MM74HC273 AC Electrical Characteristics VCC 5V, TA 25qC, CL 15 pF, tr Symbol tf 6 ns Parameter Conditions Guaranteed Typ Limit Units fMAX Maximum Operating Frequency 50 30 MHz tPHL, tPLH Maximum Propagation 18 27 ns 18 27 ns 10 20 ns 10 20 ns 2 0 ns 10 16 ns Delay, Clock to Output tPHL Maximum Propagation Delay, Clear to Output Minimum Removal Time, tREM Clear to Clock ts Minimum Setup Time Data to Clock tH Minimum Hold Time Clock to Data Minimum Pulse Width tW Clock or Clear AC Electrical Characteristics CL 50 pF, tr Symbol fMAX tPHL, tPLH tPHL tREM tf 6 ns (unless otherwise specified) Parameter Conditions tH tW tr, tf TA 40 to 85qC TA 55 to 125qC Guaranteed Limits Units 2.0V 16 5 4 3 MHz 4.5V 74 27 21 18 MHz 6.0V 78 31 24 20 MHz Maximum Propagation 2.0V 38 135 170 205 ns Delay, Clock to Output 4.5V 14 27 34 41 ns 6.0V 12 23 29 35 ns Maximum Propagation 2.0V 42 135 170 205 ns Delay, Clear to Output 4.5V 19 27 34 41 ns 6.0V 18 23 29 35 ns 2.0V 0 25 32 37 ns Minimum Removal Time 4.5V 0 5 6 7 ns 6.0V 0 4 5 6 ns Minimum Setup Time 2.0V 26 100 125 150 ns Data to Clock 4.5V 7 20 25 30 ns 6.0V 5 17 21 25 ns Minimum Hold Time 2.0V 15 0 0 0 ns Clock to Data 4.5V 6 0 0 0 ns 6.0V 4 0 0 0 ns Minimum Pulse Width 2.0V 34 80 100 120 ns Clock or Clear 4.5V 11 16 20 24 ns 6.0V 10 14 18 20 ns Maximum Input Rise and 2.0V 1000 1000 1000 ns Fall Time, Clock 4.5V 500 500 500 ns ns 400 400 400 Maximum Output Rise 2.0V 28 75 95 110 ns and Fall Time 4.5V 11 15 19 22 ns 9 13 16 19 6.0V CPD TA Frequency 6.0V tTHL, tTLH 25qC Typ Maximum Operating Clear to Clock ts VCC Power Dissipation (per flip-flop) 45 ns pF Capacitance (Note 5) CIN Maximum Input 7 10 10 10 Capacitance Note 5: CPD determines the no load dynamic power consumption, PD IS CPD VCC f ICC. www.fairchildsemi.com CPD VCC2f ICC VCC, and the no load dynamic current consumption, 4 pF MM74HC273 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com MM74HC273 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 6 MM74HC273 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 7 www.fairchildsemi.com MM74HC273 Octal D-Type Flip-Flops with Clear Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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