[AKD4686-B] AKD4686-B AK4686 Evaluation Board Rev.0 FEATURE AKD4686-B is an evaluation board for AK4686, a single chip 24bit CODEC that has one stereo ADC and two stereo DAC. This board has interfaces with AKM’s evaluation boards for A/D converter and D/A converter and makes easy to evaluate AK4686. Also this board has the digital audio interface and then achieves the interface with digital audio systems via RCA connector. Ordering guide AKD4686-B --- Evaluation Board for AK4686 (Cable for connecting with printer port of IBM-AT compatible PC and control software are packed with this. This control software does not operate on Windows NT.) FUNCTION On-board clock generators (AK4118 x 2) Compatible with 2 types of digital audio interface - RCA (S/PDIF) input/output - 10pin headers for interfacing with external data source (x2) RCA connectors for clock input with external clock source 10pin header for register control GND +5V +3.3V Regulator Control Data 10pin Header EX2 AK4118 (DIR) RCA IN PORT 2 10pin Header LOUT1/ROUT1 AK4686 LOUT2/ROUT2 PORT 1 10pin Header AK4118 (DIT/DIR) RCA OUT RCA IN EX1 LIN / RIN Figure 1. AKD4686-B Block Diagram (* Circuit diagram and PCB layout are attached at the end of this manual.) < KM103800> 2010/08 -1- [AKD4686-B] EVALUATION BOARD MANUAL Operating sequence 1. Set up power supply lines. Name of Color of Voltage Jack Jack +5V Red +4.5∼+5.5V AVDD1 Orange +3.0∼+3.6V AVDD2 Orange +3.0∼+3.6V DVDD Orange +3.0∼+3.6V CVDD Orange +3.0∼+3.6V D3.3V Orange +3.0∼+3.6V VSS1 VSS2 VSS3 VSS4 DGND Black Black Black Black Black 0V 0V 0V 0V 0V Used for Comment and attention Regulator T2, T5 Should be always connected Should be open when JP40 (AVDD1_SEL) is set to REG side. AVDD1 of AK4686 Should be connected when JP40 (AVDD1_SEL) is set to AVDD1 side. Should be open when JP41 (AVDD2_SEL) is set to REG side. AVDD2 of AK4686 Should be connected when JP41 (AVDD2_SEL) is set to AVDD2 side. Should be open when JP42 (DVDD_SEL) is set to REG side. DVDD of AK4686 Should be connected when JP42 (DVDD_SEL) is set to DVDD side. Should be connected when default. CVDD of AK4686 Should be open in case of using regulator T2 when R85 is short and L7 is open. Should be open when JP45 (D3.3V_SEL) Power supply of is set to REG side. Should be connected when JP45 logic (D3.3V_SEL) is set to D3.3V side. Analog Ground Should be always connected Analog Ground Should be always connected Analog Ground Should be always connected Analog Ground Should be always connected Digital Ground Should be always connected Table 1. Power supply lines Default +5V Open Open Open +3.3V Open 0V 0V 0V 0V 0V Each supply line should be distributed from the power supply unit. 2. Set up evaluation mode and jumper pins. (Refer to the following item.) 3. Connect cables. (Refer to the following item.) 4. Power on. The AK4686 (U1) should be reset once bringing SW1 (PDN) “L” upon power-up. Keep “H” during normal operaion. 5. Set up control software registers. (Refer to the following item.) < KM103800> 2010/08 -2- [AKD4686-B] Evaluation modes (1) DAC with external DIR (Synchronous mode) 1. Connection of connector For digital (S/PDIF) input, RCA connectors J12 (PORT1 RX0) and J15 (PORT2 RX0) are available. For analog output, RCA connectors J5 (LOUT1)/JP6 (ROUT1), J7 (LOUT2)/J8 (ROUT2) are available. 2. Setting of jumper pin Setting of interface signal of PORT1: AK4118 (U4) is as follows. Jumper JP19 XTI1 JP20 MCKO_SEL1 JP21 MCLK1_SEL JP22 BICK1_SEL JP23 LRCK1_SEL JP50 SDTI1 Setting Open MCKO1 Short Short Short Short (Default) Table 2. Setting of interface signal of PORT1: AK4118 (U4) (1/3) Setting of interface signal of PORT2: AK4118 (U7) is as follows. Jumper JP26 XTI2 JP27 MCKO_SEL2 JP28 MCLK2_SEL JP29 BICK2_SEL JP30 LRCK2_SEL JP31 SDTI2_SEL Setting Open Don’t care MCDIR1 BIDIR1 LRDIR1 SDDIR1 Table 3. Setting of interface signal of PORT2: AK4118 (U7) (1/3) 3. Setting of toggle switch Switch SW2 SW5 SW6 SW7 Setting H L H H Table 4. Setting of interface signal of PORT1, PORT2: AK4118 (U4,U7) (2/3) 4. Setting of DIP switch Switch Setting SW3 DIF0 DIF1 DIF2 CM0 OCKS0 OCKS1 H L H L L H Table 5. Setting of interface signal of PORT1: AK4118 (U4) (3/3) Switch Setting SW4 DIF0 DIF1 DIF2 CM0 OCKS0 OCKS1 Don’t care Don’t care Don’t care Don’t care Don’t care Don’t care Table 6. Setting of interface signal of PORT2: AK4118 (U7) (3/3) < KM103800> 2010/08 -3- [AKD4686-B] (2) DAC with external DIR (Asynchronous mode) 1. Connection of connector For digital (S/PDIF) input, RCA connectors J12 (PORT1 RX0) and J15 (PORT2 RX0) are available. For analog output, RCA connectors J5 (LOUT1)/JP6 (ROUT1), J7 (LOUT2)/J8 (ROUT2) are available. 2. Setting of jumper pin Setting of interface signal of PORT1: AK4118 (U4) is as follows. Jumper JP19 XTI1 JP20 MCKO_SEL1 JP21 MCLK1_SEL JP22 BICK1_SEL JP23 LRCK1_SEL JP50 SDTI1 Setting Open MCKO1 Short Short Short Short (Default) Table 7. Setting of interface signal of PORT1: AK4118 (U4) (1/3) Setting of interface signal of PORT2: AK4118 (U7) is as follows. Jumper JP26 XTI2 JP27 MCKO_SEL2 JP28 MCLK2_SEL JP29 BICK2_SEL JP30 LRCK2_SEL JP31 SDTI2_SEL Setting Open MCKO1 MCDIR2 BIDIR2 LRDIR2 SDDIR2 (Default) Table 8. Setting of interface signal of PORT2: AK4118 (U7) (1/3) 3. Setting of toggle switch Switch SW2 SW5 SW6 SW7 Setting H H H H Table 9. Setting of interface signal of PORT1, PORT2: AK4118 (U4, U7) (2/3) 4. Setting of DIP switch Switch Setting SW3 DIF0 DIF1 DIF2 CM0 OCKS0 OCKS1 H L H L L H (Default) Table 10. Setting of interface signal of PORT1: AK4118 (U4) (3/3) Switch Setting SW4 DIF0 DIF1 DIF2 CM0 OCKS0 OCKS1 H L H L L H (Default) Table 11. Setting of interface signal of PORT2: AK4118 (U7) (3/3) < KM103800> 2010/08 -4- [AKD4686-B] (3) ADC with external DIT 1. Connection of connector For analog input, RCA connector JL1(LIN1), JL2(LIN2), JL3(LIN3), JL4(LIN4), JL5(LIN5), JL6(LIN6) and JR1(RIN1), JR2(RIN2), JR3(RIN3), JR4(RIN4), JR5(RIN5), JR6(RIN6) are available. For digital (S/PDIF) output, RCA connector J13 (PORT1 TX1) is available. 2. Setting of jumper pin Setting of interface signal of PORT1: AK4118 (U4) is as follows. X1 (24.576MHz) is used as Clock (512fs) . Jumper JP19 XTI1 JP20 MCKO1_SEL JP21 MCLK1_SEL JP22 BICK1_SEL JP23 LRCK1_SEL JP24 SDTO1_SEL Setting Open MCKO1 Short Short Short Short (Default) Table 12. Setting of interface signal of PORT1: AK4118 (U4) (1/3) 3. Setting of toggle switch Switch SW2 SW5 Setting H L Table 13. Setting of reset of PORT1 AK4118 (U4) (2/3) 4. Setting of DIP switch Switch Setting DIF0 DIF1 DIF2 SW3 CM0 H L H H OCKS0 OCKS1 MS1 L H L Table 14. Setting of interface signal of PORT1: AK4118 (U4) (3/3) < KM103800> 2010/08 -5- [AKD4686-B] Register control AKD4686-B can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT3 (uP-I/F) to PC by 10-line flat cable packed with this. Take care of the direction of connector. 10 PORT3 UP-I/F 9 SCL Connect SDA PC SDA (ACK) 1 2 RED 10-wire flat cable 10-pin connector AKD4686-B 10-pin header Figure 2. PORT1 pin layout Set-up DIP switch (SW3, 4) No. SW3-1 SW3-2 SW3-3 Name DIF0 DIF1 DIF2 Content SW3-4 CM0 SW3-6 SW3-7 OCKS0 OCKS1 SW3-8 MS1 SW4-1 SW4-2 SW4-3 DIF0 DIF1 DIF2 Default ON OFF ON Setting of AK4118 Audio Interface Format (Refer Table 16.) Selection of AK4118 Clock Mode (Clock Source) (Refer Table 17.) Selection of AK4118 Master Clock Output frequency (Refer Table 18.) PORT1 Master Mode/Slave Mode Switch (Refer to the AK4686’s datasheet) OFF ON Setting of AK4118 Audio Interface Format (Refer Table 16.) ON OFF ON Selection of AK4118 Clock Mode (Clock Source) (Refer Table 17.) OCKS0 Selection of AK4118 Master Clock Output frequency (Refer Table 18.) OCKS1 Table 15. Set up modes of AK4118 (U4, U7) and AK4686 (U1) SW4-4 CM0 SW4-6 SW4-7 Mode DIF2 DIF1 DIF0 DAUX SDTO 0 1 2 3 4 5 6 7 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 24bit, Left justified 16bit, Right justified 24bit, Left justified 18bit, Right justified 24bit, Left justified 20bit, Right justified 24bit, Left justified 24bit, Right justified 24bit, Left justified 24bit, Left justified 24bit, I2S 24bit, I2S 24bit, Left justified 24bit, Left justified 24bit, I2S 24bit, I2S Table 16. AK4118 Audio Interface Format Mode 0 1 CM0 0 1 PLL X'tal Clock source SDTO ON ON PLL RX OFF ON X'tal DAUX Table 17. AK4118 Clock Mode (Clock Source) < KM103800> OFF OFF OFF OFF ON LRCK I/O H/L O H/L O H/L O H/L O H/L O L/H O H/L I L/H I BICK 64fs 64fs 64fs 64fs 64fs 64fs 64-128fs 64-128fs I/O O O O O O O I I <Default> <Default> 2010/08 -6- [AKD4686-B] No. 0 1 2 3 OCKS1 0 0 1 1 OCKS0 MCKO1 MCKO2 X’tal fs (max) 0 256fs 256fs 256fs 96 kHz 1 256fs 128fs 256fs 96 kHz 0 512fs 256fs 512fs 48 kHz 1 128fs 64fs 128fs 192 kHz Table 18. AK4118 Master Clock Output Frequency <Default> Toggle switch [SW1] PDN: A switch for power down reset of AK4686 (U1). Keep “H” during operation of AK4686 (U1). Power down reset of AK4686 will be done by setting SW1 to “L” once, after power on. [SW2] AK4118 (U4)-PDN: A switch for power down reset of AK4118 (U4). Keep “H” during operation of AK4118 (U4). Power down reset of AK4118 (U4) will be done by setting SW2 to “L” once, after power on. [SW5] AK4118 (U7)-PDN: A switch for power down reset of AK4118 (U7). Keep “H” during operation of AK4118 (U7). Power down reset of AK4118 (U7) will be done by setting SW5 to “L” once, after power on. [SW6] MT1N: A switch for LOUT1/ROUT1 mute control. Keep SW6 “H” during normal operation of AK4686 (U1)’s DAC1. Analog output will be muted by setting SW6 to “L”. Refer to Page 20 of AK4686’s datasheet for analog soft mute function of AK4686. [SW7] MT2N: A switch for LOUT2/ROUT2 mute control. Keep SW7 “H” during normal operation of AK4686 (U1)’s DAC2. Analog output will be muted by setting SW7 to “L”. Refer to Page 20 of AK4686’s datasheet for analog soft mute function of AK4686. LED indication [LED1] ERF: An error detection for AK4118(U4). It turns on when output of AK4118 (U4): INT0 is “H”. [LED2] ERF: An error detection for AK4118(U7). It turns on when output of AK4118 (U7): INT0 is “H”. < KM103800> 2010/08 -7- [AKD4686-B] Analog Input Circuit C26 JL1 2 3 1 C10 LIN1 LIN4 + + (short) LIN1 2 3 1 (short) VSS1 MR-552LS JL4 LIN4 MR-552LS VSS1 RIN1 C27 2 3 1 JR1 C11 RIN1 + + (short) 2 3 1 RIN4 (short) VSS1 MR-552LS JR4 RIN4 MR-552LS LIN2 (short) C1 2 3 1 VSS1 JL2 C14 LIN2 + + VSS1 2 3 1 LIN5 (short) MR-552LS LIN5 JL5 MR-552LS VSS1 RIN2 C3 2 3 1 VSS1 JR2 RIN2 + + C15 (short) 2 3 1 RIN5 (short) JR5 RIN5 MR-552LS MR-552LS LIN3 (short) C7 2 3 1 VSS1 JL3 C28 LIN3 + + VSS1 2 3 1 LIN6 (short) MR-552LS JL6 LIN6 MR-552LS RIN3 (short) C8 VSS1 2 3 1 JR3 C29 RIN3 + + VSS1 2 3 1 RIN6 (short) MR-552LS JR6 RIN6 MR-552LS VSS1 Figure 3. Analog Input Circuit For analog input, RCA connector: JL1(LIN1), JL2(LIN2), JL3(LIN3), JL4(LIN4), JL5(LIN5), JL6(LIN6) and JR1(RIN1), JR2(RIN2), JR3(RIN3), JR4(RIN4), JR5(RIN5), JR6(RIN6) are available to use. Analog inputs are single-ended and input range of each channel is 2.2Vrms (typ) when AVDD1=3.3Vrms. < KM103800> 2010/08 -8- [AKD4686-B] Analog Output Circuit C30 LOUT1 + (short) R43 (short) + R45 (open) (open) VSS2 VSS2 C31 + + R46 + (short) + VSS2 C35 + (short) + C37 (open) VSS2 LOUT2 MR-552LS R48 R50 J7 VSS2 (short) (open) VSS2 C36 2 3 1 (open) VSS2 ROUT1 MR-552LS R47 R49 J6 VSS2 (short) (open) ROUT2 C33 VSS2 C34 LOUT2 2 3 1 (open) VSS2 LOUT1 VSS2 (short) (open) J5 MR-552LS R44 (short) ROUT1 C32 2 3 1 2 3 1 J8 ROUT2 MR-552LS VSS2 Figure 4. Analog Output Circuit For analog output, RCA connector: J5 (LOUT1), J6 (ROUT1), J7 (LOUT2), J8 (ROUT2) are available to use. Analog outputs are single-ended and output range of each channel is 2Vrms(typ) when AVDD1=AVDD2=3.3Vrms. < KM103800> 2010/08 -9- [AKD4686-B] Digital Input Circuit (External DIR: PORT1 RX0, PORT2 RX0) J12 C38 PORT1 RX0 2 3 1 R55 DGND 2 3 1 MR-552LS DGND C49 PORT2 RX0 0.1u 75 MR-552LS J15 DGND R62 75 0.1u DGND Figure 5. Digital Input Circuit (External DIR) For digital input, RCA connector: J12 (PORT1 RX0), J15 (PORT2 RX0) are available. Digital Output Circuit (External DIT: PORT1 TX1) J13 T1 DA02F 4 8 PORT1 TX1 MR-552LS 2 3 1 DGND 1 5 R59 R60 240 150 DGND Figure 6. Digital Output Circuit (External DIT) For digital output, RCA connector: J13 (PORT1 TX1) is available. < KM103800> 2010/08 - 10 - [AKD4686-B] Control Soft Manual ■ Evaluation Board and Control Soft Settings 1. Set an evaluation board properly. 2. Connect the evaluation board to an IBM PC/AT compatible PC by a 10wire flat cable. Be aware of the direction of the 10pin header. When running this control soft on the Windows 2000/XP, the driver which is included in the CD must be installed. Refer to the “Driver Control Install Manual for AKM Device Control Software” for installing the driver. When running this control soft on the windows 95/98/ME, driver installing is not necessary. This control soft does not support the Windows NT. 3. Proceed evaluation by following the process below. ■ Operation Screen 1. Start up the control program following the process above. The operation screen is shown below. < KM103800> 2010/08 - 11 - [AKD4686-B] ■ Operation Overview Function, register map and testing tool can be controlled by this control soft. These controls are selected by upper tabs. Buttons which are frequently used such as register initializing button “Write Default”, are located outside of the switching tab window. Refer to the “■ Dialog Boxes” for details of each dialog box setting. 1. [Port Reset]: For when connecting to USB I/F board (AKDUSBIF-A) Click this button after the control soft starts up when connecting USB I/F board (AKDUSBIF-A). 2. [Write Default]: Register Initializing When the device is reset by a hardware reset, use this button to initialize the registers. 3. [All Write]: Executing write commands for all registers displayed. 4. [All Read]: Executing read commands for all registers displayed. 5. [Save]: Saving current register settings to a file. 6. [Load]: Executing data write from a saved file. 7. [All Req Write]: “All Req Write” dialog box is popped up. 8. [Data R/W]: “Data R/W” dialog box is popped up. 9. [Sequence]: “Sequence” dialog box is popped up. 10. [Sequence(File)]: “Sequence(File)” dialog box is popped up. 11. [Read]: Reading current register settings and display on to the Register area (on the right of the main window). This is different from [All Read] button, it does not reflect to a register map, only displaying hexadecimal. < KM103800> 2010/08 - 12 - [AKD4686-B] ■ Tab Functions 1. [REG 0H∼5H]: Register Map This tab is for a register writing and reading. Each bit on the register map is a push-button switch. Button Down indicates “H” or “1” and the bit name is in red (when read only it is in deep red). Button Up indicates “L” or “0” and the bit name is in blue (when read only it is in gray) Grayout registers are Read Only registers. They can not be controlled. The registers which is not defined in the datasheet are indicated as “---”. < KM103800> 2010/08 - 13 - [AKD4686-B] [Write]: Data Writing Dialog It is for when changing two or more bits on the same address at the same time. Click [Write] button located on the right of the each corresponded address for a pop-up dialog box. When checking the checkbox, the register will be “H” or “1”, when not checking the register will be “L” or ”0”. Click [OK] to write setting value to the registers, or click [Cancel] to cancel this setting. [Read]: Data Read Click [Read] button located on the right of the each corresponded address to execute register reading. After register reading, the display will be updated regarding to the register status. Button Down indicates “H” or “1” and the bit name is in red (when read only it is in deep red). Button Up indicates “L” or “0” and the bit name is in blue (when read only it is in gray) Please be aware that button statuses will be changed by Read command. < KM103800> 2010/08 - 14 - [AKD4686-B] 2. [Tool]: Testing Tools This tab screen is for evaluation testing tool. Click buttons for each testing tool. < KM103800> 2010/08 - 15 - [AKD4686-B] ■ Dialog Boxes 1. [All Req Write]: All Req Write dialog box Click [All Reg Write] button in the main window to open register setting files. Register setting files saved by [SAVE] button can be applied. [Open (left)]: Selecting a register setting file (*.akr). [Write]: Executing register writing. [Write All]: Executing all register writings. Writings are executed in descending order. [Help]: Help window is popped up. [Save]: Saving the register setting file assignment. The file name is “*.mar”. [Open (right)]: Opening a saved register setting file assignment “*. mar”. [Close]: Closing the dialog box and finish the process. *Operating Suggestions (1) Those files saved by [Save] button and opened by [Open] button on the right of the dialog “*.mar” should be stored in the same folder. (2) When register settings are changed by [Save] button in the main window, re-read the file to reflect new register settings. < KM103800> 2010/08 - 16 - [AKD4686-B] 2. [Data R/W]: Data R/W Dialog Box Click the [Data R/W] button in the main window for data read/write dialog box. Data write is available to specified address. Address Box: Input data address in hexadecimal numbers for data writing. Data Box: Input data in hexadecimal numbers. Mask Box: Input mask data in hexadecimal numbers. This is “AND” processed input data. [Write]: Writing to the address specified by “Address” box. [Read]: Reading from the address specified by “Address” box. The result will be shown in the Read Data Box in hexadecimal numbers. [Close]: Closing the dialog box and finish the process. Data writing can be cancelled by this button instead of [Write] button. *The register map will be updated after executing [Write] or [Read] commands. < KM103800> 2010/08 - 17 - [AKD4686-B] 3. [Sequence]: Sequence Dialog Box Click [Sequence] button to open register sequence setting dialog box. Register sequence can be set in this dialog box. Sequence Setting Set register sequence by following process bellow. (1)Select a command Use [Select] pull-down box to choose commands. Corresponding boxes will be valid. < Select Pull-down menu > · No_use: Not using this address · Register: Register writing · Reg(Mask): Register writing (Masked) · Interval: Taking an interval · Stop: Pausing the sequence · End: Finishing the sequence (1) Input sequence [Address]: Data address [Data]: Writing data [Mask]: Mask [Data] box data is ANDed with [Mask] box data. This is the actual writing data. When Mask = 0x00, current setting is hold. When Mask = 0xFF, the 8bit data which is set in the [Data] box is written. When Mask =0x0F, lower 4bit data which is set in the [Data] box is written. Upper 4bit is hold to current setting. < KM103800> 2010/08 - 18 - [AKD4686-B] [ Interval ]: Interval time Valid boxes for each process command are shown bellow. · No_use: None · Register: [Address], [Data], [Interval] · Reg(Mask): [Address], [Data], [Mask], [Interval] · Interval: [Interval] · Stop: None · End: None < KM103800> 2010/08 - 19 - [AKD4686-B] Control Buttons The function of Control Button is shown bellow. [Start]: Executing the sequence [Help]: Opening a help window [Save]: Saving sequence settings as a file. The file name is “*.aks”. [Open]: Opening a sequence setting file “*.aks”. [Close]: Closing the dialog box and finish the process. Stop of the sequence When “Stop” is selected in the sequence, processing is paused and it starts again when [Start] button is clicked. Restarting step number is shown in the “Start Step” box. When finishing the process until the end of sequence, “Start Step” will return to “1”. The sequence can be started from any step by writing the step number to the “Start Step” box. Write “1” to the “Start Step” box and click [Start] button, when restarting the process from the beginning. < KM103800> 2010/08 - 20 - [AKD4686-B] 4. [Sequence(File)]: Sequence Setting File Dialog Box Click [Sequence(File)] button to open sequence setting file dialog box. Those files saved in the “Sequence setting dialog” can be applied in this dialog. [Open (left)]: Opening a sequence setting file (*.aks). [Start]: Executing the sequence setting. [Start All]: Executing all sequence settings. Sequences are executed in descending order. [Help]: Pop up the help window. [Save]: Saving sequence setting file assignment. The file name is “*.mas”. [Open(right)]: Opening a saved sequence setting file assignment “*. mas”. [Close]: Closing the dialog box and finish the process. *Operating Suggestions (1) Those files saved by [Save] button and opened by [Open] button on the right of the dialog “*.mas” should be stored in the same folder. (2) When “Stop” is selected in the sequence the process will be paused and a pop-up message will appear. Click “OK” to continue the process. < KM103800> 2010/08 - 21 - [AKD4686-B] Measure Result 1) ADC part [Measurement condition] • Measurement unit : Audio Precision SYS-2722 • MCLK : 512fs • BICK : 64fs • fs : 48kHz • BW : 20Hz∼20kHz (fs=48kHz) • Bit : 24bit • Power Supply : AVDD1=AVDD2=DVDD=CVDD=3.3V • Interface : External DIT (U4) • Temperature : Room Temp Parameter S/(N+D) DR S/N Input signal Measurement filter 1kHz, -1dB 1kHz, -60dB No signal 20kLPF 20kLPF, A-weighted 20kLPF, A-weighted < KM103800> Results Lch 88.1 97.5 97.5 [dB] Rch 87.7 97.4 97.5 2010/08 - 22 - [AKD4686-B] 2) DAC part [Measurement condition] • Measurement unit : Audio Precision SYS-2722 • MCLK : 512fs (fs=48kHz), 256fs (fs=96kHz), 128fs (fs=192kHz) • BICK : 64fs • fs : 48kHz, 96kHz, 192kHz • BW : 20Hz∼20kHz (fs=48kHz), 20Hz∼40kHz (fs=96kHz), 20Hz∼40kHz (fs=192kHz) • Resolution : 24bit • Power Supply : AVDD1=AVDD2=DVDD=CVDD=3.3V • Interface : External DIR (U4) • Temperature : Room Temp fs=48kHz Parameter Input signal Measurement filter S/(N+D) DR DR 1kHz, 0dB 1kHz, -60dB 1kHz, -60dB S/N S/N “0” data “0” data 20kHz SPCL 20kHz SPCL 20kHz SPCL, A-weighted 20kHz SPCL 20kHz SPCL, A-weighted Results Lch 88.4 97.2 100.0 [dB] Rch 88.9 97.5 99.9 98.7 101.0 98.7 101.0 fs=96kHz Parameter Input signal Measurement filter S/(N+D) DR DR 1kHz, 0dB 1kHz, -60dB 1kHz, -60dB S/N S/N “0” data “0” data 40kHz SPCL 40kHz SPCL 40kHz SPCL, A-weighted 40kHz SPCL 40kHz SPCL, A-weighted Results [dB] Lch Rch 87.8 95.0 100.0 88.1 95.1 100.0 96.9 101.7 97.0 101.7 fs=192kHz Parameter Input signal Measurement filter S/(N+D) DR DR 1kHz, 0dB 1kHz, -60dB 1kHz, -60dB S/N S/N “0” data “0” data 40kHz SPCL 40kHz SPCL 40kHz SPCL, A-weighted 40kHz SPCL 40kHz SPCL, A-weighted < KM103800> Results [dB] Lch Rch 87.4 95.1 100.0 87.7 95.2 100.0 96.0 100.8 96.1 100.9 2010/08 - 23 - [AKD4686-B] 1.ADC部 (fs=48kHz) +0 -10 -20 -30 -40 -50 d B F S -60 -70 -80 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k 20k 10k 20k Hz Figure 7. FFT (Input Frequency =1kHz, Input Level=-1dBFS) +0 -10 -20 -30 -40 -50 d B F S -60 -70 -80 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k Hz Figure 8. FFT(Input Frequency =1kHz, Input Level=-60dBFS) < KM103800> 2010/08 - 24 - [AKD4686-B] +0 -10 -20 -30 -40 -50 d B F S -60 -70 -80 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 9. FFT(noise floor) -60 -65 -70 -75 -80 d B F S -85 -90 -95 -100 -105 -110 -115 -120 -140 -120 -100 -80 -60 -40 -20 +0 dBr Figure 10. THD + N vs Input Level (Input Frequency =1kHz) < KM103800> 2010/08 - 25 - [AKD4686-B] -60 -65 -70 -75 -80 -85 d B F S -90 -95 -100 -105 -110 -115 -120 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 11. THD + N vs Input Frequency (Input Level=-1.0dBFS) +0 T TT T -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBr Figure 12. Linearity (Input Frequency =1kHz) < KM103800> 2010/08 - 26 - [AKD4686-B] +0 -0.2 -0.4 -0.6 d B F S -0.8 -1 -1.2 -1.4 -1.6 -1.8 -2 20 50 100 200 500 1k 2k 5k 10k 20k 10k 20k Hz Figure 13. Frequency Response (Input Level=-1.0dBFS) -60 TT TT T -70 -80 -90 d B -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k Hz Figure 14. Crosstalk (Input Level=-1.0dBFS) < KM103800> 2010/08 - 27 - [AKD4686-B] 2.DAC部 (DAC fs=48kHz) +0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k 20k 10k 20k Hz Figure 15. FFT(Input Frequency =1kHz, Input Level=0dBFS) +0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k Hz Figure 16. FFT(Input Frequency =1kHz, Input Level=-60dBFS) < KM103800> 2010/08 - 28 - [AKD4686-B] (DAC fs=48kHz) +0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 17. FFT(noise floor) +0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k Hz Figure 18. FFT(out-of-band noise) < KM103800> 2010/08 - 29 - [AKD4686-B] (DAC fs=48kHz) -60 -65 -70 -75 -80 d B r -85 A -95 -90 -100 -105 -110 -115 -120 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Figure 19. THD+N vs Input Level (Input Frequency =1kHz) -60 -65 -70 -75 -80 d B r -85 A -95 -90 -100 -105 -110 -115 -120 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 20. THD+N vs Input Frequency (Input Level=0dBFS) < KM103800> 2010/08 - 30 - [AKD4686-B] (DAC fs=48kHz) +0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Figure 21. Linearity (Input Frequency =1kHz) +1 +0.8 +0.6 +0.4 d B r +0.2 A -0.2 +0 -0.4 -0.6 -0.8 -1 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 22. Frequency Response (Input Level=0dBFS) < KM103800> 2010/08 - 31 - [AKD4686-B] (DAC fs=48kHz) -60 -70 -80 -90 d B -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 23. Cross-talk (Input Level=0dBFS) < KM103800> 2010/08 - 32 - [AKD4686-B] (DAC fs=96kHz) +0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k 20k 40k 20k 40k Hz Figure 24. FFT(Input Frequency =1kHz, Input Level=0dBFS) +0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k Hz Figure 25. FFT(Input Frequency =1kHz, Input Level=-60dBFS) < KM103800> 2010/08 - 33 - [AKD4686-B] (DAC fs=96kHz) +0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k 20k 40k Hz Figure 26. FFT(noise floor) +0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k Hz Figure 27. FFT (Out of band Noise) < KM103800> 2010/08 - 34 - [AKD4686-B] (DAC fs=96kHz) -60 T -65 -70 -75 -80 d B r -85 A -95 -90 -100 -105 -110 -115 -120 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Figure 28. THD+N vs Input Level (Input Frequency =1kHz) -60 -65 -70 -75 -80 d B r -85 A -95 -90 -100 -105 -110 -115 -120 20 50 100 200 500 1k 2k 5k 10k 20k 40k Hz Figure 29. THD+N vs fin (Input Level=0dBFS) < KM103800> 2010/08 - 35 - [AKD4686-B] (DAC fs=96kHz) +0 -10 -20 -30 -40 -50 d B r -60 -70 -80 A -90 -100 -110 -120 -130 -140 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Figure 30. Linearity (Input Frequency =1kHz) +1 +0.8 +0.6 +0.4 d B r +0.2 A -0.2 +0 -0.4 -0.6 -0.8 -1 20 50 100 200 500 1k 2k 5k 10k 20k 40k Hz Figure 31. Frequency Response (Input Level=0dBFS) < KM103800> 2010/08 - 36 - [AKD4686-B] (DAC fs=96kHz) -60 -70 -80 -90 d B -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k 20k 40k Hz Figure 32. Cross-talk (Input Level=0dBFS) < KM103800> 2010/08 - 37 - [AKD4686-B] (DAC fs=192kHz) +0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k 20k 80k 20k 80k Hz Figure 33. FFT(Input Frequency =1kHz, Input Level=0dBFS) +0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k Hz Figure 34. FFT(Input Frequency =1kHz, Input Level=-60dBFS) < KM103800> 2010/08 - 38 - [AKD4686-B] (DAC fs=192kHz) +0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k 20k 80k Hz Figure 35. FFT(noise floor) +0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k Hz Figure 36. FFT (Out of band Noise) < KM103800> 2010/08 - 39 - [AKD4686-B] (DAC fs=192kHz) -60 T -65 -70 -75 -80 d B r -85 A -95 -90 -100 -105 -110 -115 -120 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Figure 37. THD+N vs Input Level (Input Frequency =1kHz) -60 -65 -70 -75 -80 d B r -85 A -95 -90 -100 -105 -110 -115 -120 20 50 100 200 500 1k 2k 5k 10k 20k 80k Hz Figure 38. THD+N vs Input Frequency (Input Level=0dBFS) < KM103800> 2010/08 - 40 - [AKD4686-B] (DAC fs=192kHz) +0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Figure 39. Linearity (f Input Frequency =1kHz) +1 +0.8 +0.6 +0.4 d B r +0.2 A -0.2 +0 -0.4 -0.6 -0.8 -1 20 50 100 200 500 1k 2k 5k 10k 20k 80k Hz Figure 40. Frequency Response (Input Level=0dBFS) < KM103800> 2010/08 - 41 - [AKD4686-B] (DAC fs=192kHz) -60 -70 -80 -90 d B -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k 20k 80k Hz Figure 41. Cross-talk (Input Level=0dBFS) < KM103800> 2010/08 - 42 - [AKD4686-B] REVISION HISTORY Date (yy/mm/dd) 2010/08/13 Manual Board Reason Revision Revision KM103800 0 First Edition Page Contents IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products. z Descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. You are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKM. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. < KM103800> 2010/08 - 43 - 4 3 BICK2 MCLK2 LRCK2 SDTI2 D TP26 TP25 1 TP24 1 1 1 CVDD TP23 1 BICK2 MCLK2 LRCK2 SDTI2 R27 R26 R25 R23 R18 0 0 0 0 0 PDN TP21 D VSS3 C12 1 TP27 1 PDN 2 10u + 5 C13 VSS3 0.1u C16 C9 2.2u 2.2u VSS4 TP20 VSS2 R92 MT1N 13 VSS2 14 CVEE 15 CN 16 VSS3 17 CP 18 CVDD 19 PDN 20 SDTI2 21 LRCK2 22 MCLK2 23 MS1 ROUT2 11 LOUT2 10 28 MCLK1 ROUT1 9 TP16 U1 29 TP15 MT1N LOUT1 8 30 VSS4 0.1u C2 C4 R3 VSS1 7 AVDD1 6 ROUT1 ROUT1 LOUT1 LOUT1 VSS1 C6 0.1u VSS1 C5 10u TP13 AVDD1 31 VSS4 32 SDTO RIN6 5 RIN6 33 LRCK1 LIN6 4 LIN6 34 BICK1 NC 3 AVDD1 SDTO 1 SDTO TP8 AK4686 DVDD C LOUT2 1 TP14 10u ROUT2 LOUT2 1 MCLK1 MT1N ROUT2 1 SDTI1 AVDD2 1 1 TP17 27 AVDD2 1 1 26 SDTI1 1 VSS4 12 DVDD + TP7 AVDD2 TP18 1 TP5 1 DVDD 0 TP4 MT2N 1 TP6 0 TP19 25 1 R21 MCLK1 0 TP3 C21 10u MS1 1 SDTI1 TP2 0.1u + C R90 0 MT2N 1 R20 MS1 0 BICK2 NC TP1 R91 MT2N VSS2 C17 + 24 1 VSS3 0 R1 LRCK1 1 LRCK1 TP9 0 R2 BICK1 BICK1 1 B TP10 B 0 R19 SDA 1 SDA VSS1 TP11 35 SDA RIN5 2 RIN5 36 SCL LIN5 1 LIN5 0 R17 1 SCL TP12 SCL NC 48 RIN4 47 LIN4 46 NC 45 RIN3 44 LIN3 43 NC 42 RIN2 41 LIN2 40 NC 39 RIN1 38 37 LIN1 0 A A LIN1 RIN1 VSS1 LIN2 RIN2 VSS1 LIN3 RIN3 -44- VSS1 LIN4 RIN4 VSS1 Title Size A3 Date: 5 4 3 2 AKD4686-B-MAIN Document Number Rev 0 AK4686 Friday, August 13, 2010 Sheet 1 1 of 6 4 JL1 (short) + 3 C10 LIN1 LIN4 2 3 1 LIN1 C26 2 JL4 + 5 LIN4 2 3 1 (short) VSS1 1 MR-552LS MR-552LS VSS1 C11 RIN1 C27 (short) VSS1 RIN4 2 3 1 RIN4 2 3 1 RIN1 JR4 + JR1 (short) + D D MR-552LS MR-552LS VSS1 C14 + LIN2 C1 JL2 LIN2 JL5 + (short) (short) VSS1 LIN5 2 3 1 LIN5 2 3 1 MR-552LS MR-552LS VSS1 C15 + (short) RIN2 C3 JR5 + JR2 RIN2 RIN5 2 3 1 RIN5 2 3 1 (short) MR-552LS VSS1 MR-552LS VSS1 C C C7 JL3 C28 LIN3 2 3 1 VSS1 JL6 + + (short) LIN3 LIN6 2 3 1 LIN6 (short) MR-552LS MR-552LS VSS1 C29 + RIN3 C8 JR3 RIN3 RIN6 2 3 1 RIN6 2 3 1 VSS1 JR6 + (short) (short) MR-552LS MR-552LS VSS1 B B C30 R43 C34 J5 LOUT1 C32 (open) R45 (open) + (short) VSS2 C35 (open) J6 ROUT1 2 3 1 VSS2 (short) VSS2 R48 J8 (short) R50 C37 (open) (open) VSS2 LOUT2 2 3 1 MR-552LS VSS2 ROUT2 MR-552LS VSS2 C36 (open) (open) R44 C33 (open) J7 (short) R49 VSS2 (short) R46 R47 LOUT2 VSS2 ROUT1 VSS2 2 3 1 (short) MR-552LS VSS2 C31 LOUT1 + + (short) + (short) ROUT2 2 3 1 MR-552LS VSS2 VSS2 A A Title -45- Size A3 Date: 5 4 3 2 AKD4686-B Document Number Rev 0 Analog Input/Output Friday, August 13, 2010 Sheet 1 2 of 6 4 3 14 5 R32 R33 10k 470 1 U2A 2 D R35 R36 470 3 7 10k R34 100 R37 100 1 SCL 74LS07 14 7 D3.3V 2 U2B 4 D SDA 74LS07 PORT3 A1-10PA-2.54DSA 10 8 6 4 2 DGND 9 7 5 3 1 SCL SDA SDA(ACK) R38 (short) uP-I/F R39 10k R40 10k D3.3V C C C83 D3.3V K D3.3V 1 A 74HC14 H 0.1u L SW1 14 3 74HC14 C25 ATE1D-2M3 MT1N U3A 2 7 10k MT1N C91 ATE1D-2M3 R41 D1 1S1588 14 4 7 74HC14 7 U8B 3 7 14 2 L SW6 B U8A 1 A H 14 10k DGND 0.1u K R31 D4 1S1588 U3B 4 R42 74HC14 100 PDN DGND 0.1u B PDN DGND DGND K D3.3V A L SW7 7 H U8C 6 74HC14 14 A 5 U8D 7 10k 14 R99 D5 1S1588 74HC14 9 8 MT2N A C92 ATE1D-2M3 0.1u Title MT2N -46DGND Size A4 Date: 5 4 3 2 AKD4686-B Document Number INPUT/OUTPUT Friday, August 13, 2010 Sheet 1 3 Rev 0 of 6 5 4 3 2 1 DGND PORT1 RX0 2 0.1u C40 0.1u D3.3V 1 D3.3V 10k DGND U3C 5 D C41 0.47u DGND R57 10k 6 7 D3.3V 74HC14 A DGND R56 14 75 D2 HSU119 U3D 9 8 7 R55 MR-552LS K + 2 3 1 C39 10u C38 14 J12 D 74HC14 L H C42 1 37 IPS0 14 38 PORT1 PDN INT1 R AVDD 39 40 VCOM AVSS 41 42 NC RX0 43 44 RX1 TEST1 45 46 RX2 NC RX3 47 U4 16 15 14 13 12 11 10 9 ATE1D-2M3 R58 U5A 1k 2 74HC04 LED1 ERF INT0 36 PORT1 OCKS0 PORT1 OCKS1 1 K A D3.3V DGND 7 OCKS0 OCKS1 MS1 1 2 3 4 5 6 7 8 48 SW3 DIF0 DIF1 DIF2 CM0 SW2 0.1u PORT1 DIT/DIR/4686 2 NC OCKS0 35 3 DIF0 OCKS1 34 4 TEST2 CM1 33 5 DIF1 CM0 32 6 NC PDN 31 7 DIF2 XTI 30 RP1 9 8 7 6 5 4 3 2 1 C PORT1 CM0 PORT1 OCKS0 PORT1 OCKS1 MS1 DGND C PORT1 CM0 47k AK4118 C43 XTO 29 9 P/SN DAUX 28 10 XTL0 MCKO2 27 C44 5p 2 IPS1 JP19 XTI1 EX1 X1 24.576MHz 8 5p 1 DGND DGND DGND JP20 MCKO_SEL1 MCKO2 JP21 MCLK1_SEL MCLK1 MCKO1 11 XTL1 BICK 26 SDTO 25 JP22 BICK1_SEL BICK1 12 2 2 3 1 MR-552LS T1 DA02F 4 8 1 5 MCKO1 LRCK 24 SDTO SDTI1 JP50 A1-10PA-2.54DSA DGND R59 LRDIR1 BIDIR1 R60 DGND JP24 SDTO1_SEL 150 MCLK1 BICK1 LRCK1 SDTI1 SDTO MCDIR1 240 EX1 J14 14 PORT1 TX1 LRCK1 SDTI1 D3.3V J13 B JP23 LRCK1_SEL 2 C48 10u DGND D3.3V 23 22 DVSS DVDD 21 1 C47 10u C46 0.1u + 20 VOUT UOUT 19 COUT 18 BOUT 17 TX1 16 TX0 15 13 1 C62 0.1u + DGND DVSS TVDD VIN 14 B 1 3 5 7 9 PORT1 2 4 6 8 10 GND GND GND GND U6A A DGND 1 1 BNC JP25 EX150 DGND 2 EX1 SDDIR1 74VHC04 7 2 3 4 5 DGND R61 51 DGND -47- Title Size A3 Date: 5 4 3 2 AKD4686-B Document Number Friday, August 13, 2010 PORT 1 Sheet 1 4 Rev 0 of 6 A 5 4 3 2 DGND PORT2_RX0 0.1u C51 0.1u D3.3V 1 D3.3V K R63 C52 0.47u DGND 11 12 U3F 7 D3.3V 14 U3E 10 74HC14 R64 10k A 10k DGND D3 HSU119 D 13 7 DGND D R62 75 MR-552LS 2 + 2 3 1 C50 10u C49 14 J15 1 H 74HC14 1 IPS0 2 37 14 38 ATE1D-2M3 PORT2 PDN INT1 R AVDD 39 40 VCOM 41 AVSS 42 NC RX0 43 44 RX1 TEST1 45 46 47 NC RX2 16 15 14 13 12 11 10 9 SW5 0.1u INT0 36 NC OCKS0 35 3 DIF0 OCKS1 34 4 TEST2 CM1 33 5 DIF1 CM0 32 6 NC PDN 31 7 DIF2 XTI 30 3 R65 1k U5B 4 74HC04 LED2 ERF K A D3.3V DGND 7 OCKS0 OCKS1 1 2 3 4 5 6 7 8 RX3 DIF0 DIF1 DIF2 CM0 U7 SW4 48 C53 PORT2 OCKS0 PORT2 DIR RP2 D3.3V 9 8 7 6 5 4 3 2 1 C PORT2 CM0 PORT2 OCKS1 PORT2 OCKS0 PORT2 OCKS1 DGND C PORT2 CM0 47k AK4118 C54 5p EX2 IPS1 XTO 29 9 P/SN DAUX 28 10 XTL0 MCKO2 27 C55 5p 2 X2 24.576MHz 8 JP26 XTI2 1 DGND DGND DGND JP27 MCKO_SEL2 DGND JP28 MCLK2_SEL MCKO2 MCKO1 MCDIR1 MCDIR1 MCLK2 BICK 26 SDTO 25 JP29 BICK2_SEL BIDIR1 BIDIR1 JP30 LRCK2_SEL LRDIR1 C56 0.1u 24 23 22 21 20 19 18 17 16 15 14 13 LRDIR1 DGND 1 C58 10u D3.3V + + 2 LRCK2 LRDIR2 C57 0.1u JP31 SDTI2_SEL SDDIR1 SDDIR1 1 B BICK2 BIDIR2 LRCK MCKO1 DVSS DVDD VOUT UOUT COUT DVSS BOUT VIN TX0 12 TVDD B XTL1 TX1 MCDIR2 11 SDTI2 SDDIR2 2 C59 10u DGND D3.3V MCLK2 BICK2 LRCK2 SDTI2 DGND 14 EX2 J16 1 3 BNC JP32 EX250 7 2 3 4 5 A U6B 4 1 3 5 7 9 PORT2 2 4 6 8 10 GND GND GND GND A1-10PA-2.54DSA EX2 A DGND 74VHC04 DGND R66 51 -48- Title Size A3 DGND Date: 5 4 3 2 AKD4686-B Document Number PORT 2 Friday, August 13, 2010 Sheet 1 5 Rev 0 of 6 2 1 TM_+5V D AVDD1 T-45(O) TM_DVDD CVDD1 T-45(O) AVDD2 T-45(O) TM_AVDD1 D3.3V1 T-45(O) TM_AVDD2 1 DVDD1 T-45(O) 1 +5V1 T-45(O) 1 1 3 1 4 1 5 TM_CVDD TM_D3.3V D T2 10u 0.1u + 10u C96 + C97 10u 0.1u VSS4 OUT R98 VSS1 T-45(B) 2 C98 C99 0.1u (short) + VSS3 T-45(B) VSS4 T-45(B) DGND1 T-45(B) 10u VSS4 TM_AVDD1 VSS2 T-45(B) 1 C76 IN 1 (short) C77 0.1u LM1117-3.3V 1 3 1 C78 OUT T5 L5 1 TM_+5V 2 1 C66 + 1 (short) IN GND 3 GND LM1117-3.3V TM_+5V L4 VSS1 VSS2 VSS3 VSS4 DGND TM_D3.3V L1 + C (short) L6 JP40 AVDD1 R72 REG C71 47u AVDD1_SEL + D3.3V C79 AVDD1 R75 R76 R77 (open) (open) (open) C REG 47u DGND (short) VSS1 JP45 (short) D3.3V_SEL D3.3V VSS2 VSS3 VSS3 VSS4 VSS4 R73 R74 (open) (open) VSS1 TM_AVDD2 L3 + (short) JP41 AVDD2 R78 C73 DGND VSS4 VSS1 VSS2 REG 47u AVDD2_SEL VSS2 D3.3V D3.3V (short) AVDD2 D3.3V 11 R85 14 11 7 L7 U2E 10 74LS07 + (short) C85 7 14 TM_CVDD 14 C90 U5D 8 9 74HC04 U5E 10 11 74HC04 DGND DGND 14 U6F 12 11 U6D 8 7 74VHC04 14 14 7 74HC04 (open) DGND 74VHC04 13 74VHC04 7 14 13 7 9 7 9 U2D 8 74LS07 U5F 12 14 14 DVDD 5 74HC04 7 14 14 13 7 (short) U5C 6 U6C 6 0.1u U2C 6 74LS07 14 DVDD_SEL 5 7 47u 14 DVDD R79 REG C72 VSS4 7 JP42 5 7 (short) U2F 12 74LS07 B 7 13 7 0.1u L2 + 14 TM_DVDD 0.1u 0.1u C82 D3.3V C80 C81 B U8E 10 74HC14 U8F 12 74HC14 U6E 10 74VHC04 DGND 47u VSS3 A A CVDD -49- Title Size A3 Date: 5 4 3 2 AKD4686-B Document Number Power Supply Friday, August 13, 2010 Sheet 1 Rev 0 6 of 6 -50- -51- -52- -53- -54- -55-